From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100848+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100848+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270111; cv=none; d=zohomail.com; s=zohoarc; b=De3PQJkfV9uMR1rnJYzyGcOTGmoV6oKSU3gyQUP5PHwHX177iDzA7J/fimbbD9bYCSCMik6KfuGZq6n8rQuUos7HjQ74Ds3HcU3QUQZaORP94EXwc4sdEN49/awoIQ58kaKBMkqwZKc6cnQvbSkhrcRSq+0+UlmXsPTKKjiR/+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270111; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=B5OOTJ4a4/6/orNhWUaICC2foKafq9lHfZRJyoUXong=; b=DJobSEMmntpT/NgTCdPrDkku1G9+hEyRej4xiiW4aeksbTcXPGrjRidcRqohWUngt2uyjZD7HCMnYgkfJd64hB4IP5ArtnSrkFoIpAi7icC1MPxKhxSOiQ0Wp23F0V8GK08QSxxhHrVSmVgK7tGIwQoG182gQQvBTZUnDaEQUe0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100848+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270111036373.6143545914447; Wed, 8 Mar 2023 02:08:31 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id q98MYY1788612x4U32zWnEp2; Wed, 08 Mar 2023 02:08:30 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3463.1678270107601358969 for ; Wed, 08 Mar 2023 02:08:29 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442542" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442542" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862450" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862450" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:28 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 01/14] UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition Date: Wed, 8 Mar 2023 18:07:45 +0800 Message-Id: <20230308100758.669-2-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Cln8iQL7IsmHw6BUYpzgJbCcx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270110; bh=wP7bfz+j+GyH3DNBtHcgja8cXRT+HDj9sBHtVIUmUUo=; h=Cc:Date:From:Reply-To:Subject:To; b=sTPp/MMIKKdb5heCaZi3OeAbqojuQgz9ImtIHRy0JQIilnpDi1orxvFcF74zZRcyt2m Chg9lHK1T6y4qBa0+HXkAeczxJeP6VR2ZnNGD58ZsX5E+TbvAcUZ1DchFYFaeLQUTBvDO pZ/5WOBKlvY79xPO4opovm4/XgodGvvCJIo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270112263100002 Content-Type: text/plain; charset="utf-8" Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) is always FALSE. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 37713ec659..47027917d9 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -375,15 +375,6 @@ PageTableLibMapInLevel ( // we need to change PDPTE[0].ReadWrite =3D 1 and let all P= DE[0-255].ReadWrite =3D 0 in this step. // when PDPTE[0].Nx =3D 1 but caller wants to map [0-2MB] as Nx = =3D 0 (PDT[0].Nx =3D 0) // we need to change PDPTE[0].Nx =3D 0 and let all PDE[0-25= 5].Nx =3D 1 in this step. - if ((ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) && (Mask->Bits.Pre= sent =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1)) { - if (Modify) { - ParentPagingEntry->Pnle.Bits.Present =3D 1; - } - - ChildAttribute.Bits.Present =3D 0; - ChildMask.Bits.Present =3D 1; - } - if ((ParentPagingEntry->Pnle.Bits.ReadWrite =3D=3D 0) && (Mask->Bits.R= eadWrite =3D=3D 1) && (Attribute->Bits.ReadWrite =3D=3D 1)) { if (Modify) { ParentPagingEntry->Pnle.Bits.ReadWrite =3D 1; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100848): https://edk2.groups.io/g/devel/message/100848 Mute This Topic: https://groups.io/mt/97469465/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100849+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100849+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270117; cv=none; d=zohomail.com; s=zohoarc; b=hha6hC6JZMLfnjbsWqCqOuf9zTiSk4hstDzGYvb0ik8i6l8nWI9lNc7PxpIUfeWzLmqULbHGZjcfRRWVodIAelJqHcTxO9Qopeb8rbpFyZLqGgcjZwfcBuDHdq9w3mZz3BEU+gQayH0in2T24vVY+TwMfWCY4FuZPwMJoPDLRJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270117; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=MmzxTlHz0UGhrVfn7Y2zT3uE5YCsjAL++YE9MgaFfHs=; b=ibNOrTmzFpuADccU9KgEvnGexglc1k5wTCt1J4AkqqQrnAearMD3sCSv+EEWoRGF3XqAyIn3tyBbHqdVBvxmKQM+rOQdCIfEKINjI5Va4SC4VtsJW2x6zqP4yxrrl6Mqj7OQcxMoBHH3gNAbP9GkzuyJdYKMdefinLcBZCpXkoY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100849+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270116940626.2791417311407; Wed, 8 Mar 2023 02:08:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7nWuYY1788612xw2lXDYMGew; Wed, 08 Mar 2023 02:08:36 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.3567.1678270115763392569 for ; Wed, 08 Mar 2023 02:08:35 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442578" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442578" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862517" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862517" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:33 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 02/14] UefiCpuPkg/CpuPageTableLib: Add check for input Length Date: Wed, 8 Mar 2023 18:07:46 +0800 Message-Id: <20230308100758.669-3-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Xr3uzf5TuMqY1dTrkJGsdwkex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270116; bh=MyEWjeEsslbtXTv8JnwTntj98gbUZrQ53t2voAd58XE=; h=Cc:Date:From:Reply-To:Subject:To; b=afFkOsisW9ABxQpoJZiwmKma8cFE1sC+ahb1Uks5tfn2xBNmaHWbsdHrlB/1Lb0JJIq zwq8zOdSWf7CTI4J+Bi4z/VJIGlKYIazFAigbTkGn7SPTuQlbqamxjT3vHh5PIHoV5XUE 1isCCMsv1s6ZIp2uUwfo83fvgMv0IQaATUQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270118146100002 Content-Type: text/plain; charset="utf-8" Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 47027917d9..4c9d70fa0a 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -567,6 +567,10 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; =20 + if (Length =3D=3D 0) { + return RETURN_SUCCESS; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100849): https://edk2.groups.io/g/devel/message/100849 Mute This Topic: https://groups.io/mt/97469467/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100850+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100850+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270140; cv=none; d=zohomail.com; s=zohoarc; b=ccAZKFpiLZpRrmUAW440NXeZNuV5DLwrSNpOfEVxvRzuKcJnfIgPVZmOYHNmvg9dp08s1Sc09PS0lBuGDMKPa8VG1e9pbWHph85ZiHdkGU6+qdFiMEWvooi3hYZQhgBslj2N1pj8DQ9AIlPANEhbeOBQLpXUdqF9WPBhY+rWMuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270140; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0LWRCn913M7vCoolX+xGuNwYWV09mC1JSnh5L3+sQaE=; b=DFHyVYzxc6G4sR4DyJVpEkcQl7LQHb2d3XuVwrepv85HHin+nS9oSrVzFMPOEBAW4KmfeUFscykpvEpvJkIP5QuwrGlbLjeXX55JfyBL2Q6L7/EUF6AC4367mO9aW14bXB1oPjZCFj4RQciP65D7qNV07ubk8mf4oKVxwGaVAYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100850+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167827014045213.379680091516775; Wed, 8 Mar 2023 02:09:00 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id eXbJYY1788612x5PEusah09K; Wed, 08 Mar 2023 02:09:00 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:08:59 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442648" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442648" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862628" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862628" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:56 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 03/14] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Wed, 8 Mar 2023 18:07:47 +0800 Message-Id: <20230308100758.669-4-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: SZxnmHZYQYBckHnvREFmtdOAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270140; bh=8gc36UbmNAzu+UWnr5aI10rFon6PYgCWF0nQFCTpoNY=; h=Cc:Date:From:Reply-To:Subject:To; b=Iu1lqvMJ9uPq3hdB3bENzZxgDGQeSzGUVLWdGOVhsgeQWJqRIlpwmmDZFMH+ewjtQgo fPndZLhAzINeM02YoP5ynnOIQwQuPEiBDqM46VZyN2N5UIbq4geib7szR/Bz3oS8iVUEd rV8Ws0IQyKbql734dXVY8yoqzyGSXNG5Fko= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270142426100004 Content-Type: text/plain; charset="utf-8" In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 27 ++++++++++++++++= +---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 4c9d70fa0a..ee27238edb 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,13 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). + // + BitStart =3D 12 + (Level - 1) * 9; + PagingEntryIndex =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitS= tart, BitStart + 9 - 1); + RegionLength =3D REGION_LENGTH (Level); + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. @@ -325,8 +333,11 @@ PageTableLibMapInLevel ( // the actual attributes of grand-parents when determing the memory ty= pe. // PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && + ( (Mask->Bits.PageTableBaseAddress =3D=3D 0) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) + =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) { // // This function is called when the memory length is less than the r= egion length of the parent level. @@ -353,8 +364,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); =20 - RegionLength =3D REGION_LENGTH (Level); - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; SubOffset +=3D RegionLength; @@ -425,14 +435,11 @@ PageTableLibMapInLevel ( } =20 // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLe= ngth and lower than (LinearAddress + Offset). // - BitStart =3D 12 + (Level - 1) * 9; - Index =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart= , BitStart + 9 - 1); - RegionLength =3D LShiftU64 (1, BitStart); - RegionMask =3D RegionLength - 1; - RegionStart =3D (LinearAddress + Offset) & ~RegionMask; + Index =3D PagingEntryIndex; + RegionMask =3D RegionLength - 1; + RegionStart =3D (LinearAddress + Offset) & ~RegionMask; =20 ParentAttribute->Uint64 =3D PageTableLibGetPnleMapAttribute (&ParentPagi= ngEntry->Pnle, ParentAttribute); =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100850): https://edk2.groups.io/g/devel/message/100850 Mute This Topic: https://groups.io/mt/97469471/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100851+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100851+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270141; cv=none; d=zohomail.com; s=zohoarc; b=LzOQ9vozjuAyMXxXZJT5581IeiD/Ex5h9XybauqAE1AZQyntNBXVeJGTD/ROSLXOXeHkn70G9Us+ReXly4THvgz1ue9rNhoqF1yibEb1/BCDS5R3tZi6RLB06RH03IsuwXFJfTqbEbKVCIzav6H04oCugzrxTCfEa2y7fGAsPEQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270141; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=n4RkrNgW/WUFBqNjGWwkPHhD+t/HXCxOiR0OvVUWVzw=; b=Fo9PF9wnS2SCGe35HyxP1Z+tGpgOkWicUxv9Khsk2CT3ewLLx/nBfhlEtZ1ZUNvb6Uuw6iZYN2HsuIqZWooS1gU/PQJ7jr3ffasWdYM+ZzsJ6h2+gq+d2d7MKEb9gGpEFbznxjjJIGiztDKOx9/zLNw4gyWEmiGZxIwp2rezu04= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100851+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270141881247.3010157460875; Wed, 8 Mar 2023 02:09:01 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id NZldYY1788612xkwc14QEkf2; Wed, 08 Mar 2023 02:09:01 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:09:01 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442656" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442656" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862642" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862642" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:59 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 04/14] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry Date: Wed, 8 Mar 2023 18:07:48 +0800 Message-Id: <20230308100758.669-5-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: viAkHWs2pO5ofBSKU7r8m7Cyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270141; bh=UZZ9/r9yMsMdI1ehSPZIIWYPB2lFBpZJ4Hc5fyXtORk=; h=Cc:Date:From:Reply-To:Subject:To; b=ZrECPrFUmltC4MwBSPEo2CMU/ViTDR7DkpkMg+Wp19l3Tq7c+JpfqW4fC6maqIV84uy 2sc2wWicIjy3eFFqPv3s2Vx0MiIPaPaaDYomE7+BhKVkuPG5ffpmgSMGZqfKmMjOIo7Il 88WSiKLx5IZVmhGV6t4iqaq8xykwHP8TPLQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270142397100002 Content-Type: text/plain; charset="utf-8" When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index ee27238edb..0f3d0d684e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -354,8 +354,15 @@ PageTableLibMapInLevel ( // // Create 512 child-level entries that map to 2M/4K. // - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); + ZeroMem (PagingEntry, SIZE_4KB); + + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; + SubOffset +=3D RegionLength; + } + + ParentPagingEntry->Uintn =3D (UINTN)(VOID *)PagingEntry; =20 // // Set NOP attributes @@ -363,12 +370,6 @@ PageTableLibMapInLevel ( // will make the entire region read-only even the child entrie= s set the RW bit. // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); - - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; - } } } else { // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100851): https://edk2.groups.io/g/devel/message/100851 Mute This Topic: https://groups.io/mt/97469475/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100852+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100852+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270144; cv=none; d=zohomail.com; s=zohoarc; b=GUNoe1JZvvbLzgx9HnOt2v8sbzfytxpgY36WEvg6d/QXqnOde+1B/SYalwAaaPgVGsRMgJr3oBgExDahhxHY75PL2lyYeYhKU9QRz6HBZqLe4myJyJC5cDg057+6oPF7OhZsPXlchriYGXF/KSBoyUqnLXSPV82RNtuohR/sSrs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270144; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=j7I0sH6B5fDZ3mRi0JuQ4X+b3j0vGWJhDxsWPif4dos=; b=PLdQJWQsU0TsxR/sIUUeGxwgEY+bg3a6ugoLkh9kThdG9Jv55L7xgZCAAPIq4xyCWRv+sBS4azeayrOgKFEmzyTfGoqCvHca75D1vUy67KowmPdmOiWdxOvTJZqq+LdSJ6UpWyctjWqJzqHrnVe38XLgnjTwp5oRI1U9B2NZ8uo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100852+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270144271478.93169262009326; Wed, 8 Mar 2023 02:09:04 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id diCLYY1788612xXxAJJiVHfg; Wed, 08 Mar 2023 02:09:03 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:09:03 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442687" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442687" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862650" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862650" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:01 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 05/14] UefiCpuPkg/CpuPageTebleLib: Check Mask and Attr in PageTableMap Date: Wed, 8 Mar 2023 18:07:49 +0800 Message-Id: <20230308100758.669-6-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: pUIk9S7ZBV5hFkQy9VkRrdhsx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270143; bh=aJqpTIUTbVuv6Et5OeowdRsTrhhjE/RlmTnvZiAT+iY=; h=Cc:Date:From:Reply-To:Subject:To; b=CqF/hdlU0Mo6X/laSUGUQ1jnBCBa34c2W6hpRJzl8h54EDzY/8hkNbON6IzEs5rGceB zl7bBlLEePU59IqvYVy97r2JdBWbpveceC++b/cWd7kaksu4Faqgn/bIoNU69sxLXwgqQ lexXqWFW82DpJSJ8hHvZJo2q1XZMAdvoAZ8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270146398100002 Content-Type: text/plain; charset="utf-8" When creating new page table or mapping not-present range in existing page table, we need to make sure all the non-reserved fields of input Mask are not 0 and Present field of input Attribute is 1. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 54 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 0f3d0d684e..56f762a15e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -214,6 +214,33 @@ PageTableLibSetPnle ( Pnle->Bits.CacheDisabled =3D 0; } =20 +/** + Check if any Non-Reserved field of Mask is 0 or Attribute->Bits.Present = is 0 + when creating new page table or mapping not-present range. + + @param[in] Attribute The attribute of the linear address range. + @param[in] Mask The mask used for attribute to check. + + @retval RETURN_INVALID_PARAMETER There is 0-value field in Non-Reserv= ed fields of Mask or Attribute->Bits.Present is 0. + @retval RETURN_SUCCESS All Non-Reserved fields of Mask are = not 0 and Attribute->Bits.Present is 1. +**/ +RETURN_STATUS +CheckMaskAndAttrForNotPresentEntry ( + IN IA32_MAP_ATTRIBUTE *Attribute, + IN IA32_MAP_ATTRIBUTE *Mask + ) +{ + if ((Attribute->Bits.Present =3D=3D 0) || (Mask->Bits.Present =3D=3D 0) = || (Mask->Bits.ReadWrite =3D=3D 0) || + (Mask->Bits.UserSupervisor =3D=3D 0) || (Mask->Bits.WriteThrough =3D= =3D 0) || (Mask->Bits.CacheDisabled =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (Ma= sk->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protection= Key =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + return RETURN_INVALID_PARAMETER; + } + + return RETURN_SUCCESS; +} + /** Update page table to map [LinearAddress, LinearAddress + Length) with sp= ecified attribute in the specified level. =20 @@ -259,6 +286,7 @@ PageTableLibMapInLevel ( UINTN Index; IA32_PAGING_ENTRY *PagingEntry; UINTN PagingEntryIndex; + UINTN PagingEntryIndexLimit; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -302,6 +330,14 @@ PageTableLibMapInLevel ( // =20 if (ParentPagingEntry->Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains not-present range. + // + Status =3D CheckMaskAndAttrForNotPresentEntry (Attribute, Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. @@ -372,6 +408,23 @@ PageTableLibMapInLevel ( PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); } } else { + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_T= ABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntryIndexLimit =3D (BitFieldRead64 (LinearAddress + Length - 1,= BitStart + 9, 63) > BitFieldRead64 (LinearAddress + Offset, BitStart + 9, = 63)) ? 511 : + (UINTN)BitFieldRead64 (LinearAddress + Length = - 1, BitStart, BitStart + 9 - 1); + for (Index =3D PagingEntryIndex; Index <=3D PagingEntryIndexLimit; Ind= ex++) { + if (PagingEntry[Index].Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains not-present ra= nge. + // + Status =3D CheckMaskAndAttrForNotPresentEntry (Attribute, Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + + break; + } + } + // // It's a non-leaf entry // @@ -419,7 +472,6 @@ PageTableLibMapInLevel ( // Update child entries to use restrictive attribute inherited fro= m parent. // e.g.: Set PDE[0-255].ReadWrite =3D 0 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_B= ASE_ADDRESS (&ParentPagingEntry->Pnle); for (Index =3D 0; Index < 512; Index++) { if (PagingEntry[Index].Pce.Present =3D=3D 0) { continue; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100852): https://edk2.groups.io/g/devel/message/100852 Mute This Topic: https://groups.io/mt/97469476/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100853+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100853+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270146; cv=none; d=zohomail.com; s=zohoarc; b=PMaQoBWtbDdsd8LjDLcR4QQQh8QO6i0nNzG2+GM9pXYJ49LFfOmFWKcEv2Pd8n02/pOojMb+K28ODjCCAEVJRMT3FuU2vSInmy/9/T3KDHMD1HXDunrRLRTiugDhf43gJq+gxKZcfPp3AxErE8kgEu+bTFSubjC6YxlJLZxCf5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270146; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qqBbrXzfBFoL5/GfCLOOykuI37hM6DExw/ayR/0blSs=; b=lJ5ZO0J9vLSvjG4uT25rI9v2KnvkDyV5NTuNg2GNZYeF86puFeMnUvkghoYhiXncFNvONSWDWCkKGuw1GKTvh5bTabAqJO6t08KyzJTPIZWEXhCmMWwx1kpGS+0lyBVpicx11ghb29Z6RNlhStP0H/jJjrhHOrkFn3zuFVlH9Vg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100853+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270146369600.8303439066859; Wed, 8 Mar 2023 02:09:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aDy5YY1788612xu5wufMzTEF; Wed, 08 Mar 2023 02:09:06 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:09:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442700" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442700" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862664" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862664" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:03 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 06/14] UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr Date: Wed, 8 Mar 2023 18:07:50 +0800 Message-Id: <20230308100758.669-7-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: lQrhRj3aObgKkMI0hAYgB8cDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270146; bh=up2/FVJ7HR8R7ELKNPUxBqWWe5Mlnp9PQD71o+lwYzY=; h=Cc:Date:From:Reply-To:Subject:To; b=unev/vjia/mXHAnF1RISn1vcRZCPvjkXbbjewKTlOSNwqu30DuRleNLnPdlkiwwmt8u rLDchi/1PMbDk7Gj4B/NBrdwYqDNcWP5HwAF3ehZqXfRu/vi3ktjt67oRsc3crQYoi+Ir 0PS+xnWhbC8nC9HuTlc4DWqv0AY2My2XsqU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270148381100005 Content-Type: text/plain; charset="utf-8" Add manual test case to check input Mask and Attribute. When creating new page table or mapping not-present range in existing page table, all the non-reserved fields of Mask and Present bit of Attribute should not be 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 109 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3014a03243..fe00a7f632 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -697,6 +697,114 @@ TestCaseManualChangeNx ( return UNIT_TEST_PASSED; } =20 +/** + Check if the input Mask and Attribute is expected when creating new page= table or + map not-present range in existing page table. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +TestCaseToCheckMapMaskAndAttr ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINTN PageTable; + PAGING_MODE PagingMode; + VOID *Buffer; + UINTN PageTableBufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + // + // Create Page table to cover [0, 1G]. All fields of MapMask should be s= et. + // + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_1GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_1GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_1GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Update Page table to cover [1G, 2G - 8K]. All fields of MapMask shoul= d be set and Present bit of MapAttribute should be 1. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_1GB; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &Ma= pMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Update Page table to cover [2G - 8K, 2G] and set [2G - 8K, 2G] as RW.= All fields of MapMask should be set and Present bit of MapAttribute should= be 1. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Bits.ReadWrite =3D 1; + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapAttribute.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &Ma= pMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + MapCount =3D 0; + Status =3D PageTableParse (PageTable, PagingMode, NULL, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof (IA32_MAP_= ENTRY))); + Status =3D PageTableParse (PageTable, PagingMode, Map, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // There should be two ranges [0, 2G-8k] with RW =3D 0 and [2G-8k, 2G] w= ith RW =3D 1 + // + UT_ASSERT_EQUAL (MapCount, 2); + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB - SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D 0; + ExpectedMapAttribute.Bits.Present =3D 1; + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, ExpectedMapAttribute.Uint64); + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2GB - SIZE_8KB); + UT_ASSERT_EQUAL (Map[1].Length, SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + ExpectedMapAttribute.Bits.Present =3D 1; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); + return UNIT_TEST_PASSED; +} + /** Initialize the unit test framework, suite, and unit tests for the sample unit tests and run the unit tests. @@ -746,7 +854,7 @@ UefiTestMain ( AddTestCase (ManualTestCase, "Check if the parent entry has different Re= adWrite attribute", "Manual Test Case5", TestCaseManualChangeReadWrite, NUL= L, NULL, NULL); AddTestCase (ManualTestCase, "Check if the parent entry has different Nx= attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, NULL); AddTestCase (ManualTestCase, "Check if the needed size is expected", "Ma= nual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); - + AddTestCase (ManualTestCase, "Check MapMask when creating new page table= or mapping not-present range", "Manual Test Case8", TestCaseToCheckMapMask= AndAttr, NULL, NULL, NULL); // // Populate the Random Test Cases. // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100853): https://edk2.groups.io/g/devel/message/100853 Mute This Topic: https://groups.io/mt/97469478/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100854+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100854+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270148; cv=none; d=zohomail.com; s=zohoarc; b=AlQJiNeeW3JE8ACx73C4FDoZ3Fi5jXnoYOPyozjcRtGmKwMxC+kiFbp8iYnD1cGU0oPIUCk4zbdCIIf+rqv3z7z9oCexXConJ63ggoX898B5CbXkzjXY06FZK4k2kp+WC/V+u2l1ctiDpmPVB+hn23nKd6U1Tc7QxyXdBsflzNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270148; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AXxIu9J3Znf3ID1BNZz7msn4Hesa9u33CxKD0zN6Yz4=; b=WAsFKG/dA1D+Xq6bXyGbZYMggvAnMLCmMKf2jSwKEMh7G+eP7ffKp65FwBBIkHsf8tm4YMoQNLuqc7LsXwdV6v9d8xxs7VwPxUu6Q8R9uejFEMx5AMTPl6F7IP7DlcbTxP3uelgewqCnNSnef2TBGWx21L6hW4juc20zHy809qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100854+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16782701485551000.9842121052395; Wed, 8 Mar 2023 02:09:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Wu67YY1788612xgVeIBp1IuR; Wed, 08 Mar 2023 02:09:08 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:09:07 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442718" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442718" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862707" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862707" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:05 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V2 07/14] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr Date: Wed, 8 Mar 2023 18:07:51 +0800 Message-Id: <20230308100758.669-8-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: jUjA6LmazUOQCZ1ky9ZC7pxVx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270148; bh=LdbQAL0etYIcbHqKlRRPl2MFpYqZosvL4yCNSBhEugo=; h=Cc:Date:From:Reply-To:Subject:To; b=SKmZLKKa1dccAyMKoNDNyE1+GBiXhOGkvra9HON5PyoufeyYaMSinoFv/sd/Cjt6s5H bn5p2I1ALfKPAdS0ZQvh+omsykKr06OpnyQMVm3ZsEHDDVq5HxYiBzUqjV5BiKsA/h9xC EYbw8aBtMVOhBIrHxOS23RGIAbU2VqCF1ek= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270150433100010 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check invalid input. When creating new page table or mapping not-present range in existing page table, if any non-reserved field of Mask or Present bit of Attribute in generated random MapEntry are 0, the return status of PageTableMap () should be RETURN_INVALID_PARAMETER. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 169 +++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++------------------------------------= -------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c | 4 ++++ 2 files changed, 129 insertions(+), 44 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 97a388ca1c..8293e3d8eb 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -81,22 +81,6 @@ LocalRandomBytes ( } } =20 -/** - Return a random boolean. - - @return boolean -**/ -BOOLEAN -RandomBoolean ( - VOID - ) -{ - BOOLEAN Value; - - LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); - return Value%2; -} - /** Return a 32bit random number. =20 @@ -139,6 +123,21 @@ Random64 ( return (UINT64)(Value % (Limit - Start + 1)) + Start; } =20 +/** + Returns true with the percentage of input Probability. + + @param[in] Probability The percentage to return true. + + @return boolean +**/ +BOOLEAN +RandomBoolean ( + UINT8 Probability + ) +{ + return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE); +} + /** Check if the Page table entry is valid =20 @@ -178,7 +177,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; @@ -211,7 +210,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; =20 @@ -274,6 +273,27 @@ ValidateAndRandomeModifyPageTable ( return Status; } =20 +/** + Remove the last MAP_ENTRY in MapEntrys. + + @param MapEntrys Pointer to MapEntrys buffer +**/ +VOID +RemoveLastMapEntry ( + IN OUT MAP_ENTRYS *MapEntrys + ) +{ + UINTN MapsIndex; + + if (MapEntrys->Count =3D=3D 0) { + return; + } + + MapsIndex =3D MapEntrys->Count - 1; + ZeroMem (&(MapEntrys->Maps[MapsIndex]), sizeof (MAP_ENTRY)); + MapEntrys->Count =3D MapsIndex; +} + /** Generate single random map entry. The map entry can be the input of function PageTableMap @@ -299,7 +319,7 @@ GenerateSingleRandomMapEntry ( // // use AlignedTable to avoid that a random number can be very hard to be= 1G or 2M aligned // - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { FormerLinearAddress =3D MapEntrys->Maps[Random32 (0, (UINT32)MapsIndex= -1)].LinearAddress; if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { FormerLinearAddressBottom =3D 0; @@ -323,12 +343,21 @@ GenerateSingleRandomMapEntry ( // MapEntrys->Maps[MapsIndex].Length =3D Random64 (0, MIN (MaxAddress - Map= Entrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & AlignedTab= le[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; =20 - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; - MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; + if (RandomBoolean (5)) { + // + // The probability to get random Mask should be small since all bits= of a random number + // have a high probability of containing 0, which may be a invalid i= nput. + // + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT64) = & mSupportedBit.Uint64; + } else { + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MAX_UINT64; + } + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey !=3D 0) { MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey =3D 0xF; } @@ -338,15 +367,7 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; } else { - // - // Todo: If the mask bit for base address is zero, when dump the paget= able, every entry mapping to physical address zeor. - // This means the map count will be a large number, and impossib= le to finish in proper time. - // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING - // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean ()) { - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; - } } =20 MapEntrys->Count +=3D 1; @@ -609,23 +630,64 @@ SingleMapEntryTest ( IN UINTN InitMapCount ) { - UINTN MapsIndex; - RETURN_STATUS Status; - UINTN PageTableBufferSize; - VOID *Buffer; - IA32_MAP_ENTRY *Map; - UINTN MapCount; - UINTN Index; - UINTN KeyPointCount; - UINTN NewKeyPointCount; - UINT64 *KeyPointBuffer; - UINTN Level; - UINT64 Value; - UNIT_TEST_STATUS TestStatus; - - MapsIndex =3D MapEntrys->Count; + UINTN MapsIndex; + RETURN_STATUS Status; + UINTN PageTableBufferSize; + VOID *Buffer; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + UINTN Index; + UINTN KeyPointCount; + UINTN NewKeyPointCount; + UINT64 *KeyPointBuffer; + UINTN Level; + UINT64 Value; + UNIT_TEST_STATUS TestStatus; + IA32_MAP_ATTRIBUTE *Mask; + IA32_MAP_ATTRIBUTE *Attribute; + UINT64 PreviousAddress; + BOOLEAN IsNotPresent; + + MapsIndex =3D MapEntrys->Count; + MapCount =3D 0; + PreviousAddress =3D 0; + IsNotPresent =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); + + // + // Check if the generated MapEntrys->Maps[MapsIndex] contains not-presen= t range. + // + if (MapEntrys->Maps[MapsIndex].Length > 0) { + if (MapCount !=3D 0) { + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MA= P_ENTRY))); + ASSERT (Map !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + + if (Map[MapCount - 1].LinearAddress + Map[MapCount - 1].Length < Map= Entrys->Maps[MapsIndex].LinearAddress + MapEntrys->Maps[MapsIndex].Length) { + IsNotPresent =3D TRUE; + } else { + for (Index =3D 0; Index < MapCount; Index++) { + if ((PreviousAddress < Map[Index].LinearAddress) && + (MapEntrys->Maps[MapsIndex].LinearAddress < Map[Index].Linea= rAddress) && + ((MapEntrys->Maps[MapsIndex].LinearAddress + MapEntrys->Maps= [MapsIndex].Length) > PreviousAddress)) + { + // + // MapEntrys->Maps[MapsIndex] contains not-present range in ex= siting page table. + // + IsNotPresent =3D TRUE; + break; + } + + PreviousAddress =3D Map[Index].LinearAddress + Map[Index].Length; + } + } + } else { + IsNotPresent =3D TRUE; + } + } =20 PageTableBufferSize =3D 0; Status =3D PageTableMap ( @@ -638,6 +700,25 @@ SingleMapEntryTest ( &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask ); + + // + // Return Status should be InvalidParameter when: + // 1. MapEntrys->Maps[MapsIndex] contains not-present range. + // 2. MapEntrys->Maps[MapsIndex].Mask contains zero value field or Attri= bute->Bits.Present is 0. + // + Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; + Mask =3D &MapEntrys->Maps[MapsIndex].Mask; + if (((Attribute->Bits.Present =3D=3D 0) || (Mask->Bits.Present =3D=3D 0)= || (Mask->Bits.ReadWrite =3D=3D 0) || + (Mask->Bits.UserSupervisor =3D=3D 0) || (Mask->Bits.WriteThrough = =3D=3D 0) || (Mask->Bits.CacheDisabled =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (M= ask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protectio= nKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) && + IsNotPresent) + { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + if (PageTableBufferSize !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 5bd70c0f65..11f7e607ca 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -171,6 +171,10 @@ IsPageTableValid ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 + if (PageTable =3D=3D 0) { + return UNIT_TEST_PASSED; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100854): https://edk2.groups.io/g/devel/message/100854 Mute This Topic: https://groups.io/mt/97469479/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100855+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100855+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270158; cv=none; d=zohomail.com; s=zohoarc; b=dlYripQNxJEemK3kll8n7W3KVTG9CLDh7HJ/dfGLZCzp2JAGPdf+dF68UZmvtd46HPUAH9AOexEZUmIEMurAa048u/o6ujkSZSWKZ47kpcRdouhZEcKO6wehjQTGZobUsuRfh60ACRTqLiXyWcJ4jYubB1uTdiWPB15P0zY3js8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270158; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kr8J/w3gFXIw0rP5Lz3bivCIfWDyHbe/lVvDIeSiW2g=; b=ih/fAbV5rHMlZGRXomZWWGbSn0mRRAtK4nH/FlGqyuWibj38+6qJTGykIs9dxhrfeX2TerXt1XrU3Q4YMpwfIA3yJSpfEjlWioRHt6RKmKZKT+XMJdfCZa60eZ8JyZbSHHbYwWABig7doFniJlaKQhgRTNmt5uV5o1q7dMSTm14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100855+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270158207263.16038506556094; Wed, 8 Mar 2023 02:09:18 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id P2pwYY1788612xT0S6irKp0b; Wed, 08 Mar 2023 02:09:10 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:09:09 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442731" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442731" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862723" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862723" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:08 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 08/14] UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test Date: Wed, 8 Mar 2023 18:07:52 +0800 Message-Id: <20230308100758.669-9-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Nvmj0mZFdrJoDCWSCq0NnF9sx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270150; bh=UTrVe8aANXGhE0kS9Tl45LSJRl07SHNG4fPBd07UyqI=; h=Cc:Date:From:Reply-To:Subject:To; b=n/PVvxS1NKpuELBPX1oX4iw0UYFc0iY/EoDIBByzqUqCDvqsndRSGXrx236gADhSxmL dfXVHoFlR5wDhwxGrRUCbCb3nsMxxHc20c672oqHv0e8HGdh9ay5L+SUwN/lO433zViYt /2Ckawgi+ONklz3YOuYBo8CZokEHAcm8tAI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270158432100001 Content-Type: text/plain; charset="utf-8" Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index fe00a7f632..6f27411d4b 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,10 +9,10 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY }; =20 /** Check if the input parameters are not supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100855): https://edk2.groups.io/g/devel/message/100855 Mute This Topic: https://groups.io/mt/97469483/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100856+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100856+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270153; cv=none; d=zohomail.com; s=zohoarc; b=K94kTFoRqxSwENYs+mkKr/bWOlBft+0pffDjrA+rcGFQo6NpeGNoBYZvwVc44vi4pNBM+flFx+WecktHM3dsql6Xzdby10ty8Mlg6KtlnTUbWXLfgvlOIUmUA0GojrFYW2DqFeKSHiimDjxlH7qRKEJ1h/QLTI5HjsfiCXINwEE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270153; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kcnGxgk8dNv4eZPEW5cTpAEOReSeOEYhZ9Opk8Tig9U=; b=g7fwciAdrVJ0YAmkue1MQXVFT8Ur6DYRokOZdsV78RtVU83h6F/mhy6QrxkztjkaIvS2rysr2bxIIf6zDleCBylzKE+3LyA53+VU7rqiJr/Fh6pAeu54H9A+5ObQIClMt6cOuDXAvfKm7ds0uqSreYsy5dQ90jF0QEys9ao+R2s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100856+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270153144509.6937910668887; Wed, 8 Mar 2023 02:09:13 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9aZoYY1788612xjjZb3y63lB; Wed, 08 Mar 2023 02:09:12 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:09:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442747" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442747" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862729" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862729" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:10 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 09/14] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Date: Wed, 8 Mar 2023 18:07:53 +0800 Message-Id: <20230308100758.669-10-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: CYV4pEjoNoI4VxMnoWOWdhmNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270152; bh=CR4wT/CRiVbwC+yYPB2/uY4TRoSIpf2VumoRiH3X6Ek=; h=Cc:Date:From:Reply-To:Subject:To; b=wqirxHQhRXGUm8S2K9kehW7QQkOVdpmEQrUb1/WGusIXXNKDZMWjocl5OEi89eb3gR9 vKglTNZ/Z0KWP15uVe6XERhXGp3tlxIFXkiR6fIE98W/8wJjWtRERUFM3rB97u6ujyvh8 Y5A4oV/xxSinWlreMJr1dIilW8kzGDdLIUI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270154569100001 Content-Type: text/plain; charset="utf-8" Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h = | 4 +++- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c = | 47 ++++++++++++++++++++++++++++++++++++++++------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 66 +++++++++++++++++++++++++++++++++--------------------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 6 ++++-- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c = | 6 ++++-- 5 files changed, 84 insertions(+), 45 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 2dc9b7d18e..118dff20f4 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -74,6 +74,7 @@ typedef enum { Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. @@ -93,7 +94,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ); =20 typedef struct { diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 56f762a15e..4e8ac9b981 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -262,6 +262,7 @@ CheckMaskAndAttrForNotPresentEntry ( Page table entries that map the linear= address range are reset to 0 before set to the new attribute when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FAL= SE means page table is not modified. =20 @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. **/ @@ -278,7 +279,8 @@ PageTableLibMapInLevel ( IN UINT64 Length, IN UINT64 Offset, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ) { RETURN_STATUS Status; @@ -302,6 +304,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildMask; IA32_MAP_ATTRIBUTE CurrentMask; IA32_MAP_ATTRIBUTE LocalParentAttribute; + IA32_PAGING_ENTRY ParentPagingEntryContent; + IA32_PAGING_ENTRY PrevLeafPagingEntryContent; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -314,8 +318,9 @@ PageTableLibMapInLevel ( NopAttribute.Bits.ReadWrite =3D 1; NopAttribute.Bits.UserSupervisor =3D 1; =20 - LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; - ParentAttribute =3D &LocalParentAttribute; + LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; + ParentAttribute =3D &LocalParentAttribute; + ParentPagingEntryContent.Uint64 =3D ParentPagingEntry->Uint64; =20 // // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). @@ -542,7 +547,17 @@ PageTableLibMapInLevel ( ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->Bit= s.Nx =3D=3D 1)); } =20 + // + // Check if any leaf PagingEntry is modified. + // + PrevLeafPagingEntryContent.Uint64 =3D CurrentPagingEntry->Uint64; PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = &CurrentMask); + + if (PrevLeafPagingEntryContent.Uint64 !=3D CurrentPagingEntry->Uin= t64) { + if (IsModified !=3D NULL) { + *IsModified =3D TRUE; + } + } } } else { // @@ -565,7 +580,8 @@ PageTableLibMapInLevel ( Length, Offset, Attribute, - Mask + Mask, + IsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -577,6 +593,15 @@ PageTableLibMapInLevel ( Index++; } =20 + // + // Check if ParentPagingEntry entry is modified. + // + if (ParentPagingEntryContent.Uint64 !=3D ParentPagingEntry->Uint64) { + if (IsModified !=3D NULL) { + *IsModified =3D TRUE; + } + } + return RETURN_SUCCESS; } =20 @@ -597,6 +622,7 @@ PageTableLibMapInLevel ( Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. @@ -616,7 +642,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ) { RETURN_STATUS Status; @@ -661,6 +688,10 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 + if (IsModified !=3D NULL) { + *IsModified =3D FALSE; + } + MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); @@ -703,7 +734,8 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + NULL ); if (RETURN_ERROR (Status)) { return Status; @@ -735,7 +767,8 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + IsModified ); if (!RETURN_ERROR (Status)) { *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 6f27411d4b..3df6436af3 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -51,26 +51,26 @@ TestCaseForParameter ( // // If the input linear address is not 4K align, it should return invalid= parameter // - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PageTableBufferSize is not 4K align, it should return in= valid parameter // PageTableBufferSize =3D 10; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PagingMode is Paging32bit, it should return invalid para= meter // PageTableBufferSize =3D 0; PagingMode =3D Paging32bit; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_UNSUPPORTED); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_UNSUPPORT= ED); =20 // // If the input MapMask is NULL, it should return invalid parameter // PagingMode =3D Paging5Level1GB; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), RETURN_INVALID_PARAMETER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL, NULL), RETURN_INVALID_PARAM= ETER); =20 return UNIT_TEST_PASSED; } @@ -119,10 +119,10 @@ TestCaseWhichNoNeedExtraSize ( // // Create page table to cover [0, 10M], it should have 5 PTE // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -134,7 +134,7 @@ TestCaseWhichNoNeedExtraSize ( // We assume the fucntion doesn't need to change page table, return succ= ess and output BufferSize is 0 // Buffer =3D NULL; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (PageTableBufferSize, 0); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -148,7 +148,7 @@ TestCaseWhichNoNeedExtraSize ( // MapMask.Bits.Nx =3D 0; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -164,7 +164,7 @@ TestCaseWhichNoNeedExtraSize ( MapAttribute.Bits.Accessed =3D 1; MapMask.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -217,10 +217,10 @@ TestCase1Gmapto4K ( MapAttribute.Bits.Present =3D 1; MapMask.Bits.Present =3D 1; MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -281,11 +281,11 @@ TestCaseManualChangeReadWrite ( // // Create Page table to cover [0,2G], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); BackupPageTableBufferSize =3D PageTableBufferSize; Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -331,7 +331,7 @@ TestCaseManualChangeReadWrite ( // Call library to change ReadWrite to 0 for [0,2M] // MapAttribute.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -360,7 +360,7 @@ TestCaseManualChangeReadWrite ( // MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -434,10 +434,10 @@ TestCaseManualSizeNotMatch ( // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -493,7 +493,7 @@ TestCaseManualSizeNotMatch ( MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } @@ -540,10 +540,10 @@ TestCaseManualNotMergeEntry ( // // Create Page table to cover [0,4M], and [4M, 1G] is not present // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -555,7 +555,7 @@ TestCaseManualNotMergeEntry ( // It looks like the chioce is not bad, but sometime, we need to keep so= me small entry // PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NUL= L); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -564,7 +564,7 @@ TestCaseManualNotMergeEntry ( =20 MapAttribute.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk, NULL); // // If it didn't use a big 1G entry to cover whole range, only change [0,= 2M] for some attribute won't need extra memory // @@ -619,10 +619,10 @@ TestCaseManualChangeNx ( // // Create Page table to cover [0,2G], with Nx =3D 0 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -666,7 +666,7 @@ TestCaseManualChangeNx ( // // Call library to change Nx to 0 for [0,1G] // - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -741,13 +741,13 @@ TestCaseToCheckMapMaskAndAttr ( // // Create Page table to cover [0, 1G]. All fields of MapMask should be s= et. // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -758,13 +758,13 @@ TestCaseToCheckMapMaskAndAttr ( MapAttribute.Bits.Present =3D 1; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &Ma= pMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &Ma= pMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &MapMask, NULL= ); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_1GB, SIZE_1GB - SIZE_8KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -774,10 +774,10 @@ TestCaseToCheckMapMaskAndAttr ( MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; MapAttribute.Bits.ReadWrite =3D 1; MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapAttribute.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &Ma= pMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &Ma= pMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 MapCount =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 8293e3d8eb..b2965d61fb 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -698,7 +698,8 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].LinearAddress, MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + &MapEntrys->Maps[MapsIndex].Mask, + NULL ); =20 // @@ -736,7 +737,8 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].LinearAddress, MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + &MapEntrys->Maps[MapsIndex].Mask, + NULL ); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index 7cf91ed9c4..c10121ede5 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -60,7 +60,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); @@ -75,7 +76,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT_EFI_ERROR (Status); return PageTable; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100856): https://edk2.groups.io/g/devel/message/100856 Mute This Topic: https://groups.io/mt/97469484/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100857+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100857+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270164; cv=none; d=zohomail.com; s=zohoarc; b=V+mhg4/NQTLa+rpiyBb96rjSkl01iWcDFrxPIOR9hkc7929muRJk7smv9YO4UUr8s64kuMd0GML4vTD4YL6M6LKFOLredki42UTcAQfHjnuC3M6aUvRfnfgQHgdwupcWx+zWbSrmPCtIpX6kT8JONaEZOA77PfBMdrvNlfVF7kg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270164; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cNSOU2LsEkZJ15KBDwxiJOd9ZRu8fZTNK5r2nH5L9IE=; b=cfPuxO8V8g8Jk1JpOE3pQ98UfA6rHNk7KAh63Ykk99eeY1rHENOy77ShLOatx8mu1tf1FTeZjO41f24Aw7wqIffx2FKn/lsdFW4lCBR6TjLDP8xWFRjQmI3PMou0bx+hz4dvT+fguAPhFp4fVBi9UdL2DvpWisGt+UZ3WKUyMnA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100857+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270164289669.0411384148393; Wed, 8 Mar 2023 02:09:24 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id vAs3YY1788612xPyQW0assiX; Wed, 08 Mar 2023 02:09:24 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3482.1678270163429735420 for ; Wed, 08 Mar 2023 02:09:23 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442823" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442823" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862765" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862765" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:12 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V2 10/14] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified Date: Wed, 8 Mar 2023 18:07:54 +0800 Message-Id: <20230308100758.669-11-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: xjQawVkkojcFCpZuayfq4tBsx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270164; bh=rTacFe5cfOm/QLR6dygwRTanJmTscYK1lWA7YkH+eZY=; h=Cc:Date:From:Reply-To:Subject:To; b=txqJ36WKdDyq77ZsH9zAIMFnP/oa1PXwCRpdfXARndkTP6s4KK6yqxRiaiq/nrrJK6H A0PRFj3Omm9qQs6Hccmo0a/cizGYshK01gEVAabYzFatT1T023K0d8bQc8DB1/TOzkLMg SB4dotmxCKG4RFuOvAuh/+NWFQTd7KQA4K8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270166460100001 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 63 ++++++++++++= ++++++++++++++++++++++++++++++++++----------------- 1 file changed, 46 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index b2965d61fb..8f8f0a5a9f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -636,6 +636,8 @@ SingleMapEntryTest ( VOID *Buffer; IA32_MAP_ENTRY *Map; UINTN MapCount; + IA32_MAP_ENTRY *Map2; + UINTN MapCount2; UINTN Index; UINTN KeyPointCount; UINTN NewKeyPointCount; @@ -647,25 +649,33 @@ SingleMapEntryTest ( IA32_MAP_ATTRIBUTE *Attribute; UINT64 PreviousAddress; BOOLEAN IsNotPresent; + BOOLEAN IsModified; =20 MapsIndex =3D MapEntrys->Count; MapCount =3D 0; PreviousAddress =3D 0; IsNotPresent =3D FALSE; + IsModified =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); =20 + if (MapCount !=3D 0) { + // + // Allocate memory for Map + // Note the memory is only used in this one Single MapEntry Test + // + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); + ASSERT (Map !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + } + // // Check if the generated MapEntrys->Maps[MapsIndex] contains not-presen= t range. // if (MapEntrys->Maps[MapsIndex].Length > 0) { if (MapCount !=3D 0) { - UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); - Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MA= P_ENTRY))); - ASSERT (Map !=3D NULL); - Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); - if (Map[MapCount - 1].LinearAddress + Map[MapCount - 1].Length < Map= Entrys->Maps[MapsIndex].LinearAddress + MapEntrys->Maps[MapsIndex].Length) { IsNotPresent =3D TRUE; } else { @@ -699,7 +709,7 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask, - NULL + &IsModified ); =20 // @@ -738,7 +748,7 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask, - NULL + &IsModified ); } =20 @@ -752,18 +762,33 @@ SingleMapEntryTest ( return TestStatus; } =20 - MapCount =3D 0; - Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); - if (MapCount !=3D 0) { + MapCount2 =3D 0; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount2); + if (MapCount2 !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 // - // Allocate memory for Maps + // Allocate memory for Map2 // Note the memory is only used in this one Single MapEntry Test // - Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); - ASSERT (Map !=3D NULL); - Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + Map2 =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MA= P_ENTRY))); + ASSERT (Map2 !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map2, &MapCount2); + } + + // + // Check if PageTable has been modified. + // + if (MapCount2 !=3D MapCount) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + if (MapCount2 =3D=3D 0) { + UT_ASSERT_EQUAL (IsModified, FALSE); + } else if (CompareMem (Map, Map2, MapCount2 * sizeof (IA32_MAP_ENTRY))= !=3D 0) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + UT_ASSERT_EQUAL (IsModified, FALSE); + } } =20 UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); @@ -773,17 +798,17 @@ SingleMapEntryTest ( // Note the memory is only used in this one Single MapEntry Test // KeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); + GetKeyPointList (MapEntrys, Map2, MapCount2, NULL, &KeyPointCount); KeyPointBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * siz= eof (UINT64))); ASSERT (KeyPointBuffer !=3D NULL); NewKeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, &NewKeyPointC= ount); + GetKeyPointList (MapEntrys, Map2, MapCount2, KeyPointBuffer, &NewKeyPoin= tCount); =20 // // Compare all key point's attribute // for (Index =3D 0; Index < NewKeyPointCount; Index++) { - if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, = MapCount, InitMap, InitMapCount)) { + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map2,= MapCount2, InitMap, InitMapCount)) { DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); DEBUG ((DEBUG_INFO, "Index =3D %d KeyPointBuffer[Index] =3D 0x%lx\n"= , Index, KeyPointBuffer[Index])); Value =3D GetEntryFromPageTable (*PageTable, PagingMode, KeyPointBuf= fer[Index], &Level); @@ -797,6 +822,10 @@ SingleMapEntryTest ( FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_ENTRY))= ); } =20 + if (MapCount2 !=3D 0) { + FreePages (Map2, EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MAP_ENTRY= ))); + } + return UNIT_TEST_PASSED; } =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100857): https://edk2.groups.io/g/devel/message/100857 Mute This Topic: https://groups.io/mt/97469486/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100858+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100858+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270167; cv=none; d=zohomail.com; s=zohoarc; b=aFkO/am7+tpe9fHgo9FxTkOzdGuWS22EobfNOGfvhL9z+mnY0/lFSDG3VNiVjGsdMqrh+I+Mdas3uRWFYgTAPMOH5ibhHjWQZrgzzdnhzsRW2cgDe4zi+J5LNdIRS9jO2FMa4+CWwmlidhpXwroBjodffNwrkCwsIRfJMYSK7OE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270167; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qFoR4Jh4TMAalKi8GD13zJeaaZ2DXvmhIS2/8I1/9Yg=; b=C/j9/6sYBHA0pwSnVQw6eOvy74xJZ7mLeNZYHxmJf/bjyoTtAJw02aI1lFA5amS+cNICsdJLVLim4V8gYf9xUNcPFfAoD2fB4wV8PQ0z1MiWTcQSzzYaQfcI6ngCuuSV3mSetvy8jb/cTKmumsa3pncfvtn4GMQ71+WMGbWFJ3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100858+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270167554232.70874184501304; Wed, 8 Mar 2023 02:09:27 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Ue5WYY1788612xbly6IGX2Xf; Wed, 08 Mar 2023 02:09:26 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3482.1678270163429735420 for ; Wed, 08 Mar 2023 02:09:25 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442846" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442846" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862858" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862858" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:20 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 11/14] UefiCpuPkg/CpuPageTableLib: Enable PAE paging Date: Wed, 8 Mar 2023 18:07:55 +0800 Message-Id: <20230308100758.669-12-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: iig0srHb3zRJC0INNtvciok3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270166; bh=NQPjHo5b0xX952wQU8Dz+YkUZ0voBwA3UWkkAVtYb68=; h=Cc:Date:From:Reply-To:Subject:To; b=e15ilIFLjdmfT9yM5IgBilCRAGAGu6krp82qACoJ1jW1uc9GVLsaZuImFvHi6sybxmx UB7HmeCnwrGgFur2jZ7eMHYaU83UGIDFZ5ZKjyW7lBr7Wm7S6yvrMpSZvBbZYJTutv+mL tf469c0wZcgz5UvcwHyS7eS3hBT3W0k9BrE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270168466100007 Content-Type: text/plain; charset="utf-8" Remove the limitation check for PagingPae to enable creating or updating PAE page table in CpuPageTableLib. The origin code is naturally adapted for PAE paging. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 4e8ac9b981..d99a21a0fc 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -658,10 +658,9 @@ PageTableMap ( return RETURN_SUCCESS; } =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return RETURN_UNSUPPORTED; } @@ -694,11 +693,11 @@ PageTableMap ( =20 MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); - MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); + MaxLinearAddress =3D (PagingMode =3D=3D PagingPae) ? LShiftU64 (1, 32) := LShiftU64 (1, 12 + MaxLevel * 9); =20 if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - L= inearAddress)) { // - // Maximum linear address is (1 << 48) or (1 << 57) + // Maximum linear address is (1 << 32), (1 << 48) or (1 << 57) // return RETURN_INVALID_PARAMETER; } @@ -771,6 +770,14 @@ PageTableMap ( IsModified ); if (!RETURN_ERROR (Status)) { + if (PagingMode =3D=3D PagingPae) { + // + // These fields of PAE paging PDPTE should be 0 according to SDM. + // + TopPagingEntry.PdptePae.Bits.MustBeZero =3D 0; + TopPagingEntry.PdptePae.Bits.MustBeZero2 =3D 0; + } + *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); } =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100858): https://edk2.groups.io/g/devel/message/100858 Mute This Topic: https://groups.io/mt/97469487/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100859+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100859+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270168; cv=none; d=zohomail.com; s=zohoarc; b=QTD8hDEkh5LWKJut3h/cP9CmWIzcIwvZX7gGWOrigLw4k7mmYz9YkFnHp8jP3nzuVsk9cnhIe6k0k2uglAPzIvc79G7zR0lfy/8hZidospmkQsmDN3OJWCG11VNVkn2dFP+2rqm5TlnjNnxyP3MO9KgjKPGnkFFAR2IpPJuHK+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270168; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7fhIM6dJm0BpJj4w4GEaGagLZkSWU2ghl6pY4zG88e8=; b=h/dwSOE+VRtq1Dln00G4CC9K6L9gMrUyfywO32IvWykYV72zQZQr2HTPSjfGYmN40+T9VJ7Ai2mhv1BWJAuwFvysbFDoW2uHQ1EiyU2rIyr5x8v5xQJ2TO9Su4fkpjJP/SV9zXSeI9TpAHvwT3O/2Rxnoc0PIKy8xKwgvfkb5to= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100859+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270168229423.4480738382184; Wed, 8 Mar 2023 02:09:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id HHvbYY1788612xwnqaV5flJh; Wed, 08 Mar 2023 02:09:27 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3482.1678270163429735420 for ; Wed, 08 Mar 2023 02:09:25 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442850" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442850" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862861" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862861" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:23 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 12/14] UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging Date: Wed, 8 Mar 2023 18:07:56 +0800 Message-Id: <20230308100758.669-13-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Hh5Mb9JNU8blQVp4g6cFFpmEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270167; bh=tJF30j2/oQMOVfpLTxQtu3g8YwOQsCleJ4q7IELQUOg=; h=Cc:Date:From:Reply-To:Subject:To; b=Kdq+wjwo7Y+l7FLlByPcvtUDpqZx2N5Iseb5yvuSIp+m7KH9WWWOkmkQgIgb8f+zAkN X7y5viG9R91JtE7UpLNQVvWWbXcORcd7RKi4pDs7g+nxL9fhMJbcklB0X4ABm9ri/mI8B LjuAgjIL7hViACKEGUPE3v8MDS9AJ47UbH4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270168457100005 Content-Type: text/plain; charset="utf-8" Add RandomTest for PAE paging. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 2 ++ UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 3 +-- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 5 ++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3df6436af3..06a8fd3c02 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,6 +9,7 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; @@ -865,6 +866,7 @@ UefiTestMain ( goto EXIT; } =20 + AddTestCase (RandomTestCase, "Random Test for PagingPae", "Random Test C= ase1", TestCaseforRandomTest, NULL, NULL, &mTestContextPagingPae); AddTestCase (RandomTestCase, "Random Test for Paging4Level", "Random Tes= t Case1", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging4Level); AddTestCase (RandomTestCase, "Random Test for Paging4Level1G", "Random T= est Case2", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging4Level1GB= ); AddTestCase (RandomTestCase, "Random Test for Paging5Level", "Random Tes= t Case3", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging5Level); diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 8f8f0a5a9f..a7f45fb175 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -251,10 +251,9 @@ ValidateAndRandomeModifyPageTable ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return UNIT_TEST_ERROR_TEST_FAILED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 11f7e607ca..614bd6bbf1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -175,10 +175,9 @@ IsPageTableValid ( return UNIT_TEST_PASSED; } =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return UNIT_TEST_ERROR_TEST_FAILED; } @@ -264,7 +263,7 @@ GetEntryFromPageTable ( UINT64 Index; IA32_PAGING_ENTRY *PagingEntry; =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. // PAE paging will be supported later. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100859): https://edk2.groups.io/g/devel/message/100859 Mute This Topic: https://groups.io/mt/97469488/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100860+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100860+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270170; cv=none; d=zohomail.com; s=zohoarc; b=JzuKtIOydAJZnYI/YxleapoLV11ZGq9VSBcUhHaMkaKo97Cr0lnXoTmKDxPCjv6NcWiXjBxaaJbgy6acpaQcoisPznbvlgTOUy4uLJ2jRAMNymHRbqOWo206No6MmQaf4ovUvNVOyYewqTm1WEL0UnkCb8oNDVKbGCOxreqxDmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270170; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4ZdBb6EdDIn80wj6A0oBPNj/LoASOJjemjY3KIiHpuA=; b=FjYBbHUXItXeFSClNFELy1XBI/5iC3mPRYqE2te0JlhfTcJtGH/6S3nnGSrv0IyzyFkQybv9TwWXqbqnP3JWnX+ImuDXsfqN3cV0N56gxBV8chJWpfUl0umIXEsp92aHSvjYudv4RqPFaxOq1/nwGwCPzUu9cV3zqBGkOm5Y6t0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100860+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678270170138932.1046870764499; Wed, 8 Mar 2023 02:09:30 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 66ZGYY1788612xjIVT4clQva; Wed, 08 Mar 2023 02:09:29 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.3579.1678270169090361638 for ; Wed, 08 Mar 2023 02:09:29 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442881" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442881" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862905" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862905" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:27 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V2 13/14] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf Date: Wed, 8 Mar 2023 18:07:57 +0800 Message-Id: <20230308100758.669-14-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: DI004nh6zyv559GdN4QaOxe9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270169; bh=9CVaO0UFBLvHS0sew/OtVXRB4tKTE986dKvFZNfSJEE=; h=Cc:Date:From:Reply-To:Subject:To; b=n+fiMeD4awy8jjNEm6fp1m20WGhPO/AZ73KdN5V4psrccYnIJXPPSVvw3MJz+7Wz7bh fmS+tdvgFdFqJhSDZvQuQ5U52iKp8ZuhdYOuBkn6mfFSMMvW+mGZwHqz49p2lF5iRoryM JuBguBQzjQrwTSRpT+UgUWy9V9hHclE4PKk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270170601100001 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu Signed-off-by: Ray Ni --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 32 +++++++++++++++= +---------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 125 +++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++---------------------------= ----------------------------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 22 +++++++++++----= ------- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 6 +++--- 4 files changed, 93 insertions(+), 92 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 118dff20f4..a04040123f 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -11,22 +11,22 @@ =20 typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Reserved1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Reserved2 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Reserved1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Reserved2 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_MAP_ATTRIBUTE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 8d856d7c7e..882719546f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -29,11 +29,12 @@ typedef enum { } IA32_PAGE_LEVEL; =20 typedef struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 Reserved : 58; - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 Reserved0 : 29; + UINT32 Reserved1 : 31; + UINT32 Nx : 1; // No Execute bit } IA32_PAGE_COMMON_ENTRY; =20 /// @@ -41,20 +42,20 @@ typedef struct { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Available0 : 1; // Ignored - UINT64 MustBeZero : 1; // Must Be Zero - - UINT64 Available2 : 4; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 11; // Ignored - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Available0 : 1; // Ignored + UINT32 MustBeZero : 1; // Must Be Zero + UINT32 Available2 : 4; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 11; // Ignored + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_NON_LEAF_ENTRY; @@ -86,23 +87,23 @@ typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 MustBeOne : 1; // Page Size. Must Be One - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - UINT64 Pat : 1; // PAT - - UINT64 PageTableBaseAddress : 39; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 MustBeOne : 1; // Page Size. Must Be One + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 Pat : 1; // PAT + UINT32 PageTableBaseAddressLow : 19; // Page Table Base Address Hi= gh + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE; @@ -123,22 +124,22 @@ typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_= 1G; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PTE_4K; @@ -149,16 +150,16 @@ typedef union { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 MustBeZero : 2; // Must Be Zero - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 MustBeZero2 : 4; // Must Be Zero - - UINT64 Available : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 MustBeZero3 : 12; // Must Be Zero + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 MustBeZero : 2; // Must Be Zero + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 MustBeZero2 : 4; // Must Be Zero + UINT32 Available : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 MustBeZero3 : 12; // Must Be Zero } Bits; UINT64 Uint64; } IA32_PDPTE_PAE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index d99a21a0fc..fd5c5b50d2 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -26,7 +26,7 @@ PageTableLibSetPte4K ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { Pte4K->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribu= te) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40); } =20 @@ -93,7 +93,7 @@ PageTableLibSetPleB ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { PleB->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39); } =20 @@ -233,7 +233,7 @@ CheckMaskAndAttrForNotPresentEntry ( if ((Attribute->Bits.Present =3D=3D 0) || (Mask->Bits.Present =3D=3D 0) = || (Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D=3D 0) || (Mask->Bits.WriteThrough =3D= =3D 0) || (Mask->Bits.CacheDisabled =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (Ma= sk->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protection= Key =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.PageTa= bleBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) || (Ma= sk->Bits.Nx =3D=3D 0)) { return RETURN_INVALID_PARAMETER; } @@ -376,7 +376,7 @@ PageTableLibMapInLevel ( PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && - ( (Mask->Bits.PageTableBaseAddress =3D=3D 0) + ( ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.P= ageTableBaseAddressHigh =3D=3D 0)) || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) { @@ -676,7 +676,7 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 - if ((LinearAddress % SIZE_4KB !=3D 0) || (Length % SIZE_4KB !=3D 0)) { + if (((UINTN)LinearAddress % SIZE_4KB !=3D 0) || ((UINTN)Length % SIZE_4K= B !=3D 0)) { // // LinearAddress and Length should be multiple of 4K. // @@ -710,12 +710,12 @@ PageTableMap ( TopPagingEntry.Pce.Nx =3D 0; } =20 - ParentAttribute.Uint64 =3D 0; - ParentAttribute.Bits.PageTableBaseAddress =3D 1; - ParentAttribute.Bits.Present =3D 1; - ParentAttribute.Bits.ReadWrite =3D 1; - ParentAttribute.Bits.UserSupervisor =3D 1; - ParentAttribute.Bits.Nx =3D 0; + ParentAttribute.Uint64 =3D 0; + ParentAttribute.Bits.PageTableBaseAddressLow =3D 1; + ParentAttribute.Bits.Present =3D 1; + ParentAttribute.Bits.ReadWrite =3D 1; + ParentAttribute.Bits.UserSupervisor =3D 1; + ParentAttribute.Bits.Nx =3D 0; =20 // // Query the required buffer size without modifying the page table. diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index c10121ede5..05a40bb225 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -37,9 +37,9 @@ CreatePageTable ( MapAttribute.Bits.Present =3D 1; MapAttribute.Bits.ReadWrite =3D 1; =20 - MapMask.Bits.PageTableBaseAddress =3D 1; - MapMask.Bits.Present =3D 1; - MapMask.Bits.ReadWrite =3D 1; + MapMask.Bits.PageTableBaseAddressLow =3D 1; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; =20 PageTable =3D 0; PageTableBufferSize =3D 0; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100860): https://edk2.groups.io/g/devel/message/100860 Mute This Topic: https://groups.io/mt/97469489/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Mar 28 21:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100861+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100861+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678270172; cv=none; d=zohomail.com; s=zohoarc; b=Nlp9ZvgzYx9NkCs6U3IdElpzvEzaTqMCc/NVTbzlzLkxhQA2ehZyQEcv0yUXIT5On1choSBLAFkNPmZFr5WOvFaePK5kNdzMtLYOQ7KFr+b4fFRUeKaUJb+TUdT/+LVVAaJbPyWDuvNzUKPZMaVpvMxpif9Gw3jN5rbbWdnt7E4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678270172; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=mwXsky2FlnJqh7xf2v7eXjxU6Wdid2QM/FnbOWknn/A=; b=ZDqGZPM1DW2xgxtZm6RJ4V/QKrJCkGuGq03VHBpc0QOlQHFJR9xt+L9cBBL+KH6tKPFGxNLFPqVkPWNPVh4ajkaMloh5j3Zo5MD2lPHnPU0h8ADCWlFvDoc8nKvV4sAGljYcCln82Dm/sETuBQynME1/5VnSE/4FYsAEX1IxSUs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100861+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167827017216458.6497058340849; Wed, 8 Mar 2023 02:09:32 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id JbaxYY1788612xkATPi6jgsE; Wed, 08 Mar 2023 02:09:31 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.3579.1678270169090361638 for ; Wed, 08 Mar 2023 02:09:31 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442901" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442901" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862922" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862922" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:29 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V2 14/14] UefiCpuPkg: Modify UnitTest code since tested API is changed Date: Wed, 8 Mar 2023 18:07:58 +0800 Message-Id: <20230308100758.669-15-dun.tan@intel.com> In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: HJmyc1SlEPjRza1bN7d21luux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678270171; bh=ESDH750PrKM5IKhOrlEEb3LvBpJe2aU3NdENMRcDnDI=; h=Cc:Date:From:Reply-To:Subject:To; b=CH1wShBk2rYvcvKmuXySWo9B4xz+aOU5CC6zMhoZpDscCWkwtiXDVOQvbnWo8Z06+BO qVaZ2Zur0B6ZbU9YIjHyV78G9BcdhAjKQ7ct3hH3ErH3t/RXADXCS78D0O7pI26FVa7bg PSGleA9XWjICiXywZ7MkWp4mUcswp1khzTE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678270172641100005 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 38 ++++++++++++++++++-------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 84 +++++++++++++++++++++++++++++++++++++++++++++++-----------------------= -------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 4 ++-- 3 files changed, 67 insertions(+), 59 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 06a8fd3c02..34e5852579 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -423,15 +423,14 @@ TestCaseManualSizeNotMatch ( UINTN MapCount; IA32_PAGING_ENTRY *PagingEntry; =20 - PagingMode =3D Paging4Level; - PageTableBufferSize =3D 0; - PageTable =3D 0; - Buffer =3D NULL; - MapAttribute.Uint64 =3D 0; - MapMask.Uint64 =3D MAX_UINT64; - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D (SIZE_2MB - SIZE_4KB); + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // @@ -461,9 +460,9 @@ TestCaseManualSizeNotMatch ( // [2M-4K,2M], R/W =3D 0 // [2M ,4M], R/W =3D 1 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 3 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 2 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 3 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 2 level entry PagingEntry->Uint64 =3D PagingEntry->Uint64 & (~(UINT64)0x2); MapCount =3D 0; Status =3D PageTableParse (PageTable, PagingMode, NULL, &Ma= pCount); @@ -481,20 +480,19 @@ TestCaseManualSizeNotMatch ( =20 UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); - ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64; - ExpectedMapAttribute.Bits.ReadWrite =3D 1; - ExpectedMapAttribute.Bits.PageTableBaseAddress =3D SIZE_2MB >> 12; + ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64 + SIZE_4KB; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); =20 // // Set Page table [2M-4K, 2M+4K]'s ReadWrite =3D 1, [2M,2M+4K]'s ReadWri= te is already 1 // Just need to set [2M-4K,2M], won't need extra size, so the status sho= uld be success // - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - PageTableBufferSize =3D 0; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); + MapAttribute.Uint64 =3D SIZE_2MB - SIZE_4KB; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + PageTableBufferSize =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribut= e, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index a7f45fb175..56d894cc04 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( ) { UINT64 Index; - UINT64 TempPhysicalBase; + UINT32 PageTableBaseAddressLow; + UINT32 PageTableBaseAddressHigh; IA32_PAGING_ENTRY *ChildPageEntry; UNIT_TEST_STATUS Status; =20 @@ -180,17 +181,21 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { - TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressLow; + PageTableBaseAddressHigh =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressHigh; } else { - TempPhysicalBase =3D PagingEntry->PleB.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressHigh; } =20 PagingEntry->Uint64 =3D (Random64 (0, MAX_UINT64) & mVal= idMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; PagingEntry->Pte4K.Bits.Present =3D 1; if (Level =3D=3D 1) { - PagingEntry->Pte4K.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Pte4K.Bits.PageTableBaseAddressLow =3D PageTableBase= AddressLow; + PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh =3D PageTableBase= AddressHigh; } else { - PagingEntry->PleB.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseA= ddressLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseA= ddressHigh; } =20 if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) !=3D Paging= Entry->Uint64) { @@ -212,15 +217,17 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( =20 if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; - TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssHigh; =20 - PagingEntry->Uint64 =3D Random64 (0, MAX_UINT6= 4) & mValidMaskNoLeaf[Level].Uint64; - PagingEntry->Pnle.Bits.Present =3D 1; - PagingEntry->Pnle.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Uint64 =3D Random64 (0, MAX_U= INT64) & mValidMaskNoLeaf[Level].Uint64; + PagingEntry->Pnle.Bits.Present =3D 1; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseAddre= ssLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseAddre= ssHigh; ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) !=3D = mValidMaskLeafFlag[Level].Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry->Pnle.Bits= .PageTableBaseAddress) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPage= Entry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -363,10 +370,12 @@ GenerateSingleRandomMapEntry ( } =20 if (mRandomOption & ONLY_ONE_ONE_MAPPING) { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D MapEntrys->Maps[MapsI= ndex].LinearAddress; + MapEntrys->Maps[MapsIndex].Mask.Uint64 |=3D IA32_MAP_ATTRIBUTE_PA= GE_TABLE_BASE_ADDRESS_MASK; } else { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D (Random64 (0, (((UINT= 64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]); } =20 MapEntrys->Count +=3D 1; @@ -413,8 +422,9 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < MapCount; Index++) { if ((Address >=3D Map[Index].LinearAddress) && (Address < (Map[Index].= LinearAddress + Map[Index].Length))) { - AttributeInMap.Uint64 =3D (Map[Index].Attribute.U= int64 & mSupportedBit.Uint64); - AttributeInMap.Bits.PageTableBaseAddress =3D ((Address - Map[Index].= LinearAddress) >> 12) + Map[Index].Attribute.Bits.PageTableBaseAddress; + AttributeInMap.Uint64 =3D (Map[Index].Attribute.Uint64 & mSupported= Bit.Uint64); + AttributeInMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDR= ESS_MASK); + AttributeInMap.Uint64 |=3D (Address - Map[Index].LinearAddress + IA3= 2_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&Map[Index].Attribute)) & IA32_MAP= _ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; break; } } @@ -424,8 +434,10 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < InitMapCount; Index++) { if ((Address >=3D InitMap[Index].LinearAddress) && (Address < (InitMap= [Index].LinearAddress + InitMap[Index].Length))) { - AttributeInInitMap.Uint64 =3D (InitMap[Index].Att= ribute.Uint64 & mSupportedBit.Uint64); - AttributeInInitMap.Bits.PageTableBaseAddress =3D ((Address - InitMap= [Index].LinearAddress) >> 12) + InitMap[Index].Attribute.Bits.PageTableBase= Address; + AttributeInInitMap.Uint64 =3D (InitMap[Index].Attribute.Uint64 & mS= upportedBit.Uint64); + AttributeInInitMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_= ADDRESS_MASK); + AttributeInInitMap.Uint64 |=3D (Address - InitMap[Index].LinearAddre= ss + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&InitMap[Index].Attribute)= ) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; + break; } } @@ -442,8 +454,9 @@ CompareEntrysforOnePoint ( MaskInMapEntrys.Uint64 |=3D MapEntrys->Maps[Index].Mask.Uint64; AttributeInMapEntrys.Uint64 &=3D (~MapEntrys->Maps[Index].Mask.Uint6= 4); AttributeInMapEntrys.Uint64 |=3D (MapEntrys->Maps[Index].Attribute.= Uint64 & MapEntrys->Maps[Index].Mask.Uint64); - if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress !=3D 0) { - AttributeInMapEntrys.Bits.PageTableBaseAddress =3D ((Address - Map= Entrys->Maps[Index].LinearAddress) >> 12) + MapEntrys->Maps[Index].Attribut= e.Bits.PageTableBaseAddress; + if (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Ind= ex].Mask) !=3D 0) { + AttributeInMapEntrys.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_B= ASE_ADDRESS_MASK); + AttributeInMapEntrys.Uint64 |=3D (Address - MapEntrys->Maps[Index]= .LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Ma= ps[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; } } } @@ -457,8 +470,8 @@ CompareEntrysforOnePoint ( if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) !=3D (AttributeInMa= pEntrys.Uint64 & MaskInMapEntrys.Uint64)) { DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3Ddetailed information begin=3D= =3D=3D=3D=3D\n")); DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point wi= th linear address: 0x%lx\n", Address)); - DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBase= Address)); - DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, AttributeInMa= pEntrys.Bits.PageTableBaseAddress)); + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BAS= E_ADDRESS (&AttributeInMap))); + DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, IA32_MAP_ATTR= IBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMapEntrys))); DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint6= 4)); =20 if (MapEntrys->InitCount !=3D 0) { @@ -721,7 +734,7 @@ SingleMapEntryTest ( if (((Attribute->Bits.Present =3D=3D 0) || (Mask->Bits.Present =3D=3D 0)= || (Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D=3D 0) || (Mask->Bits.WriteThrough = =3D=3D 0) || (Mask->Bits.CacheDisabled =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (M= ask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protectio= nKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) && + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.PageT= ableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) || (M= ask->Bits.Nx =3D=3D 0)) && IsNotPresent) { RemoveLastMapEntry (MapEntrys); @@ -1000,21 +1013,18 @@ TestCaseforRandomTest ( UT_ASSERT_EQUAL (Random64 (100, 100), 100); UT_ASSERT_TRUE ((Random32 (9, 10) >=3D 9) & (Random32 (9, 10) <=3D 10)); UT_ASSERT_TRUE ((Random64 (9, 10) >=3D 9) & (Random64 (9, 10) <=3D 10)); - - mSupportedBit.Bits.Present =3D 1; - mSupportedBit.Bits.ReadWrite =3D 1; - mSupportedBit.Bits.UserSupervisor =3D 1; - mSupportedBit.Bits.WriteThrough =3D 1; - mSupportedBit.Bits.CacheDisabled =3D 1; - mSupportedBit.Bits.Accessed =3D 1; - mSupportedBit.Bits.Dirty =3D 1; - mSupportedBit.Bits.Pat =3D 1; - mSupportedBit.Bits.Global =3D 1; - mSupportedBit.Bits.Reserved1 =3D 0; - mSupportedBit.Bits.PageTableBaseAddress =3D 0; - mSupportedBit.Bits.Reserved2 =3D 0; - mSupportedBit.Bits.ProtectionKey =3D 0xF; - mSupportedBit.Bits.Nx =3D 1; + mSupportedBit.Uint64 =3D 0; + mSupportedBit.Bits.Present =3D 1; + mSupportedBit.Bits.ReadWrite =3D 1; + mSupportedBit.Bits.UserSupervisor =3D 1; + mSupportedBit.Bits.WriteThrough =3D 1; + mSupportedBit.Bits.CacheDisabled =3D 1; + mSupportedBit.Bits.Accessed =3D 1; + mSupportedBit.Bits.Dirty =3D 1; + mSupportedBit.Bits.Pat =3D 1; + mSupportedBit.Bits.Global =3D 1; + mSupportedBit.Bits.ProtectionKey =3D 0xF; + mSupportedBit.Bits.Nx =3D 1; =20 mRandomOption =3D ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->R= andomOption; mNumberIndex =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 614bd6bbf1..64c42c5135 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -140,7 +140,7 @@ IsPageTableEntryValid ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, Max= LeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -232,7 +232,7 @@ GetEntryFromSubPageTable ( // // Not a leaf // - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); *Level =3D *Level -1; Index =3D Address >> (*Level * 9 + 3); ASSERT (Index =3D=3D (Index & ((1<< 9) - 1))); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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