From nobody Sun May 5 22:20:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100705+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100705+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678062134; cv=none; d=zohomail.com; s=zohoarc; b=Z9ZdfNGMKB6nYalYpQw7AiWmCqcpBGRcfxYUHypBoWW5USaw4UHKfq32QDcDy7yJ0xuMoZZO7Ko/4fm7RdHp37QlgP27GiU3xzJh2iQJkuvLO4B4v5pf+Blb6KoQzMd3r81pkyMxUACk1oqCvDIjSpXkBKn20HSD7OGLsbrA4wg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678062134; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=DHD5gCWd+tQRTn7/en5jtEKuCcNm8v5NkTt35skDbX4=; b=SwV7R3PmEV2UZ4CeR9/dLnIqoY4VClgAuJwi0oIsaIEpBc9emRuTLfmVpVqfNnCjX03koPjkdzCkmhc7BolBZUKP10I0LCx/WHlwQo0aKezoyI7ehXKwIh9eBFP9jqMD7U8aC52AanF5wRoLiPGTQIp6UFqbvy87EDoPjKLLOw0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100705+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678062134251421.8146875207491; Sun, 5 Mar 2023 16:22:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id oF9aYY1788612ximD1CAO7Qf; Sun, 05 Mar 2023 16:22:13 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.22191.1678062132259075315 for ; Sun, 05 Mar 2023 16:22:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="337758110" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="337758110" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="669263309" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="669263309" X-Received: from nldesimo-desk.amr.corp.intel.com ([10.24.12.177]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Sami Mujawar , Michael D Kinney , Chasel Chiu Subject: [edk2-devel] [PATCH v1 1/6] ArmPkg: Add ArmMmuNullLib Date: Sun, 5 Mar 2023 16:22:00 -0800 Message-Id: <20230306002205.1640-2-nathaniel.l.desimone@intel.com> In-Reply-To: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> References: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: Jzno6Tla26FVcU5uMaqcuHX9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678062133; bh=lBwpJrK5p5anGfV4y6vZt7B9Sgtd3m/ue+16X9FQ9Nk=; h=Cc:Date:From:Reply-To:Subject:To; b=aVezwoPCbTiUIcXOhIE2Ocffcky01vdeDlECq7agYLgWhUDFPZKyt+gzBhW0n8BIK/+ EjB7DP6s6SQo0euc/RVPsCx7b7cJJs1ExuRrh0xSNINvtv2fHoasBRe0dN9Q1qb6XHoMT oilK8HtHrq5WXgjFms8DfpifHRHiSKejzmQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678062136083100003 Content-Type: text/plain; charset="utf-8" Adds a NULL implementation of the ArmMmuLib. This is nessesary for ARM support in EmulatorPkg due to DxeIplPeim requiring an implementation of ArmMmuLib. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Sami Mujawar Cc: Michael D Kinney Cc: Chasel Chiu Signed-off-by: Nate DeSimone Tested-by: Ard Biesheuvel --- ArmPkg/ArmPkg.dsc | 2 + ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.c | 84 +++++++++++++++++++ .../Library/ArmMmuNullLib/ArmMmuNullLib.inf | 36 ++++++++ 3 files changed, 122 insertions(+) create mode 100644 ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.c create mode 100644 ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.inf diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc index 3fb95d1951..3dc2c21e9d 100644 --- a/ArmPkg/ArmPkg.dsc +++ b/ArmPkg/ArmPkg.dsc @@ -6,6 +6,7 @@ # Copyright (c) 2016, Linaro Ltd. All rights reserved.
# Copyright (c) Microsoft Corporation.
# Copyright (c) 2021, Ampere Computing LLC. All rights reserved. +# Copyright (c) 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -142,6 +143,7 @@ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf =20 ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.inf =20 ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf diff --git a/ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.c b/ArmPkg/Library/= ArmMmuNullLib/ArmMmuNullLib.c new file mode 100644 index 0000000000..f91582f86a --- /dev/null +++ b/ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.c @@ -0,0 +1,84 @@ +/** @file + ARM MMU NULL Library + +Copyright (c) 2023, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +EFI_STATUS +EFIAPI +ArmConfigureMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, + OUT VOID **TranslationTableBase OPTIONAL, + OUT UINTN *TranslationTableSize OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +ArmSetMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +ArmClearMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +ArmSetMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +ArmClearMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return EFI_UNSUPPORTED; +} + +VOID +EFIAPI +ArmReplaceLiveTranslationEntry ( + IN UINT64 *Entry, + IN UINT64 Value, + IN UINT64 RegionStart, + IN BOOLEAN DisableMmu + ) +{ + return; +} + +EFI_STATUS +ArmSetMemoryAttributes ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.inf b/ArmPkg/Librar= y/ArmMmuNullLib/ArmMmuNullLib.inf new file mode 100644 index 0000000000..fa6791f3d9 --- /dev/null +++ b/ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.inf @@ -0,0 +1,36 @@ +## @file +# Module Information description file for ARM MMU NULL Library +# +# For user space environments like EmulatorPkg +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D ArmMmuNullLib + FILE_GUID =3D E61735C8-DD00-4C4A-B07B-FD71A67C239D + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D ArmMmuLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES ARM AARCH64 +# + +[LibraryClasses] + + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[Pcd] + +[Sources] + ArmMmuNullLib.c + +[Guids] --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100705): https://edk2.groups.io/g/devel/message/100705 Mute This Topic: https://groups.io/mt/97414909/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 22:20:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100704+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100704+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678062133; cv=none; d=zohomail.com; s=zohoarc; b=jWxtg3KmrYwdYqUnXPZ6OEyMYMUuLwA3FgAvk4s++YFdoAr1XWt7MPSmbQv6jUdxNujrJ4w/aYRAHpHazjoj3+jgsV4uxIfRxXjqaXR+AH9L9J3S2n1eLLcf35STArezFiazPRGYXbEim81fQ7C+29Ia3pFhf3s5WR/Q6HCyqJ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678062133; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jY3pkpzw6EvoRM8IGGfXSq7K9hDIwzbTdEErBE8oOI0=; b=JEvnJHCOtKtqge2fJC9HV8b5SLo5f4E9iSAol1uFEKuWgMKdmZfd0jUhJVC5c/fKo1piQO813Z5r9+zv0wmI44dieOqe0lTGy62rLfc0OcdT6ZOellXzlkv9l7s27uywPh9ucnAluQ6Kvpl8xVPdRwMa3qPZaLbpuY0n+iIvN/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100704+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678062133778117.47605310795223; Sun, 5 Mar 2023 16:22:13 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1C5PYY1788612xm1NJaYN75z; Sun, 05 Mar 2023 16:22:13 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.22191.1678062132259075315 for ; Sun, 05 Mar 2023 16:22:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="337758114" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="337758114" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="669263312" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="669263312" X-Received: from nldesimo-desk.amr.corp.intel.com ([10.24.12.177]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Andrew Fish , Ray Ni , Michael D Kinney , Chasel Chiu Subject: [edk2-devel] [PATCH v1 2/6] EmulatorPkg: Add ARM Build Target Date: Sun, 5 Mar 2023 16:22:01 -0800 Message-Id: <20230306002205.1640-3-nathaniel.l.desimone@intel.com> In-Reply-To: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> References: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: 7SgqmhcyoSzaiqoXzGAKAbCWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678062133; bh=qbYe4r73vvP6VWPYZGu+9f88nUzRQieDEz6iLrOHyzE=; h=Cc:Date:From:Reply-To:Subject:To; b=SYD++M5yMmomZgw1FP7jFC4mdWzgITqScBwjJrK+UAqvo0gMrCciK55Fkj6ujXihjW6 bbP801hcKh2wKoLxMo1+LjhjWh2hkiOIWTAIkwu6nazoDo3KXkk4eLgcnTbXZN85n8wSr Lc7LjQTF7gTj0GP6uqwqIFmPaOOtiixOlnI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678062134081100001 Content-Type: text/plain; charset="utf-8" Adds the ARM build target to EmulatorPkg. Moves PcdDxeIplSwitchToLongMode and PcdDxeIplBuildPageTables to only apply for the IA32 and X64 build targets since they are not used on ARM. Adds ARM compiler instrinsics libraries. Adds NULL implementation of ArmMmuLib. Disables EbcDxe on ARM builds since EbcDxe does not support the ARM architecture. Cc: Andrew Fish Cc: Ray Ni Cc: Michael D Kinney Cc: Chasel Chiu Signed-off-by: Nate DeSimone Tested-by: Ard Biesheuvel --- EmulatorPkg/EmulatorPkg.dsc | 17 ++++++++++++++--- EmulatorPkg/EmulatorPkg.fdf | 6 ++++-- EmulatorPkg/build.sh | 13 ++++++++++++- 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc index b44435d7e6..19ba60aa23 100644 --- a/EmulatorPkg/EmulatorPkg.dsc +++ b/EmulatorPkg/EmulatorPkg.dsc @@ -4,7 +4,7 @@ # The Emulation Platform can be used to debug individual modules, prior to= creating # a real platform. This also provides an example for how an DSC is created. # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# Portions copyright (c) 2010 - 2011, Apple Inc. All rights reserved.
# Copyright (c) Microsoft Corporation. # @@ -19,7 +19,7 @@ DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/Emulator$(ARCH) =20 - SUPPORTED_ARCHITECTURES =3D X64|IA32 + SUPPORTED_ARCHITECTURES =3D X64|IA32|ARM BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D EmulatorPkg/EmulatorPkg.fdf @@ -140,6 +140,13 @@ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf !endif =20 +[LibraryClasses.ARM] + ArmMmuLib|ArmPkg/Library/ArmMmuNullLib/ArmMmuNullLib.inf + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + [LibraryClasses.common.SEC] PeiServicesLib|EmulatorPkg/Library/SecPeiServicesLib/SecPeiServicesLib.i= nf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf @@ -211,8 +218,10 @@ TimerLib|EmulatorPkg/Library/DxeTimerLib/DxeTimerLib.inf =20 [PcdsFeatureFlag] - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE + +[PcdsFeatureFlag.IA32, PcdsFeatureFlag.X64] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplBuildPageTables|FALSE =20 [PcdsFixedAtBuild] @@ -368,7 +377,9 @@ !endif } =20 +!if "ARM" not in $(ARCH) MdeModulePkg/Universal/EbcDxe/EbcDxe.inf +!endif MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf EmulatorPkg/EmuThunkDxe/EmuThunk.inf EmulatorPkg/CpuRuntimeDxe/Cpu.inf diff --git a/EmulatorPkg/EmulatorPkg.fdf b/EmulatorPkg/EmulatorPkg.fdf index 5420756eaa..06f002a624 100644 --- a/EmulatorPkg/EmulatorPkg.fdf +++ b/EmulatorPkg/EmulatorPkg.fdf @@ -1,7 +1,7 @@ ## @file # This is Emulator FDF file with UEFI HII features enabled # -# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
# Portions copyright (c) 2009 - 2011, Apple Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -148,7 +148,9 @@ INF EmulatorPkg/ResetRuntimeDxe/Reset.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF EmulatorPkg/FvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf +!if "ARM" not in $(ARCH) + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf +!endif INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf INF EmulatorPkg/EmuThunkDxe/EmuThunk.inf INF EmulatorPkg/CpuRuntimeDxe/Cpu.inf diff --git a/EmulatorPkg/build.sh b/EmulatorPkg/build.sh index 76c22dfaf8..55f9cbaa1b 100755 --- a/EmulatorPkg/build.sh +++ b/EmulatorPkg/build.sh @@ -1,7 +1,7 @@ #!/bin/bash # # Copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
-# Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -83,6 +83,15 @@ case `uname` in x86_64) HOST_PROCESSOR=3DX64 ;; + armv6l) + HOST_PROCESSOR=3DARM + ;; + armv7l) + HOST_PROCESSOR=3DARM + ;; + armv8l) + HOST_PROCESSOR=3DARM + ;; esac =20 gcc_version=3D$(gcc -v 2>&1 | tail -1 | awk '{print $3}') @@ -174,6 +183,8 @@ case $PROCESSOR in LIB_NAMES=3D"ld-linux-x86-64.so.2 libdl.so.2 crt1.o crti.o crtn.o" LIB_SEARCH_PATHS=3D"/usr/lib/x86_64-linux-gnu /usr/lib64 /lib64 /usr/l= ib /lib" ;; + ARM) + ARCH_SIZE=3D32 esac =20 for libname in $LIB_NAMES --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100704): https://edk2.groups.io/g/devel/message/100704 Mute This Topic: https://groups.io/mt/97414908/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 22:20:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100707+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100707+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678062135; cv=none; d=zohomail.com; s=zohoarc; b=QZfLDszcDEyWjeqssv32l2JUZP3Ff2JwGyvSx5U5HF4HZtgZ8WgbHkd1V+eVKRSbAFYo6XmdbxSDbuhwagt9V4TeFDEmQgKgG1br41cjIpLaZQpztfW2C2QSt7Nw4SItYr8dOz1SAJhZbtHjLulL/yxN/POYgyspNDAAgBublKI= ARC-Message-Signature: i=1; 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Sun, 05 Mar 2023 16:22:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="337758115" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="337758115" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="669263316" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="669263316" X-Received: from nldesimo-desk.amr.corp.intel.com ([10.24.12.177]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Andrew Fish , Ray Ni , Michael D Kinney , Chasel Chiu Subject: [edk2-devel] [PATCH v1 3/6] EmulatorPkg: Fix PosixFileSystem function misspellings Date: Sun, 5 Mar 2023 16:22:02 -0800 Message-Id: <20230306002205.1640-4-nathaniel.l.desimone@intel.com> In-Reply-To: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> References: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: ahskbvYk1jM3OtRZjpv4Nqfrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678062135; bh=cYQ+lhTrbjSNpRk1vwYHKnwnjN0exZkbEBsFVsqNy28=; h=Cc:Date:From:Reply-To:Subject:To; b=tQCZDeLsRoELJ3+xHWX6pfFU28nQqq34n1e4cAoLljRDVPu5qHIB++BmZk4pjyjLoWt 4YoR0LF41juuL+g4xPG8oBmYUY56ABzTVpsnhixTKJFTagqwEi/TSfaU16UDuAt5yI/2q wWuH6FC8U2XxAFN6kLeHeM4e3Zw5BV3Brm8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678062136121100011 Content-Type: text/plain; charset="utf-8" Fixes spelling errors in the following function names: GasketPosixFileCLose --> GasketPosixFileClose PosixFileCLose --> PosixFileClose GasketPosixFileSetPossition --> GasketPosixFileSetPosition PosixFileSetPossition --> PosixFileSetPosition GasketPosixFileGetPossition --> GasketPosixFileGetPosition PosixFileGetPossition --> PosixFileGetPosition GasketPosixFileSystmeThunkOpen --> GasketPosixFileSystemThunkOpen PosixFileSystmeThunkOpen --> PosixFileSystemThunkOpen GasketPosixFileSystmeThunkClose --> GasketPosixFileSystemThunkClose PosixFileSystmeThunkClose --> PosixFileSystemThunkClose Cc: Andrew Fish Cc: Ray Ni Cc: Michael D Kinney Cc: Chasel Chiu Signed-off-by: Nate DeSimone Tested-by: Ard Biesheuvel --- EmulatorPkg/Unix/Host/Gasket.h | 12 +++++----- EmulatorPkg/Unix/Host/Ia32/Gasket.S | 31 +++++++++++++------------ EmulatorPkg/Unix/Host/PosixFileSystem.c | 22 +++++++++--------- EmulatorPkg/Unix/Host/X64/Gasket.S | 31 +++++++++++++------------ 4 files changed, 49 insertions(+), 47 deletions(-) diff --git a/EmulatorPkg/Unix/Host/Gasket.h b/EmulatorPkg/Unix/Host/Gasket.h index 6dafc903cf..90c591e024 100644 --- a/EmulatorPkg/Unix/Host/Gasket.h +++ b/EmulatorPkg/Unix/Host/Gasket.h @@ -1,7 +1,7 @@ /** @file =20 Copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
- Copyright (c) 2011 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 - 2023, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -360,7 +360,7 @@ GasketPosixFileOpen ( =20 EFI_STATUS EFIAPI -GasketPosixFileCLose ( +GasketPosixFileClose ( IN EFI_FILE_PROTOCOL *This ); =20 @@ -388,14 +388,14 @@ GasketPosixFileWrite ( =20 EFI_STATUS EFIAPI -GasketPosixFileSetPossition ( +GasketPosixFileSetPosition ( IN EFI_FILE_PROTOCOL *This, IN UINT64 Position ); =20 EFI_STATUS EFIAPI -GasketPosixFileGetPossition ( +GasketPosixFileGetPosition ( IN EFI_FILE_PROTOCOL *This, OUT UINT64 *Position ); @@ -426,13 +426,13 @@ GasketPosixFileFlush ( =20 EFI_STATUS EFIAPI -GasketPosixFileSystmeThunkOpen ( +GasketPosixFileSystemThunkOpen ( IN EMU_IO_THUNK_PROTOCOL *This ); =20 EFI_STATUS EFIAPI -GasketPosixFileSystmeThunkClose ( +GasketPosixFileSystemThunkClose ( IN EMU_IO_THUNK_PROTOCOL *This ); =20 diff --git a/EmulatorPkg/Unix/Host/Ia32/Gasket.S b/EmulatorPkg/Unix/Host/Ia= 32/Gasket.S index 36197ff260..f4c2b456d8 100644 --- a/EmulatorPkg/Unix/Host/Ia32/Gasket.S +++ b/EmulatorPkg/Unix/Host/Ia32/Gasket.S @@ -7,6 +7,7 @@ # the code common. # # Copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # #-------------------------------------------------------------------------= ----- @@ -847,8 +848,8 @@ ASM_PFX(GasketPosixFileOpen): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileCLose) -ASM_PFX(GasketPosixFileCLose): +ASM_GLOBAL ASM_PFX(GasketPosixFileClose) +ASM_PFX(GasketPosixFileClose): pushl %ebp movl %esp, %ebp subl $24, %esp // sub extra 16 from the stack for alignment @@ -856,7 +857,7 @@ ASM_PFX(GasketPosixFileCLose): movl 8(%ebp), %eax movl %eax, (%esp) =20 - call ASM_PFX(PosixFileCLose) + call ASM_PFX(PosixFileClose) =20 leave ret @@ -915,8 +916,8 @@ ASM_PFX(GasketPosixFileWrite): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileSetPossition) -ASM_PFX(GasketPosixFileSetPossition): +ASM_GLOBAL ASM_PFX(GasketPosixFileSetPosition) +ASM_PFX(GasketPosixFileSetPosition): pushl %ebp movl %esp, %ebp subl $40, %esp // sub extra 16 from the stack for alignment @@ -928,14 +929,14 @@ ASM_PFX(GasketPosixFileSetPossition): movl 8(%ebp), %eax movl %eax, (%esp) =20 - call ASM_PFX(PosixFileSetPossition) + call ASM_PFX(PosixFileSetPosition) =20 leave ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileGetPossition) -ASM_PFX(GasketPosixFileGetPossition): +ASM_GLOBAL ASM_PFX(GasketPosixFileGetPosition) +ASM_PFX(GasketPosixFileGetPosition): pushl %ebp movl %esp, %ebp subl $24, %esp // sub extra 16 from the stack for alignment @@ -945,7 +946,7 @@ ASM_PFX(GasketPosixFileGetPossition): movl 8(%ebp), %eax movl %eax, (%esp) =20 - call ASM_PFX(PosixFileGetPossition) + call ASM_PFX(PosixFileGetPosition) =20 leave ret @@ -1008,8 +1009,8 @@ ASM_PFX(GasketPosixFileFlush): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileSystmeThunkOpen) -ASM_PFX(GasketPosixFileSystmeThunkOpen): +ASM_GLOBAL ASM_PFX(GasketPosixFileSystemThunkOpen) +ASM_PFX(GasketPosixFileSystemThunkOpen): pushl %ebp movl %esp, %ebp subl $24, %esp // sub extra 16 from the stack for alignment @@ -1017,14 +1018,14 @@ ASM_PFX(GasketPosixFileSystmeThunkOpen): movl 8(%ebp), %eax movl %eax, (%esp) =20 - call ASM_PFX(PosixFileSystmeThunkOpen) + call ASM_PFX(PosixFileSystemThunkOpen) =20 leave ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileSystmeThunkClose) -ASM_PFX(GasketPosixFileSystmeThunkClose): +ASM_GLOBAL ASM_PFX(GasketPosixFileSystemThunkClose) +ASM_PFX(GasketPosixFileSystemThunkClose): pushl %ebp movl %esp, %ebp subl $24, %esp // sub extra 16 from the stack for alignment @@ -1032,7 +1033,7 @@ ASM_PFX(GasketPosixFileSystmeThunkClose): movl 8(%ebp), %eax movl %eax, (%esp) =20 - call ASM_PFX(PosixFileSystmeThunkClose) + call ASM_PFX(PosixFileSystemThunkClose) =20 leave ret diff --git a/EmulatorPkg/Unix/Host/PosixFileSystem.c b/EmulatorPkg/Unix/Hos= t/PosixFileSystem.c index b69d3d5520..3a86d6675c 100644 --- a/EmulatorPkg/Unix/Host/PosixFileSystem.c +++ b/EmulatorPkg/Unix/Host/PosixFileSystem.c @@ -2,7 +2,7 @@ POSIX Pthreads to emulate APs and implement threads =20 Copyright (c) 2011, Apple Inc. All rights reserved. -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 =20 @@ -70,12 +70,12 @@ PosixFileSetInfo ( EFI_FILE_PROTOCOL gPosixFileProtocol =3D { EFI_FILE_REVISION, GasketPosixFileOpen, - GasketPosixFileCLose, + GasketPosixFileClose, GasketPosixFileDelete, GasketPosixFileRead, GasketPosixFileWrite, - GasketPosixFileGetPossition, - GasketPosixFileSetPossition, + GasketPosixFileGetPosition, + GasketPosixFileSetPosition, GasketPosixFileGetInfo, GasketPosixFileSetInfo, GasketPosixFileFlush @@ -643,7 +643,7 @@ Done:; =20 **/ EFI_STATUS -PosixFileCLose ( +PosixFileClose ( IN EFI_FILE_PROTOCOL *This ) { @@ -883,7 +883,7 @@ PosixFileWrite ( =20 **/ EFI_STATUS -PosixFileSetPossition ( +PosixFileSetPosition ( IN EFI_FILE_PROTOCOL *This, IN UINT64 Position ) @@ -930,7 +930,7 @@ PosixFileSetPossition ( =20 **/ EFI_STATUS -PosixFileGetPossition ( +PosixFileGetPosition ( IN EFI_FILE_PROTOCOL *This, OUT UINT64 *Position ) @@ -1473,7 +1473,7 @@ PosixFileFlush ( } =20 EFI_STATUS -PosixFileSystmeThunkOpen ( +PosixFileSystemThunkOpen ( IN EMU_IO_THUNK_PROTOCOL *This ) { @@ -1530,7 +1530,7 @@ PosixFileSystmeThunkOpen ( } =20 EFI_STATUS -PosixFileSystmeThunkClose ( +PosixFileSystemThunkClose ( IN EMU_IO_THUNK_PROTOCOL *This ) { @@ -1566,7 +1566,7 @@ EMU_IO_THUNK_PROTOCOL gPosixFileSystemThunkIo =3D { NULL, NULL, 0, - GasketPosixFileSystmeThunkOpen, - GasketPosixFileSystmeThunkClose, + GasketPosixFileSystemThunkOpen, + GasketPosixFileSystemThunkClose, NULL }; diff --git a/EmulatorPkg/Unix/Host/X64/Gasket.S b/EmulatorPkg/Unix/Host/X64= /Gasket.S index 030faa8e4c..e82c9d4ad6 100644 --- a/EmulatorPkg/Unix/Host/X64/Gasket.S +++ b/EmulatorPkg/Unix/Host/X64/Gasket.S @@ -8,6 +8,7 @@ # RSI, RDI calle-save on EFI, scatch on UNIX callign # # Copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # #-------------------------------------------------------------------------= ----- @@ -941,8 +942,8 @@ ASM_PFX(GasketPosixFileOpen): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileCLose) -ASM_PFX(GasketPosixFileCLose): +ASM_GLOBAL ASM_PFX(GasketPosixFileClose) +ASM_PFX(GasketPosixFileClose): pushq %rbp // stack frame is for the debugger movq %rsp, %rbp =20 @@ -951,7 +952,7 @@ ASM_PFX(GasketPosixFileCLose): =20 movq %rcx, %rdi // Swizzle args =20 - call ASM_PFX(PosixFileCLose) + call ASM_PFX(PosixFileClose) =20 popq %rdi // restore state popq %rsi @@ -1017,8 +1018,8 @@ ASM_PFX(GasketPosixFileWrite): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileSetPossition) -ASM_PFX(GasketPosixFileSetPossition): +ASM_GLOBAL ASM_PFX(GasketPosixFileSetPosition) +ASM_PFX(GasketPosixFileSetPosition): pushq %rbp // stack frame is for the debugger movq %rsp, %rbp =20 @@ -1028,7 +1029,7 @@ ASM_PFX(GasketPosixFileSetPossition): movq %rcx, %rdi // Swizzle args movq %rdx, %rsi =20 - call ASM_PFX(PosixFileSetPossition) + call ASM_PFX(PosixFileSetPosition) =20 popq %rdi // restore state popq %rsi @@ -1036,8 +1037,8 @@ ASM_PFX(GasketPosixFileSetPossition): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileGetPossition) -ASM_PFX(GasketPosixFileGetPossition): +ASM_GLOBAL ASM_PFX(GasketPosixFileGetPosition) +ASM_PFX(GasketPosixFileGetPosition): pushq %rbp // stack frame is for the debugger movq %rsp, %rbp =20 @@ -1047,7 +1048,7 @@ ASM_PFX(GasketPosixFileGetPossition): movq %rcx, %rdi // Swizzle args movq %rdx, %rsi =20 - call ASM_PFX(PosixFileGetPossition) + call ASM_PFX(PosixFileGetPosition) =20 popq %rdi // restore state popq %rsi @@ -1115,8 +1116,8 @@ ASM_PFX(GasketPosixFileFlush): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileSystmeThunkOpen) -ASM_PFX(GasketPosixFileSystmeThunkOpen): +ASM_GLOBAL ASM_PFX(GasketPosixFileSystemThunkOpen) +ASM_PFX(GasketPosixFileSystemThunkOpen): pushq %rbp // stack frame is for the debugger movq %rsp, %rbp =20 @@ -1125,7 +1126,7 @@ ASM_PFX(GasketPosixFileSystmeThunkOpen): =20 movq %rcx, %rdi // Swizzle args =20 - call ASM_PFX(PosixFileSystmeThunkOpen) + call ASM_PFX(PosixFileSystemThunkOpen) =20 popq %rdi // restore state popq %rsi @@ -1133,8 +1134,8 @@ ASM_PFX(GasketPosixFileSystmeThunkOpen): ret =20 =20 -ASM_GLOBAL ASM_PFX(GasketPosixFileSystmeThunkClose) -ASM_PFX(GasketPosixFileSystmeThunkClose): +ASM_GLOBAL ASM_PFX(GasketPosixFileSystemThunkClose) +ASM_PFX(GasketPosixFileSystemThunkClose): pushq %rbp // stack frame is for the debugger movq %rsp, %rbp =20 @@ -1143,7 +1144,7 @@ ASM_PFX(GasketPosixFileSystmeThunkClose): =20 movq %rcx, %rdi // Swizzle args =20 - call ASM_PFX(PosixFileSystmeThunkClose) + call ASM_PFX(PosixFileSystemThunkClose) =20 popq %rdi // restore state popq %rsi --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100707): https://edk2.groups.io/g/devel/message/100707 Mute This Topic: https://groups.io/mt/97414911/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 22:20:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100709+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100709+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678062140; cv=none; d=zohomail.com; s=zohoarc; b=g8fvYF0wcFcVJYJO3wXwKO1/9qADkbwv03Ha35CSAf1kUq7psr5WL6F2+bbVhaVieMkT8c/PYs/kBzFTZ9jUJoQY0WWlxAioSnXf8CQforaXTOwlXWRqTeYKOZxwn992MH5mMVa6vEQ7ytjft1BLGCBS06pIMsXHPM/CDGybANo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678062140; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=W8hiPnIHQ5q12AZY73qjvkP15KZdGOjRTcBU3A6X8Jk=; b=fVV/vL5JJAIyPXuegP9atycmebbXb+MzOYlYLXr2PXwcU7jmgL/ELhEAQXirUR9PI/MiMEbMx2Mf9hABcuRVQREkRIYRBZzmUNspf+bs4ftDfDs0eHkDPBD40mwMGk58w6qqHiyoF+lKK+svkQImLEfyqJFmKgI4wCBb8ns47B0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100709+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678062140008175.42271844286927; Sun, 5 Mar 2023 16:22:20 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id OBsWYY1788612xZ0DIwJLDEz; Sun, 05 Mar 2023 16:22:19 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.22095.1678062133152377972 for ; Sun, 05 Mar 2023 16:22:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="337758117" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="337758117" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="669263320" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="669263320" X-Received: from nldesimo-desk.amr.corp.intel.com ([10.24.12.177]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Andrew Fish , Ray Ni , Michael D Kinney , Chasel Chiu Subject: [edk2-devel] [PATCH v1 4/6] EmulatorPkg: Add ARM support to UNIX Host App Date: Sun, 5 Mar 2023 16:22:03 -0800 Message-Id: <20230306002205.1640-5-nathaniel.l.desimone@intel.com> In-Reply-To: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> References: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: oPP5s1U4IJT2auJOG0KICD1Dx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678062139; bh=ubOwK9P+m0UviFdy3taP16rDzYZVyNKfOUV7wW5QmG4=; h=Cc:Date:From:Reply-To:Subject:To; b=J5cZQVPDA6mC76vjFMLdepDNuD6gyDqmDCoT3fFRVlU9tTyjM1iCCM44i0fWlKQAA27 EPb7L4dV+Tyryfb+YhcbGWicRU9cs3E9xkpvdGGkOd7WqpTcIY8Uh/WvBziU06WDmbWn/ waLYuj3qUb9eSq6EMjYg6n1XJe2BCKtpz+E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678062142342100002 Content-Type: text/plain; charset="utf-8" Adds ARM implementation of the EFIAPI to UNIX ABI gasket. Adds ARM implementation of SecCore stack switch and invocation. Adds ARM compiler flags. Cc: Andrew Fish Cc: Ray Ni Cc: Michael D Kinney Cc: Chasel Chiu Signed-off-by: Nate DeSimone Tested-by: Ard Biesheuvel --- EmulatorPkg/EmulatorPkg.dsc | 5 + EmulatorPkg/Unix/Host/Arm/Gasket.c | 895 ++++++++++++++ .../Unix/Host/Arm/GasketFunctionDefinitions.h | 1092 +++++++++++++++++ EmulatorPkg/Unix/Host/Arm/SwitchStack.S | 39 + EmulatorPkg/Unix/Host/Host.inf | 12 +- 5 files changed, 2042 insertions(+), 1 deletion(-) create mode 100644 EmulatorPkg/Unix/Host/Arm/Gasket.c create mode 100644 EmulatorPkg/Unix/Host/Arm/GasketFunctionDefinitions.h create mode 100644 EmulatorPkg/Unix/Host/Arm/SwitchStack.S diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc index 19ba60aa23..62d853e470 100644 --- a/EmulatorPkg/EmulatorPkg.dsc +++ b/EmulatorPkg/EmulatorPkg.dsc @@ -313,6 +313,11 @@ ## EmulatorPkg/Unix/Host/Host.inf !endif +!elseif "ARM" in $(ARCH) && "MSFT" not in $(FAMILY) && $(WIN_HOST_BUILD) = =3D=3D FALSE + ## + # Emulator, OS POSIX application + ## + EmulatorPkg/Unix/Host/Host.inf !endif =20 !ifndef $(SKIP_MAIN_BUILD) diff --git a/EmulatorPkg/Unix/Host/Arm/Gasket.c b/EmulatorPkg/Unix/Host/Arm= /Gasket.c new file mode 100644 index 0000000000..818025df58 --- /dev/null +++ b/EmulatorPkg/Unix/Host/Arm/Gasket.c @@ -0,0 +1,895 @@ +/**@file Gasket.c + + Manages any differences between the UNIX ABI and the EFI/Windows ABI + For ARM systems the AAPCS + (https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst) + has mostly standardized the ABI across different operating systems. Ther= e are + some differences in argument passing for variadic functions and passing = of + enum values as arguments. Neither of these cases apply for + the EMU_THUNK_PROTOCOL so we can use a simple wrapper functions. + +Copyright (c) 2004 - 2023, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "GasketFunctionDefinitions.h" + +// +// Gasket functions for the top-level EMU_THUNK_PROTOCOL +// + +UINTN +EFIAPI +GasketSecWriteStdErr ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + return SecWriteStdErr (Buffer, NumberOfBytes); +} + +EFI_STATUS +EFIAPI +GasketSecConfigStdIn ( + VOID + ) +{ + return SecConfigStdIn (); +} + +UINTN +EFIAPI +GasketSecWriteStdOut ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + return SecWriteStdOut (Buffer, NumberOfBytes); +} + +UINTN +EFIAPI +GasketSecReadStdIn ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + return SecReadStdIn (Buffer, NumberOfBytes); +} + +BOOLEAN +EFIAPI +GasketSecPollStdIn ( + VOID + ) +{ + return SecPollStdIn (); +} + +VOID * +EFIAPI +GasketSecMalloc ( + IN UINTN Size + ) +{ + return SecMalloc (Size); +} + +VOID * +EFIAPI +GasketSecValloc ( + IN UINTN Size + ) +{ + return SecValloc (Size); +} + +BOOLEAN +EFIAPI +GasketSecFree ( + IN VOID *Ptr + ) +{ + return SecFree (Ptr); +} + +RETURN_STATUS +EFIAPI +GasketSecPeCoffGetEntryPoint ( + IN VOID *Pe32Data, + IN OUT VOID **EntryPoint + ) +{ + return SecPeCoffGetEntryPoint (Pe32Data, EntryPoint); +} + +VOID +EFIAPI +GasketSecPeCoffRelocateImageExtraAction ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ) +{ + SecPeCoffRelocateImageExtraAction (ImageContext); +} + +VOID +EFIAPI +GasketSecPeCoffUnloadImageExtraAction ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ) +{ + SecPeCoffUnloadImageExtraAction (ImageContext); +} + +VOID +EFIAPI +GasketSecEnableInterrupt ( + VOID + ) +{ + SecEnableInterrupt (); +} + +VOID +EFIAPI +GasketSecDisableInterrupt ( + VOID + ) +{ + SecDisableInterrupt (); +} + +UINT64 +EFIAPI +GasketQueryPerformanceFrequency ( + VOID + ) +{ + return QueryPerformanceFrequency (); +} + +UINT64 +EFIAPI +GasketQueryPerformanceCounter ( + VOID + ) +{ + return QueryPerformanceCounter (); +} + +VOID +EFIAPI +GasketSecSleep ( + IN UINT64 Nanoseconds + ) +{ + SecSleep (Nanoseconds); +} + +VOID +EFIAPI +GasketSecCpuSleep ( + VOID + ) +{ + SecCpuSleep (); +} + +VOID +EFIAPI +GasketSecExit ( + UINTN Status + ) +{ + SecExit (Status); +} + +VOID +EFIAPI +GasketSecGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL + ) +{ + SecGetTime (Time, Capabilities); +} + +VOID +EFIAPI +GasketSecSetTime ( + IN EFI_TIME *Time + ) +{ + SecSetTime (Time); +} + +VOID +EFIAPI +GasketSecSetTimer ( + IN UINT64 PeriodMs, + IN EMU_SET_TIMER_CALLBACK CallBack + ) +{ + SecSetTimer (PeriodMs, CallBack); +} + +EFI_STATUS +EFIAPI +GasketSecGetNextProtocol ( + IN BOOLEAN EmuBusDriver, + OUT EMU_IO_THUNK_PROTOCOL **Instance OPTIONAL + ) +{ + return SecGetNextProtocol (EmuBusDriver, Instance); +} + +// +// Gasket functions for PPIs produced by SEC +// + +EFI_STATUS +EFIAPI +GasketSecUnixPeiAutoScan ( + IN UINTN Index, + OUT EFI_PHYSICAL_ADDRESS *MemoryBase, + OUT UINT64 *MemorySize + ) +{ + return SecUnixPeiAutoScan (Index, MemoryBase, MemorySize); +} + +EFI_STATUS +EFIAPI +GasketSecUnixFdAddress ( + IN UINTN Index, + IN OUT EFI_PHYSICAL_ADDRESS *FdBase, + IN OUT UINT64 *FdSize, + IN OUT EFI_PHYSICAL_ADDRESS *FixUp + ) +{ + return SecUnixFdAddress (Index, FdBase, FdSize, FixUp); +} + +VOID * +EFIAPI +GasketSecEmuThunkAddress ( + VOID + ) +{ + return SecEmuThunkAddress (); +} + +// +// Reverse (UNIX to EFIAPI) gaskets +// + +UINTN +ReverseGasketUint64 ( + UINTN CallBack, + UINT64 a + ) +{ + CALL_BACK Function; + + Function =3D (CALL_BACK)(VOID *) CallBack; + Function (a); + return CallBack; +} + +UINTN +ReverseGasketUint64Uint64 ( + VOID *CallBack, + VOID *Context, + VOID *Key + ) +{ + CALL_BACK_2ARG Function; + + Function =3D (CALL_BACK_2ARG) CallBack; + Function (Context, Key); + return (UINTN) CallBack; +} + +// +// Gasket functions for EMU_GRAPHICS_WINDOW_PROTOCOL +// + +EFI_STATUS +EFIAPI +GasketX11Size ( + EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo, + UINT32 Width, + UINT32 Height + ) +{ + return X11Size (GraphicsWindowsIo, Width, Height); +} + +EFI_STATUS +EFIAPI +GasketX11CheckKey ( + EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo + ) +{ + return X11CheckKey (GraphicsWindowsIo); +} + +EFI_STATUS +EFIAPI +GasketX11GetKey ( + EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo, + EFI_KEY_DATA *key + ) +{ + return X11GetKey (GraphicsWindowsIo, key); +} + +EFI_STATUS +EFIAPI +GasketX11KeySetState ( + EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo, + EFI_KEY_TOGGLE_STATE *KeyToggleState + ) +{ + return X11KeySetState (GraphicsWindowsIo, KeyToggleState); +} + +EFI_STATUS +EFIAPI +GasketX11RegisterKeyNotify ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo, + IN EMU_GRAPHICS_WINDOW_REGISTER_KEY_NOTIFY_CALLBACK MakeCallBack, + IN EMU_GRAPHICS_WINDOW_REGISTER_KEY_NOTIFY_CALLBACK BreakCallBack, + IN VOID *Context + ) +{ + return X11RegisterKeyNotify (GraphicsWindowsIo, MakeCallBack, BreakCallB= ack, Context); +} + +EFI_STATUS +EFIAPI +GasketX11Blt ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindows, + IN EFI_UGA_PIXEL *BltBuffer OPTIONAL, + IN EFI_UGA_BLT_OPERATION BltOperation, + IN EMU_GRAPHICS_WINDOWS__BLT_ARGS *Args + ) +{ + return X11Blt (GraphicsWindows, BltBuffer, BltOperation, Args); +} + +EFI_STATUS +EFIAPI +GasketX11CheckPointer ( + EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo + ) +{ + return X11CheckPointer (GraphicsWindowsIo); +} + +EFI_STATUS +EFIAPI +GasketX11GetPointerState ( + EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsWindowsIo, + EFI_SIMPLE_POINTER_STATE *state + ) +{ + return X11GetPointerState (GraphicsWindowsIo, state); +} + +EFI_STATUS +EFIAPI +GasketX11GraphicsWindowOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return X11GraphicsWindowOpen (This); +} + +EFI_STATUS +EFIAPI +GasketX11GraphicsWindowClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return X11GraphicsWindowClose (This); +} + +// +// Gasket functions for accessing Pthreads +// + +UINTN +EFIAPI +GasketPthreadMutexLock ( + IN VOID *Mutex + ) +{ + return PthreadMutexLock (Mutex); +} + +UINTN +EFIAPI +GasketPthreadMutexUnLock ( + IN VOID *Mutex + ) +{ + return PthreadMutexUnLock (Mutex); +} + +UINTN +EFIAPI +GasketPthreadMutexTryLock ( + IN VOID *Mutex + ) +{ + return PthreadMutexTryLock (Mutex); +} + +VOID * +EFIAPI +GasketPthreadMutexInit ( + IN VOID + ) +{ + return PthreadMutexInit (); +} + +UINTN +EFIAPI +GasketPthreadMutexDestroy ( + IN VOID *Mutex + ) +{ + return PthreadMutexDestroy (Mutex); +} + +UINTN +EFIAPI +GasketPthreadCreate ( + IN VOID *Thread, + IN VOID *Attribute, + IN THREAD_THUNK_THREAD_ENTRY Start, + IN VOID *Context + ) +{ + return PthreadCreate (Thread, Attribute, Start, Context); +} + +VOID +EFIAPI +GasketPthreadExit ( + IN VOID *ValuePtr + ) +{ + PthreadExit (ValuePtr); +} + +UINTN +EFIAPI +GasketPthreadSelf ( + VOID + ) +{ + return PthreadSelf (); +} + +EFI_STATUS +EFIAPI +GasketPthreadOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return PthreadOpen (This); +} + +EFI_STATUS +EFIAPI +GasketPthreadClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return PthreadClose (This); +} + +// +// Gasket functions for accessing the host filesystem +// + +EFI_STATUS +EFIAPI +GasketPosixOpenVolume ( + IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **Root + ) +{ + return PosixOpenVolume (This, Root); +} + +EFI_STATUS +EFIAPI +GasketPosixFileOpen ( + IN EFI_FILE_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **NewHandle, + IN CHAR16 *FileName, + IN UINT64 OpenMode, + IN UINT64 Attributes + ) +{ + return PosixFileOpen (This, NewHandle, FileName, OpenMode, Attributes); +} + +EFI_STATUS +EFIAPI +GasketPosixFileClose ( + IN EFI_FILE_PROTOCOL *This + ) +{ + return PosixFileClose (This); +} + +EFI_STATUS +EFIAPI +GasketPosixFileDelete ( + IN EFI_FILE_PROTOCOL *This + ) +{ + return PosixFileDelete (This); +} + +EFI_STATUS +EFIAPI +GasketPosixFileRead ( + IN EFI_FILE_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + return PosixFileRead (This, BufferSize, Buffer); +} + +EFI_STATUS +EFIAPI +GasketPosixFileWrite ( + IN EFI_FILE_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ) +{ + return PosixFileWrite (This, BufferSize, Buffer); +} + +EFI_STATUS +EFIAPI +GasketPosixFileSetPosition ( + IN EFI_FILE_PROTOCOL *This, + IN UINT64 Position + ) +{ + return PosixFileSetPosition (This, Position); +} + +EFI_STATUS +EFIAPI +GasketPosixFileGetPosition ( + IN EFI_FILE_PROTOCOL *This, + OUT UINT64 *Position + ) +{ + return PosixFileGetPosition (This, Position); +} + +EFI_STATUS +EFIAPI +GasketPosixFileGetInfo ( + IN EFI_FILE_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + return PosixFileGetInfo (This, InformationType, BufferSize, Buffer); +} + +EFI_STATUS +EFIAPI +GasketPosixFileSetInfo ( + IN EFI_FILE_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + return PosixFileSetInfo (This, InformationType, BufferSize, Buffer); +} + +EFI_STATUS +EFIAPI +GasketPosixFileFlush ( + IN EFI_FILE_PROTOCOL *This + ) +{ + return PosixFileFlush (This); +} + +EFI_STATUS +EFIAPI +GasketPosixFileSystemThunkOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return PosixFileSystemThunkOpen (This); +} + +EFI_STATUS +EFIAPI +GasketPosixFileSystemThunkClose (//@todo + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return PosixFileSystemThunkClose (This); +} + +// +// Gasket functions for reading/writing to disk images +// + +EFI_STATUS +EFIAPI +GasketEmuBlockIoReset ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + return EmuBlockIoReset (This, ExtendedVerification); +} + +EFI_STATUS +EFIAPI +GasketEmuBlockIoReadBlocks ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO2_TOKEN *Token, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + return EmuBlockIoReadBlocks (This, MediaId, LBA, Token, BufferSize, Buff= er); +} + +EFI_STATUS +EFIAPI +GasketEmuBlockIoWriteBlocks ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO2_TOKEN *Token, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + return EmuBlockIoWriteBlocks (This, MediaId, LBA, Token, BufferSize, Buf= fer); +} + +EFI_STATUS +EFIAPI +GasketEmuBlockIoFlushBlocks ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN OUT EFI_BLOCK_IO2_TOKEN *Token + ) +{ + return EmuBlockIoFlushBlocks (This, Token); +} + +EFI_STATUS +EFIAPI +GasketEmuBlockIoCreateMapping ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN EFI_BLOCK_IO_MEDIA *Media + ) +{ + return EmuBlockIoCreateMapping (This, Media); +} + +EFI_STATUS +EFIAPI +GasketBlockIoThunkOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return EmuBlockIoThunkOpen (This); +} + +EFI_STATUS +EFIAPI +GasketBlockIoThunkClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return EmuBlockIoThunkClose (This); +} + +// +// Gasket functions for accessing BSD Sockets (TCP-IP Networks) +// + +EFI_STATUS +EFIAPI +GasketSnpCreateMapping ( + IN EMU_SNP_PROTOCOL *This, + IN EFI_SIMPLE_NETWORK_MODE *Media + ) +{ + return EmuSnpCreateMapping (This, Media); +} + +EFI_STATUS +EFIAPI +GasketSnpStart ( + IN EMU_SNP_PROTOCOL *This + ) +{ + return EmuSnpStart (This); +} + +EFI_STATUS +EFIAPI +GasketSnpStop ( + IN EMU_SNP_PROTOCOL *This + ) +{ + return EmuSnpStop (This); +} + +EFI_STATUS +EFIAPI +GasketSnpInitialize ( + IN EMU_SNP_PROTOCOL *This, + IN UINTN ExtraRxBufferSize OPTIONAL, + IN UINTN ExtraTxBufferSize OPTIONAL + ) +{ + return EmuSnpInitialize (This, ExtraRxBufferSize, ExtraTxBufferSize); +} + +EFI_STATUS +EFIAPI +GasketSnpReset ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + return EmuSnpReset (This, ExtendedVerification); +} + +EFI_STATUS +EFIAPI +GasketSnpShutdown ( + IN EMU_SNP_PROTOCOL *This + ) +{ + return EmuSnpShutdown (This); +} + +EFI_STATUS +EFIAPI +GasketSnpReceiveFilters ( + IN EMU_SNP_PROTOCOL *This, + IN UINT32 Enable, + IN UINT32 Disable, + IN BOOLEAN ResetMCastFilter, + IN UINTN MCastFilterCnt OPTIONAL, + IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL + ) +{ + return EmuSnpReceiveFilters (This, Enable, Disable, ResetMCastFilter, MC= astFilterCnt, MCastFilter); +} + +EFI_STATUS +EFIAPI +GasketSnpStationAddress ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN Reset, + IN EFI_MAC_ADDRESS *New OPTIONAL + ) +{ + return EmuSnpStationAddress (This, Reset, New); +} + +EFI_STATUS +EFIAPI +GasketSnpStatistics ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN Reset, + IN OUT UINTN *StatisticsSize OPTIONAL, + OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL + ) +{ + return EmuSnpStatistics (This, Reset, StatisticsSize, StatisticsTable); +} + +EFI_STATUS +EFIAPI +GasketSnpMCastIpToMac ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN IPv6, + IN EFI_IP_ADDRESS *IP, + OUT EFI_MAC_ADDRESS *MAC + ) +{ + return EmuSnpMCastIpToMac (This, IPv6, IP, MAC); +} + +EFI_STATUS +EFIAPI +GasketSnpNvData ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN ReadWrite, + IN UINTN Offset, + IN UINTN BufferSize, + IN OUT VOID *Buffer + ) +{ + return EmuSnpNvData (This, ReadWrite, Offset, BufferSize, Buffer); +} + +EFI_STATUS +EFIAPI +GasketSnpGetStatus ( + IN EMU_SNP_PROTOCOL *This, + OUT UINT32 *InterruptStatus OPTIONAL, + OUT VOID **TxBuf OPTIONAL + ) +{ + return EmuSnpGetStatus (This, InterruptStatus, TxBuf); +} + +EFI_STATUS +EFIAPI +GasketSnpTransmit ( + IN EMU_SNP_PROTOCOL *This, + IN UINTN HeaderSize, + IN UINTN BufferSize, + IN VOID *Buffer, + IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + IN EFI_MAC_ADDRESS *DestAddr OPTIONAL, + IN UINT16 *Protocol OPTIONAL + ) +{ + return EmuSnpTransmit (This, HeaderSize, BufferSize, Buffer, SrcAddr, De= stAddr, Protocol); +} + +EFI_STATUS +EFIAPI +GasketSnpReceive ( + IN EMU_SNP_PROTOCOL *This, + OUT UINTN *HeaderSize OPTIONAL, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + OUT EFI_MAC_ADDRESS *DestAddr OPTIONAL, + OUT UINT16 *Protocol OPTIONAL + ) +{ + return EmuSnpReceive (This, HeaderSize, BufferSize, Buffer, SrcAddr, Des= tAddr, Protocol); +} + +EFI_STATUS +EFIAPI +GasketSnpThunkOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return EmuSnpThunkOpen (This); +} + +EFI_STATUS +EFIAPI +GasketSnpThunkClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return EmuSnpThunkClose (This); +} diff --git a/EmulatorPkg/Unix/Host/Arm/GasketFunctionDefinitions.h b/Emulat= orPkg/Unix/Host/Arm/GasketFunctionDefinitions.h new file mode 100644 index 0000000000..ab71dac9ec --- /dev/null +++ b/EmulatorPkg/Unix/Host/Arm/GasketFunctionDefinitions.h @@ -0,0 +1,1092 @@ +/**@file GasketFunctionDefitions.h + + This header file contains function definitions for the UNIX side of the = ABI. + The Gaskets call these functions to allow UNIX APIs to be accessed from + within the PEI and DXE environments. + +Copyright (c) 2004 - 2023, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Functions for the top-level EMU_THUNK_PROTOCOL +// + +#ifndef _GASKET_FUNCTION_DEFINITIONS_H_ +#define _GASKET_FUNCTION_DEFINITIONS_H_ + +#include +#include +#include +#include +#include +#include +#include +#include "Gasket.h" + +UINTN +SecWriteStdErr ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ); + +EFI_STATUS +SecConfigStdIn ( + VOID + ); + +UINTN +SecWriteStdOut ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ); + +UINTN +SecReadStdIn ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ); + +BOOLEAN +SecPollStdIn ( + VOID + ); + +VOID * +SecMalloc ( + IN UINTN Size + ); + +VOID * +SecValloc ( + IN UINTN Size + ); + +BOOLEAN +SecFree ( + IN VOID *Ptr + ); + +RETURN_STATUS +EFIAPI +SecPeCoffGetEntryPoint ( + IN VOID *Pe32Data, + IN OUT VOID **EntryPoint + ); + +VOID +EFIAPI +SecPeCoffRelocateImageExtraAction ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + +VOID +SecEnableInterrupt ( + VOID + ); + +VOID +SecDisableInterrupt ( + VOID + ); + +UINT64 +QueryPerformanceFrequency ( + VOID + ); + +UINT64 +QueryPerformanceCounter ( + VOID + ); + +VOID +SecSleep ( + IN UINT64 Nanoseconds + ); + +VOID +SecCpuSleep ( + VOID + ); + +VOID +SecExit ( + UINTN Status + ); + +VOID +SecGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL + ); + +VOID +SecSetTime ( + IN EFI_TIME *Time + ); + +VOID +SecSetTimer ( + IN UINT64 PeriodMs, + IN EMU_SET_TIMER_CALLBACK CallBack + ); + +EFI_STATUS +SecGetNextProtocol ( + IN BOOLEAN EmuBusDriver, + OUT EMU_IO_THUNK_PROTOCOL **Instance OPTIONAL + ); + +VOID +EFIAPI +SecPeCoffUnloadImageExtraAction ( + IN PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + +// +// Functions for PPIs produced by SEC +// + +EFI_STATUS +SecUnixPeiAutoScan ( + IN UINTN Index, + OUT EFI_PHYSICAL_ADDRESS *MemoryBase, + OUT UINT64 *MemorySize + ); + +EFI_STATUS +SecUnixFdAddress ( + IN UINTN Index, + IN OUT EFI_PHYSICAL_ADDRESS *FdBase, + IN OUT UINT64 *FdSize, + IN OUT EFI_PHYSICAL_ADDRESS *FixUp + ); + +/** + Since the SEC is the only Unix program in stack it must export + an interface to do POSIX calls. gEmuThunkProtocol is initialized in EmuT= hunk.c + + @retval Address of the gEmuThunkProtocol global + +**/ +VOID * +SecEmuThunkAddress ( + VOID + ); + +// +// Reverse (UNIX to EFIAPI) gaskets +// + +typedef +VOID +(EFIAPI *CALL_BACK_2ARG) ( + IN VOID *Context, + IN VOID *Key + ); + +// +// Functions for accessing libX11 +// + +EFI_STATUS +X11Size ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo, + IN UINT32 Width, + IN UINT32 Height + ); + +EFI_STATUS +X11CheckKey ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo + ); + +EFI_STATUS +X11GetKey ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo, + IN EFI_KEY_DATA *KeyData + ); + +EFI_STATUS +X11KeySetState ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo, + IN EFI_KEY_TOGGLE_STATE *KeyToggleState + ); + +EFI_STATUS +X11RegisterKeyNotify ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo, + IN EMU_GRAPHICS_WINDOW_REGISTER_KEY_NOTIFY_CALLBACK MakeCallBack, + IN EMU_GRAPHICS_WINDOW_REGISTER_KEY_NOTIFY_CALLBACK BreakCallBack, + IN VOID *Context + ); + +EFI_STATUS +X11Blt ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo, + IN EFI_UGA_PIXEL *BltBuffer OPTIONAL, + IN EFI_UGA_BLT_OPERATION BltOperation, + IN EMU_GRAPHICS_WINDOWS__BLT_ARGS *Args + ); + +EFI_STATUS +X11CheckPointer ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo + ); + +EFI_STATUS +X11GetPointerState ( + IN EMU_GRAPHICS_WINDOW_PROTOCOL *GraphicsIo, + IN EFI_SIMPLE_POINTER_STATE *State + ); + +EFI_STATUS +X11GraphicsWindowOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +EFI_STATUS +X11GraphicsWindowClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +// +// Functions for accessing Pthreads +// + +UINTN +EFIAPI +PthreadMutexLock ( + IN VOID *Mutex + ); + +UINTN +EFIAPI +PthreadMutexUnLock ( + IN VOID *Mutex + ); + +UINTN +EFIAPI +PthreadMutexTryLock ( + IN VOID *Mutex + ); + +VOID * +PthreadMutexInit ( + IN VOID + ); + +UINTN +PthreadMutexDestroy ( + IN VOID *Mutex + ); + +UINTN +PthreadCreate ( + IN VOID *Thread, + IN VOID *Attribute, + IN THREAD_THUNK_THREAD_ENTRY Start, + IN VOID *Context + ); + +VOID +PthreadExit ( + IN VOID *ValuePtr + ); + +UINTN +PthreadSelf ( + VOID + ); + +EFI_STATUS +PthreadOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +EFI_STATUS +PthreadClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +// +// Functions for accessing the host filesystem +// + +/** + Open the root directory on a volume. + + @param This Protocol instance pointer. + @param Root Returns an Open file handle for the root directory + + @retval EFI_SUCCESS The device was opened. + @retval EFI_UNSUPPORTED This volume does not support the file syste= m. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_ACCESS_DENIED The service denied access to the file. + @retval EFI_OUT_OF_RESOURCES The volume was not opened due to lack of re= sources. + +**/ +EFI_STATUS +PosixOpenVolume ( + IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **Root + ); + +/** + Opens a new file relative to the source file's location. + + @param This The protocol instance pointer. + @param NewHandle Returns File Handle for FileName. + @param FileName Null terminated string. "\", ".", and ".." are suppor= ted. + @param OpenMode Open mode for file. + @param Attributes Only used for EFI_FILE_MODE_CREATE. + + @retval EFI_SUCCESS The device was opened. + @retval EFI_NOT_FOUND The specified file could not be found on th= e device. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_MEDIA_CHANGED The media has changed. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_ACCESS_DENIED The service denied access to the file. + @retval EFI_OUT_OF_RESOURCES The volume was not opened due to lack of re= sources. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +EFI_STATUS +PosixFileOpen ( + IN EFI_FILE_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **NewHandle, + IN CHAR16 *FileName, + IN UINT64 OpenMode, + IN UINT64 Attributes + ); + +/** + Close the file handle + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The device was opened. + +**/ +EFI_STATUS +PosixFileClose ( + IN EFI_FILE_PROTOCOL *This + ); + +/** + Close and delete the file handle. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The device was opened. + @retval EFI_WARN_DELETE_FAILURE The handle was closed but the file was = not deleted. + +**/ +EFI_STATUS +PosixFileDelete ( + IN EFI_FILE_PROTOCOL *This + ); + +/** + Read data from the file. + + @param This Protocol instance pointer. + @param BufferSize On input size of buffer, on output amount of data in = buffer. + @param Buffer The buffer in which data is read. + + @retval EFI_SUCCESS Data was read. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_BUFFER_TO_SMALL BufferSize is too small. BufferSize contain= s required size. + +**/ +EFI_STATUS +PosixFileRead ( + IN EFI_FILE_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Write data to a file. + + @param This Protocol instance pointer. + @param BufferSize On input size of buffer, on output amount of data in = buffer. + @param Buffer The buffer in which data to write. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Writes to Open directory are not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_DEVICE_ERROR An attempt was made to write to a deleted f= ile. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write protected. + @retval EFI_ACCESS_DENIED The file was open for read only. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +EFI_STATUS +PosixFileWrite ( + IN EFI_FILE_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Set a files current position + + @param This Protocol instance pointer. + @param Position Byte position from the start of the file. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Seek request for non-zero is not valid on open. + +**/ +EFI_STATUS +PosixFileSetPosition ( + IN EFI_FILE_PROTOCOL *This, + IN UINT64 Position + ); + +/** + Get a file's current position + + @param This Protocol instance pointer. + @param Position Byte position from the start of the file. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Seek request for non-zero is not valid on open.. + +**/ +EFI_STATUS +PosixFileGetPosition ( + IN EFI_FILE_PROTOCOL *This, + OUT UINT64 *Position + ); + +/** + Get information about a file. + + @param This Protocol instance pointer. + @param InformationType Type of information to return in Buffer. + @param BufferSize On input size of buffer, on output amount of dat= a in buffer. + @param Buffer The buffer to return data. + + @retval EFI_SUCCESS Data was returned. + @retval EFI_UNSUPPORTED InformationType is not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write protected. + @retval EFI_ACCESS_DENIED The file was open for read only. + @retval EFI_BUFFER_TOO_SMALL Buffer was too small; required size returne= d in BufferSize. + +**/ +EFI_STATUS +PosixFileGetInfo ( + IN EFI_FILE_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Set information about a file + + @param File Protocol instance pointer. + @param InformationType Type of information in Buffer. + @param BufferSize Size of buffer. + @param Buffer The data to write. + + @retval EFI_SUCCESS Data was returned. + @retval EFI_UNSUPPORTED InformationType is not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write protected. + @retval EFI_ACCESS_DENIED The file was open for read only. + +**/ +EFI_STATUS +PosixFileSetInfo ( + IN EFI_FILE_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flush data back for the file handle. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Writes to Open directory are not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write protected. + @retval EFI_ACCESS_DENIED The file was open for read only. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +EFI_STATUS +PosixFileFlush ( + IN EFI_FILE_PROTOCOL *This + ); + +EFI_STATUS +PosixFileSystemThunkOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +EFI_STATUS +PosixFileSystemThunkClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +// +// Functions for reading/writing to disk images +// + +EFI_STATUS +EmuBlockIoReset ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Read BufferSize bytes from Lba into Buffer. + + This function reads the requested number of blocks from the device. All = the + blocks are read, or an error is returned. + If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_or EFI_MEDIA_CHANGED is returned and + non-blocking I/O is being used, the Event associated with this request w= ill + not be signaled. + + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId Id of the media, changes every time the medi= a is + replaced. + @param[in] Lba The starting Logical Block Address to read f= rom. + @param[in, out] Token A pointer to the token associated with the t= ransaction. + @param[in] BufferSize Size of Buffer, must be a multiple of device= block size. + @param[out] Buffer A pointer to the destination buffer for the = data. The + caller is responsible for either having impl= icit or + explicit ownership of the buffer. + + @retval EFI_SUCCESS The read request was queued if Token->Even= t is + not NULL.The data was read correctly from = the + device if the Token->Event is NULL. + @retval EFI_DEVICE_ERROR The device reported an error while perform= ing + the read. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple= of the + intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are no= t valid, + or the buffer is not on proper alignment. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack + of resources. +**/ +EFI_STATUS +EmuBlockIoReadBlocks ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO2_TOKEN *Token, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Write BufferSize bytes from Lba into Buffer. + + This function writes the requested number of blocks to the device. All b= locks + are written, or an error is returned.If EFI_DEVICE_ERROR, EFI_NO_MEDIA, + EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED is returned and non-blocking I/= O is + being used, the Event associated with this request will not be signaled. + + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId The media ID that the write request is for. + @param[in] Lba The starting logical block address to be wri= tten. The + caller is responsible for writing to only le= gitimate + locations. + @param[in, out] Token A pointer to the token associated with the t= ransaction. + @param[in] BufferSize Size of Buffer, must be a multiple of device= block size. + @param[in] Buffer A pointer to the source buffer for the data. + + @retval EFI_SUCCESS The write request was queued if Event is n= ot NULL. + The data was written correctly to the devi= ce if + the Event is NULL. + @retval EFI_WRITE_PROTECTED The device can not be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId does not match the current dev= ice. + @retval EFI_DEVICE_ERROR The device reported an error while perform= ing the write. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block= size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are n= ot valid, + or the buffer is not on proper alignment. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack + of resources. + +**/ +EFI_STATUS +EmuBlockIoWriteBlocks ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO2_TOKEN *Token, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flush the Block Device. + + If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_EFI_WRITE_PROTECTED or EFI_MEDIA_CHAN= GED + is returned and non-blocking I/O is being used, the Event associated with + this request will not be signaled. + + @param[in] This Indicates a pointer to the calling context. + @param[in,out] Token A pointer to the token associated with the tran= saction + + @retval EFI_SUCCESS The flush request was queued if Event is no= t NULL. + All outstanding data was written correctly = to the + device if the Event is NULL. + @retval EFI_DEVICE_ERROR The device reported an error while writing = back + the data. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a= lack + of resources. + +**/ +EFI_STATUS +EmuBlockIoFlushBlocks ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN OUT EFI_BLOCK_IO2_TOKEN *Token + ); + +EFI_STATUS +EmuBlockIoCreateMapping ( + IN EMU_BLOCK_IO_PROTOCOL *This, + IN EFI_BLOCK_IO_MEDIA *Media + ); + +EFI_STATUS +EmuBlockIoThunkOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +EFI_STATUS +EmuBlockIoThunkClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +// +// Functions for accessing BSD Sockets (TCP-IP Networks) +// + +/** + Register storage for SNP Mode. + + @param This Protocol instance pointer. + @param Mode SimpleNetworkProtocol Mode structure passed into driver. + + @retval EFI_SUCCESS The network interface was started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + +**/ +EFI_STATUS +EmuSnpCreateMapping ( + IN EMU_SNP_PROTOCOL *This, + IN EFI_SIMPLE_NETWORK_MODE *Mode + ); + +/** + Changes the state of a network interface from "stopped" to "started". + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The network interface was started. + @retval EFI_ALREADY_STARTED The network interface is already in the st= arted state. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpStart ( + IN EMU_SNP_PROTOCOL *This + ); + +/** + Changes the state of a network interface from "started" to "stopped". + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The network interface was stopped. + @retval EFI_ALREADY_STARTED The network interface is already in the st= opped state. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpStop ( + IN EMU_SNP_PROTOCOL *This + ); + +/** + Resets a network adapter and allocates the transmit and receive buffers + required by the network interface; optionally, also requests allocation + of additional transmit and receive buffers. + + @param This The protocol instance pointer. + @param ExtraRxBufferSize The size, in bytes, of the extra receive buffe= r space + that the driver should allocate for the networ= k interface. + Some network interfaces will not be able to us= e the extra + buffer, and the caller will not know if it is = actually + being used. + @param ExtraTxBufferSize The size, in bytes, of the extra transmit buff= er space + that the driver should allocate for the networ= k interface. + Some network interfaces will not be able to us= e the extra + buffer, and the caller will not know if it is = actually + being used. + + @retval EFI_SUCCESS The network interface was initialized. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_OUT_OF_RESOURCES There was not enough memory for the transm= it and + receive buffers. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpInitialize ( + IN EMU_SNP_PROTOCOL *This, + IN UINTN ExtraRxBufferSize OPTIONAL, + IN UINTN ExtraTxBufferSize OPTIONAL + ); + +/** + Resets a network adapter and re-initializes it with the parameters that = were + provided in the previous call to Initialize(). + + @param This The protocol instance pointer. + @param ExtendedVerification Indicates that the driver may perform a more + exhaustive verification operation of the de= vice + during reset. + + @retval EFI_SUCCESS The network interface was reset. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpReset ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Resets a network adapter and leaves it in a state that is safe for + another driver to initialize. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The network interface was shutdown. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpShutdown ( + IN EMU_SNP_PROTOCOL *This + ); + +/** + Manages the multicast receive filters of a network interface. + + @param This The protocol instance pointer. + @param Enable A bit mask of receive filters to enable on the = network interface. + @param Disable A bit mask of receive filters to disable on the= network interface. + @param ResetMCastFilter Set to TRUE to reset the contents of the multic= ast receive + filters on the network interface to their defau= lt values. + @param McastFilterCnt Number of multicast HW MAC addresses in the new + MCastFilter list. This value must be less than = or equal to + the MCastFilterCnt field of EMU_SNP_MODE. This + field is optional if ResetMCastFilter is TRUE. + @param MCastFilter A pointer to a list of new multicast receive fi= lter HW MAC + addresses. This list will replace any existing = multicast + HW MAC address list. This field is optional if + ResetMCastFilter is TRUE. + + @retval EFI_SUCCESS The multicast receive filter list was upda= ted. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpReceiveFilters ( + IN EMU_SNP_PROTOCOL *This, + IN UINT32 Enable, + IN UINT32 Disable, + IN BOOLEAN ResetMCastFilter, + IN UINTN MCastFilterCnt OPTIONAL, + IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL + ); + +/** + Modifies or resets the current station address, if supported. + + @param This The protocol instance pointer. + @param Reset Flag used to reset the station address to the network inte= rfaces + permanent address. + @param New The new station address to be used for the network interfa= ce. + + @retval EFI_SUCCESS The network interfaces station address was= updated. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpStationAddress ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN Reset, + IN EFI_MAC_ADDRESS *New OPTIONAL + ); + +/** + Resets or collects the statistics on a network interface. + + @param This Protocol instance pointer. + @param Reset Set to TRUE to reset the statistics for the netw= ork interface. + @param StatisticsSize On input the size, in bytes, of StatisticsTable.= On + output the size, in bytes, of the resulting tabl= e of + statistics. + @param StatisticsTable A pointer to the EFI_NETWORK_STATISTICS structur= e that + contains the statistics. + + @retval EFI_SUCCESS The statistics were collected from the net= work interface. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_BUFFER_TOO_SMALL The Statistics buffer was too small. The c= urrent buffer + size needed to hold the statistics is retu= rned in + StatisticsSize. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpStatistics ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN Reset, + IN OUT UINTN *StatisticsSize OPTIONAL, + OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL + ); + +/** + Converts a multicast IP address to a multicast HW MAC address. + + @param This The protocol instance pointer. + @param IPv6 Set to TRUE if the multicast IP address is IPv6 [RFC 2460].= Set + to FALSE if the multicast IP address is IPv4 [RFC 791]. + @param IP The multicast IP address that is to be converted to a multi= cast + HW MAC address. + @param MAC The multicast HW MAC address that is to be generated from I= P. + + @retval EFI_SUCCESS The multicast IP address was mapped to the= multicast + HW MAC address. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_BUFFER_TOO_SMALL The Statistics buffer was too small. The c= urrent buffer + size needed to hold the statistics is retu= rned in + StatisticsSize. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpMCastIpToMac ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN IPv6, + IN EFI_IP_ADDRESS *IP, + OUT EFI_MAC_ADDRESS *MAC + ); + +/** + Performs read and write operations on the NVRAM device attached to a + network interface. + + @param This The protocol instance pointer. + @param ReadWrite TRUE for read operations, FALSE for write operations. + @param Offset Byte offset in the NVRAM device at which to start the= read or + write operation. This must be a multiple of NvRamAcce= ssSize and + less than NvRamSize. + @param BufferSize The number of bytes to read or write from the NVRAM d= evice. + This must also be a multiple of NvramAccessSize. + @param Buffer A pointer to the data buffer. + + @retval EFI_SUCCESS The NVRAM access was performed. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpNvData ( + IN EMU_SNP_PROTOCOL *This, + IN BOOLEAN ReadWrite, + IN UINTN Offset, + IN UINTN BufferSize, + IN OUT VOID *Buffer + ); + +/** + Reads the current interrupt status and recycled transmit buffer status f= rom + a network interface. + + @param This The protocol instance pointer. + @param InterruptStatus A pointer to the bit mask of the currently activ= e interrupts + If this is NULL, the interrupt status will not b= e read from + the device. If this is not NULL, the interrupt s= tatus will + be read from the device. When the interrupt sta= tus is read, + it will also be cleared. Clearing the transmit = interrupt + does not empty the recycled transmit buffer arra= y. + @param TxBuf Recycled transmit buffer address. The network in= terface will + not transmit if its internal recycled transmit b= uffer array + is full. Reading the transmit buffer does not cl= ear the + transmit interrupt. If this is NULL, then the tr= ansmit buffer + status will not be read. If there are no transmi= t buffers to + recycle and TxBuf is not NULL, * TxBuf will be s= et to NULL. + + @retval EFI_SUCCESS The status of the network interface was re= trieved. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpGetStatus ( + IN EMU_SNP_PROTOCOL *This, + OUT UINT32 *InterruptStatus OPTIONAL, + OUT VOID **TxBuf OPTIONAL + ); + +/** + Places a packet in the transmit queue of a network interface. + + @param This The protocol instance pointer. + @param HeaderSize The size, in bytes, of the media header to be filled = in by + the Transmit() function. If HeaderSize is non-zero, t= hen it + must be equal to This->Mode->MediaHeaderSize and the = DestAddr + and Protocol parameters must not be NULL. + @param BufferSize The size, in bytes, of the entire packet (media heade= r and + data) to be transmitted through the network interface. + @param Buffer A pointer to the packet (media header followed by dat= a) to be + transmitted. This parameter cannot be NULL. If Header= Size is zero, + then the media header in Buffer must already be fille= d in by the + caller. If HeaderSize is non-zero, then the media hea= der will be + filled in by the Transmit() function. + @param SrcAddr The source HW MAC address. If HeaderSize is zero, the= n this parameter + is ignored. If HeaderSize is non-zero and SrcAddr is = NULL, then + This->Mode->CurrentAddress is used for the source HW = MAC address. + @param DestAddr The destination HW MAC address. If HeaderSize is zero= , then this + parameter is ignored. + @param Protocol The type of header to build. If HeaderSize is zero, t= hen this + parameter is ignored. See RFC 1700, section "Ether Ty= pes", for + examples. + + @retval EFI_SUCCESS The packet was placed on the transmit queu= e. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_NOT_READY The network interface is too busy to accep= t this transmit request. + @retval EFI_BUFFER_TOO_SMALL The BufferSize parameter is too small. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsup= ported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netwo= rk interface. + @retval EFI_UNSUPPORTED This function is not supported by the netw= ork interface. + +**/ +EFI_STATUS +EmuSnpTransmit ( + IN EMU_SNP_PROTOCOL *This, + IN UINTN HeaderSize, + IN UINTN BufferSize, + IN VOID *Buffer, + IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + IN EFI_MAC_ADDRESS *DestAddr OPTIONAL, + IN UINT16 *Protocol OPTIONAL + ); + +/** + Receives a packet from a network interface. + + @param This The protocol instance pointer. + @param HeaderSize The size, in bytes, of the media header received on t= he network + interface. If this parameter is NULL, then the media = header size + will not be returned. + @param BufferSize On entry, the size, in bytes, of Buffer. On exit, the= size, in + bytes, of the packet that was received on the network= interface. + @param Buffer A pointer to the data buffer to receive both the medi= a header and + the data. + @param SrcAddr The source HW MAC address. If this parameter is NULL,= the + HW MAC source address will not be extracted from the = media + header. + @param DestAddr The destination HW MAC address. If this parameter is = NULL, + the HW MAC destination address will not be extracted = from the + media header. + @param Protocol The media header type. If this parameter is NULL, the= n the + protocol will not be extracted from the media header.= See + RFC 1700 section "Ether Types" for examples. + + @retval EFI_SUCCESS The received data was stored in Buffer, a= nd BufferSize has + been updated to the number of bytes recei= ved. + @retval EFI_NOT_STARTED The network interface has not been starte= d. + @retval EFI_NOT_READY The network interface is too busy to acce= pt this transmit + request. + @retval EFI_BUFFER_TOO_SMALL The BufferSize parameter is too small. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsu= pported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the netw= ork interface. + @retval EFI_UNSUPPORTED This function is not supported by the net= work interface. + +**/ +EFI_STATUS +EmuSnpReceive ( + IN EMU_SNP_PROTOCOL *This, + OUT UINTN *HeaderSize OPTIONAL, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + OUT EFI_MAC_ADDRESS *DestAddr OPTIONAL, + OUT UINT16 *Protocol OPTIONAL + ); + +EFI_STATUS +EmuSnpThunkOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +EFI_STATUS +EmuSnpThunkClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ); + +#endif diff --git a/EmulatorPkg/Unix/Host/Arm/SwitchStack.S b/EmulatorPkg/Unix/Hos= t/Arm/SwitchStack.S new file mode 100644 index 0000000000..cb3dfcf5c0 --- /dev/null +++ b/EmulatorPkg/Unix/Host/Arm/SwitchStack.S @@ -0,0 +1,39 @@ +#-------------------------------------------------------------------------= ----- +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-------------------------------------------------------------------------= ----- + +#include + +#/** +# Routine for switching stacks with 2 parameters +# +# @param EntryPoint Entry point to be invoked after switching sta= ck +# @param Context1 Parameter1 for entry point. +# @param Context2 Parameter2 for entry point. +# @param NewStack The pointer to the new stack. +# +# @return None +# +#**/ +#VOID +#EFIAPI +#PeiSwitchStacks ( +# IN SWITCH_STACK_ENTRY_POINT EntryPoint, +# IN VOID *Context1 OPTIONAL, +# IN VOID *Context2 OPTIONAL, +# IN VOID *NewStack +# ) +# +ASM_FUNC(PeiSwitchStacks) + mov sp, r3 + push {r1} + push {r2} + push {r0} + pop {r3} + pop {r1} + pop {r0} + bx r3 diff --git a/EmulatorPkg/Unix/Host/Host.inf b/EmulatorPkg/Unix/Host/Host.inf index f5ebbed683..effd0a3217 100644 --- a/EmulatorPkg/Unix/Host/Host.inf +++ b/EmulatorPkg/Unix/Host/Host.inf @@ -2,7 +2,7 @@ # Entry Point of Emu Emulator # # Main executable file of Unix Emulator that loads PEI core after initiali= zation finished. -# Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -42,6 +42,10 @@ Ia32/Gasket.S # enforce 16-byte stack alignment for Mac OS X Ia32/SwitchStack.c =20 +[Sources.ARM] + Arm/Gasket.c + Arm/SwitchStack.S + CacheMaintenance.c =20 [Packages] MdePkg/MdePkg.dec @@ -49,6 +53,9 @@ NetworkPkg/NetworkPkg.dec EmulatorPkg/EmulatorPkg.dec =20 +[Packages.ARM] + ArmPkg/ArmPkg.dec + [LibraryClasses] DebugLib PcdLib @@ -127,6 +134,9 @@ GCC:*_*_X64_PP_FLAGS =3D=3D -m64 -E -x assembler-with-cpp -include $(DE= ST_DIR_DEBUG)/AutoGen.h GCC:*_*_X64_ASM_FLAGS =3D=3D -m64 -c -x assembler -imacros $(DEST_DIR_D= EBUG)/AutoGen.h =20 + GCC:*_*_ARM_DLINK_FLAGS =3D=3D -o $(BIN_DIR)/Host -mthumb -march=3Darmv= 7-a -mlittle-endian -mabi=3Daapcs -L/usr/X11R6/lib + GCC:*_*_ARM_CC_FLAGS =3D=3D -g -Os -fshort-wchar -fno-builtin -fno-stri= ct-aliasing -Wall -Werror -Wno-array-bounds -fno-common -march=3Darmv7-a -m= little-endian -mabi=3Daapcs -fno-short-enums -funsigned-char -fstack-protec= tor -Wno-unused-but-set-variable -Wno-unused-const-variable -mword-relocati= ons -flto -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-add= ress -mthumb -mfloat-abi=3Dhard -fno-pic -fno-pie -c -include $(DEST_DIR_DE= BUG)/AutoGen.h + GCC:*_*_*_DLINK2_FLAGS =3D=3D -lpthread -ldl -lXext -lX11 =20 # --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100709): https://edk2.groups.io/g/devel/message/100709 Mute This Topic: https://groups.io/mt/97414913/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 22:20:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100706+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100706+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678062134; cv=none; d=zohomail.com; s=zohoarc; b=a9Z0eaQVEj/O3OHG0Y41G/em5ODyVykMGMYg6iZbeLj8LHdyn806uE+hUGZr7OXteOreqeKs40sBsVERx7yVFuhbwSVsqyShKUQ1XCBiehuZsy9KTF4Xa8uilGpcNG7Twdql5fgmw7qB7C+8PRzRCWOWsIFI9f75oB+vrK3qI4Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678062134; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NWpRdzluZnONmJJ4RyLoTEfEFDETeTwghKN+Rwq1JYc=; b=CWfqWDwGwhl7uc7JmwM0OTkQIil5iTDjdfSTbixGnBszDfOexOKkJlP0w3x9xOMoKItvQydx3PKpg3hNEkAGEu0pmmmdB3DbxOZQzX0fTdXDLlYXt+t/Wwto2wblsZ8yegO/cWw3lvfrMuFVW6yMe87R9bqWVi83gEN2nJQvdHE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100706+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678062134743587.6072850992656; Sun, 5 Mar 2023 16:22:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id JHMlYY1788612xiWly9001WE; Sun, 05 Mar 2023 16:22:14 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.22191.1678062132259075315 for ; Sun, 05 Mar 2023 16:22:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="337758120" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="337758120" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="669263323" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="669263323" X-Received: from nldesimo-desk.amr.corp.intel.com ([10.24.12.177]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Andrew Fish , Ray Ni , Michael D Kinney , Chasel Chiu Subject: [edk2-devel] [PATCH v1 5/6] EmulatorPkg: Add ARM support to EmuSec Date: Sun, 5 Mar 2023 16:22:04 -0800 Message-Id: <20230306002205.1640-6-nathaniel.l.desimone@intel.com> In-Reply-To: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> References: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: bdyWuVPQwZ6B2HSlGoUu5qyXx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678062134; bh=04khj1hp90c+YaSBdAx5ESJx1T4BIRYEh8dvP9/SrGw=; h=Cc:Date:From:Reply-To:Subject:To; b=LcYDrAiPkT4l6OMwrJHEQl3K64ys6g1pooexJdLCunTZgxqLkpu+KnnyTunUVN0yLCg TuHqjzIlWOhWVicQ1VQztZHFqDQpTYCuQPbLltkiC75EWcqDQCEJqLGIm6lJgx4IdiRV7 MqXjWp7tf9EtqiHcuIXwOHqEvkFBPlxgbvs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678062136111100008 Content-Type: text/plain; charset="utf-8" Adds ARM implementation of EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI. Cc: Andrew Fish Cc: Ray Ni Cc: Michael D Kinney Cc: Chasel Chiu Signed-off-by: Nate DeSimone Tested-by: Ard Biesheuvel --- EmulatorPkg/Sec/Arm/SwitchRam.S | 32 ++++++++++++++++++ EmulatorPkg/Sec/Arm/TempRam.c | 58 +++++++++++++++++++++++++++++++++ EmulatorPkg/Sec/Sec.inf | 9 ++++- 3 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 EmulatorPkg/Sec/Arm/SwitchRam.S create mode 100644 EmulatorPkg/Sec/Arm/TempRam.c diff --git a/EmulatorPkg/Sec/Arm/SwitchRam.S b/EmulatorPkg/Sec/Arm/SwitchRa= m.S new file mode 100644 index 0000000000..d64772b8ed --- /dev/null +++ b/EmulatorPkg/Sec/Arm/SwitchRam.S @@ -0,0 +1,32 @@ +#-------------------------------------------------------------------------= ----- +# +# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-------------------------------------------------------------------------= ----- + +#include + +#/** +# This allows the caller to switch the stack and return +# +# @param StackDelta Signed amount by which to modify the stack po= inter +# +# @return Nothing. Goes to the Entry Point passing in the new paramete= rs +# +#**/ +#VOID +#EFIAPI +#SecSwitchStack ( +# VOID *StackDelta +# )# +# +ASM_FUNC(SecSwitchStack) + mov R1, R13 + add R1, R0, R1 + mov R13, R1 + bx LR + + + diff --git a/EmulatorPkg/Sec/Arm/TempRam.c b/EmulatorPkg/Sec/Arm/TempRam.c new file mode 100644 index 0000000000..0a6b215591 --- /dev/null +++ b/EmulatorPkg/Sec/Arm/TempRam.c @@ -0,0 +1,58 @@ +/*++ @file + Temp RAM PPI + + Copyright (c) 2011, Apple Inc. All rights reserved.
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include + +VOID +SecSwitchStack ( + INTN StackDelta + ); + +EFI_STATUS +EFIAPI +SecTemporaryRamSupport ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + // + // Migrate the whole temporary memory to permanent memory. + // + CopyMem ( + (VOID *)(UINTN)PermanentMemoryBase, + (VOID *)(UINTN)TemporaryMemoryBase, + CopySize + ); + + // + // SecSwitchStack function must be invoked after the memory migration + // immediately, also we need fixup the stack change caused by new call i= nto + // permanent memory. + // + SecSwitchStack ((UINTN)(PermanentMemoryBase - TemporaryMemoryBase)); + + // + // We need *not* fix the return address because currently, + // The PeiCore is executed in flash. + // + + // + // Simulate to invalid temporary memory, terminate temporary memory + // + // ZeroMem ((VOID*)(UINTN)TemporaryMemoryBase, CopySize); + + return EFI_SUCCESS; +} diff --git a/EmulatorPkg/Sec/Sec.inf b/EmulatorPkg/Sec/Sec.inf index 2f9e3d4780..264666f544 100644 --- a/EmulatorPkg/Sec/Sec.inf +++ b/EmulatorPkg/Sec/Sec.inf @@ -3,7 +3,7 @@ # # Main executable file of Unix Emulator that loads PEI core after initiali= zation finished. # Portions copyright (c) 2011, Apple Inc. All rights reserved.
-# Copyright (c) 2012, Intel Corporation. All rights reserved.
+# Copyright (c) 2012 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -30,10 +30,17 @@ Ia32/SwitchRam.asm Ia32/SwitchRam.S =20 +[Sources.ARM] + Arm/TempRam.c + Arm/SwitchRam.S + [Packages] MdePkg/MdePkg.dec EmulatorPkg/EmulatorPkg.dec =20 +[Packages.ARM] + ArmPkg/ArmPkg.dec + [LibraryClasses] DebugLib PeCoffGetEntryPointLib --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100706): https://edk2.groups.io/g/devel/message/100706 Mute This Topic: https://groups.io/mt/97414910/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 22:20:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100708+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100708+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1678062135; cv=none; d=zohomail.com; s=zohoarc; b=NxmPeAPl7X8+4c3G9W8flLwXsHfTqvCPZuJUJDSu1KriRkFA/92jjmW9rtdYDB/2zR4bktH0H1EvgHhNSMYWsQJ/xgpNnMfu/+TVxMN68mLdgxX2lshmWZIFqTEs72KAkXwFx7CEP/144ztovSuzqmXGrb5a0g8OpPV+I/4I/3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678062135; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Mq9cZqfCQAa3V19USoTbHuMqe55ofoDRgEMfrRn65z8=; b=nfA+vDcclmrlPnU3a7JRXW0VdlZo28T68D2y7qPaRQNC1ufoh/kSU+3d7IlueGcLOnLWzXZid81qjAIZKDsvNxVbhhSc0aHdT/OZbScNbmMR2EczdMTmMYplz56Xrr0MoYwxkvuOj5mB7Q3apDI451zKsSof6YQrzij6882Nqk8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100708+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678062135831272.3793264649295; Sun, 5 Mar 2023 16:22:15 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id YDi6YY1788612xhAnnxRstYf; Sun, 05 Mar 2023 16:22:15 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.22191.1678062132259075315 for ; Sun, 05 Mar 2023 16:22:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="337758121" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="337758121" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10640"; a="669263326" X-IronPort-AV: E=Sophos;i="5.98,236,1673942400"; d="scan'208";a="669263326" X-Received: from nldesimo-desk.amr.corp.intel.com ([10.24.12.177]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2023 16:22:11 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Andrew Fish , Ray Ni , Michael D Kinney , Chasel Chiu Subject: [edk2-devel] [PATCH v1 6/6] EmulatorPkg: Add EmuCacheMaintenanceLib Date: Sun, 5 Mar 2023 16:22:05 -0800 Message-Id: <20230306002205.1640-7-nathaniel.l.desimone@intel.com> In-Reply-To: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> References: <20230306002205.1640-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: Lgf2QKGQw26nUGyUn8Aqm1Pjx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678062135; bh=2hFO35lXM2LIWXLSWG4U0WgsHxgGiOvSY/U5JsZ+o/Y=; h=Cc:Date:From:Reply-To:Subject:To; b=Nexqh+mrqQm/ekDS4A4ABoijb1USySijY9ft5Dx5nEaq9NJ+0BOV4PKV0BhWD05yywz lU7waIQiIineOdZ3riBE74DhPRVQ7LVZudDiOc3bN+CO0CyxgfKueVM2AqSrwfDe6XYoY 3lUavtLVjLCwTFh+WACnz+6vxT5BUGFhi6o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678062136128100012 Content-Type: text/plain; charset="utf-8" Adds new implementation of CacheMaintenanceLib that uses the GCC intrinsic __builtin__clear_cache() to clear processor caches. This is required on machine types that use a syscall to access the cache controller. Cc: Andrew Fish Cc: Ray Ni Cc: Michael D Kinney Cc: Chasel Chiu Signed-off-by: Nate DeSimone Tested-by: Ard Biesheuvel --- EmulatorPkg/EmulatorPkg.dec | 4 +- EmulatorPkg/EmulatorPkg.dsc | 7 + EmulatorPkg/Include/Protocol/EmuCache.h | 217 +++++++++++ .../DxeEmuCacheMaintenanceLib.c | 337 +++++++++++++++++ .../DxeEmuCacheMaintenanceLib.inf | 37 ++ .../PeiEmuCacheMaintenanceLib.c | 344 ++++++++++++++++++ .../PeiEmuCacheMaintenanceLib.inf | 39 ++ EmulatorPkg/Unix/Host/CacheMaintenance.c | 284 +++++++++++++++ EmulatorPkg/Unix/Host/Host.c | 5 +- EmulatorPkg/Unix/Host/Host.h | 2 + EmulatorPkg/Unix/Host/Host.inf | 2 + 11 files changed, 1276 insertions(+), 2 deletions(-) create mode 100644 EmulatorPkg/Include/Protocol/EmuCache.h create mode 100644 EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCac= heMaintenanceLib.c create mode 100644 EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCac= heMaintenanceLib.inf create mode 100644 EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCac= heMaintenanceLib.c create mode 100644 EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCac= heMaintenanceLib.inf create mode 100644 EmulatorPkg/Unix/Host/CacheMaintenance.c diff --git a/EmulatorPkg/EmulatorPkg.dec b/EmulatorPkg/EmulatorPkg.dec index fe81652b04..adf615f796 100644 --- a/EmulatorPkg/EmulatorPkg.dec +++ b/EmulatorPkg/EmulatorPkg.dec @@ -2,7 +2,7 @@ # # This is the Emu Emulation Environment Platform # -# Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
# Portions copyright (c) 2011, Apple Inc. All rights reserved. # (C) Copyright 2020 Hewlett Packard Enterprise Development LP
# @@ -37,6 +37,7 @@ gEmuThreadThunkProtocolGuid =3D { 0x3B1E4B7C, 0x09D8, 0x944F, { 0xA4,= 0x08, 0x13, 0x09, 0xEB, 0x8B, 0x44, 0x27 } } gEmuBlockIoProtocolGuid =3D { 0x6888A4AE, 0xAFCE, 0xE84B, { 0x91,= 0x02, 0xF7, 0xB9, 0xDA, 0xE6, 0xA0, 0x30 } } gEmuSnpProtocolGuid =3D { 0xFD5FBE54, 0x8C35, 0xB345, { 0x8A,= 0x0F, 0x7A, 0xC8, 0xA5, 0xFD, 0x05, 0x21 } } + gEmuCacheThunkProtocolGuid =3D { 0x8816732A, 0xF6DE, 0x466A, { 0x8E,= 0x47, 0x1C, 0xE0, 0xEE, 0x1F, 0xB3, 0x3A } } =20 [Ppis] gEmuThunkPpiGuid =3D { 0xE113F896, 0x75CF, 0xF640, { 0x81,= 0x7F, 0xC8, 0x5A, 0x79, 0xE8, 0xAE, 0x67 } } @@ -109,6 +110,7 @@ gEmulatorPkgTokenSpaceGuid.PcdEmuGop|L"GOP Window"|VOID*|0x00001018 gEmulatorPkgTokenSpaceGuid.PcdEmuFileSystem|L"."|VOID*|0x00001004 gEmulatorPkgTokenSpaceGuid.PcdEmuSerialPort|L"/dev/ttyS0"|VOID*|0x000010= 02 + gEmulatorPkgTokenSpaceGuid.PcdEmuCache|L"CacheCtl"|VOID*|0x0000101d =20 # # On Unix host, this is the network interface name on host system that w= ill diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc index 62d853e470..601c2d7988 100644 --- a/EmulatorPkg/EmulatorPkg.dsc +++ b/EmulatorPkg/EmulatorPkg.dsc @@ -187,6 +187,9 @@ [LibraryClasses.common.PEIM] PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf =20 +[LibraryClasses.ARM.PEIM, LibraryClasses.ARM.PEI_CORE] + CacheMaintenanceLib|EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmu= CacheMaintenanceLib.inf + [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf @@ -217,6 +220,9 @@ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf TimerLib|EmulatorPkg/Library/DxeTimerLib/DxeTimerLib.inf =20 +[LibraryClasses.ARM.DXE_CORE, LibraryClasses.ARM.DXE_RUNTIME_DRIVER, Libra= ryClasses.ARM.UEFI_DRIVER, LibraryClasses.ARM.DXE_DRIVER, LibraryClasses.AR= M.UEFI_APPLICATION] + CacheMaintenanceLib|EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmu= CacheMaintenanceLib.inf + [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE =20 @@ -269,6 +275,7 @@ gEmulatorPkgTokenSpaceGuid.PcdEmuFileSystem|L"." gEmulatorPkgTokenSpaceGuid.PcdEmuSerialPort|L"/dev/ttyS0" gEmulatorPkgTokenSpaceGuid.PcdEmuNetworkInterface|L"en0" + gEmulatorPkgTokenSpaceGuid.PcdEmuCache|L"CacheCtl" =20 gEmulatorPkgTokenSpaceGuid.PcdEmuCpuModel|L"Intel(R) Processor Model" gEmulatorPkgTokenSpaceGuid.PcdEmuCpuSpeed|L"3000" diff --git a/EmulatorPkg/Include/Protocol/EmuCache.h b/EmulatorPkg/Include/= Protocol/EmuCache.h new file mode 100644 index 0000000000..3c05e7807c --- /dev/null +++ b/EmulatorPkg/Include/Protocol/EmuCache.h @@ -0,0 +1,217 @@ +/** @file + Invoke syscalls for cache maintenance on platforms that require kernel + mode to manage the cache. ARM and RISC-V for example. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EMU_CACHE__ +#define __EMU_CACHE__ + +typedef struct _EMU_CACHE_THUNK_PROTOCOL EMU_CACHE_THUNK_PROTOCOL; + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +typedef +VOID +(EFIAPI *EMU_CACHE_PROTOCOL_INVALIDATE_INSTRUCTION_CACHE) ( + VOID + ); + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +typedef +VOID * +(EFIAPI *EMU_CACHE_PROTOCOL_INVALIDATE_INSTRUCTION_CACHE_RANGE)( + IN VOID *Address, + IN UINTN Length + ); + +/** + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +typedef +VOID +(EFIAPI *EMU_CACHE_PROTOCOL_WRITE_BACK_INVALIDATE_DATA_CACHE)( + VOID + ); + +/** + Writes Back and Invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +typedef +VOID * +(EFIAPI *EMU_CACHE_PROTOCOL_WRITE_BACK_INVALIDATE_DATA_CACHE_RANGE)( + IN VOID *Address, + IN UINTN Length + ); + +/** + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +typedef +VOID +(EFIAPI *EMU_CACHE_PROTOCOL_WRITE_BACK_DATA_CACHE)( + VOID + ); + +/** + Writes Back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes Back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +typedef +VOID * +(EFIAPI *EMU_CACHE_PROTOCOL_WRITE_BACK_DATA_CACHE_RANGE)( + IN VOID *Address, + IN UINTN Length + ); + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +typedef +VOID +(EFIAPI *EMU_CACHE_PROTOCOL_INVALIDATE_DATA_CACHE)( + VOID + ); + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, the no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +typedef +VOID * +(EFIAPI *EMU_CACHE_INVALIDATE_DATA_CACHE_RANGE)( + IN VOID *Address, + IN UINTN Length + ); + +struct _EMU_CACHE_THUNK_PROTOCOL { + EMU_CACHE_PROTOCOL_INVALIDATE_INSTRUCTION_CACHE InvalidateIn= structionCache; + EMU_CACHE_PROTOCOL_INVALIDATE_INSTRUCTION_CACHE_RANGE InvalidateIn= structionCacheRange; + EMU_CACHE_PROTOCOL_WRITE_BACK_INVALIDATE_DATA_CACHE WriteBackInv= alidateDataCache; + EMU_CACHE_PROTOCOL_WRITE_BACK_INVALIDATE_DATA_CACHE_RANGE WriteBackInv= alidateDataCacheRange; + EMU_CACHE_PROTOCOL_WRITE_BACK_DATA_CACHE WriteBackDat= aCache; + EMU_CACHE_PROTOCOL_WRITE_BACK_DATA_CACHE_RANGE WriteBackDat= aCacheRange; + EMU_CACHE_PROTOCOL_INVALIDATE_DATA_CACHE InvalidateDa= taCache; + EMU_CACHE_INVALIDATE_DATA_CACHE_RANGE InvalidateDa= taCacheRange; +}; + +#endif diff --git a/EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCacheMaint= enanceLib.c b/EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCacheMain= tenanceLib.c new file mode 100644 index 0000000000..2db07b5bd0 --- /dev/null +++ b/EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCacheMaintenanceL= ib.c @@ -0,0 +1,337 @@ +/** @file + Instance of Cache Maintenance Library using emulator thunks to OS syscal= ls + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +EFI_STATUS +EFIAPI +DxeGetCacheThunkProtocol ( + OUT EMU_CACHE_THUNK_PROTOCOL **EmuCache + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EMU_THUNK_PROTOCOL *Thunk; + EMU_IO_THUNK_PROTOCOL *EmuIoThunk; + EFI_STATUS Status; + + // + // Get Unix Thunk Protocol so we can retrieve I/O Thunk Protocols + // + GuidHob =3D GetFirstGuidHob (&gEmuThunkProtocolGuid); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + Thunk =3D (EMU_THUNK_PROTOCOL *)(*(UINTN *)(GET_GUID_HOB_DATA (GuidHob))= ); + if (Thunk =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + // + // Locate the I/O Thunk Protocol representing the Cache Thunk Protocol + // + for (Status =3D EFI_SUCCESS, EmuIoThunk =3D NULL; !EFI_ERROR (Status); )= { + Status =3D Thunk->GetNextProtocol (FALSE, &EmuIoThunk); + if (EFI_ERROR (Status)) { + break; + } + + if (EmuIoThunk->Instance =3D=3D 0) { + if (CompareGuid (EmuIoThunk->Protocol, &gEmuCacheThunkProtocolGuid))= { + // + // Open the I/O Thunk Protocol to retrieve the Cache Thunk Protocol + // + Status =3D EmuIoThunk->Open (EmuIoThunk); + if (EFI_ERROR (Status)) { + return Status; + } + *EmuCache =3D (EMU_CACHE_THUNK_PROTOCOL *) EmuIoThunk->Interface; + return EFI_SUCCESS; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->InvalidateInstructionCache (); + } +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->InvalidateInstructionCacheRange (Address, Length); + } + return NULL; +} + +/** + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->WriteBackInvalidateDataCache (); + } +} + +/** + Writes Back and Invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->WriteBackInvalidateDataCacheRange (Address, Length); + } + return NULL; +} + +/** + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->WriteBackDataCache (); + } +} + +/** + Writes Back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes Back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->WriteBackDataCacheRange (Address, Length); + } + return NULL; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->InvalidateDataCache (); + } +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, the no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D DxeGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->InvalidateDataCacheRange (Address, Length); + } + return NULL; +} diff --git a/EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCacheMaint= enanceLib.inf b/EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCacheMa= intenanceLib.inf new file mode 100644 index 0000000000..e71fa218d5 --- /dev/null +++ b/EmulatorPkg/Library/DxeEmuCacheMaintenanceLib/DxeEmuCacheMaintenanceL= ib.inf @@ -0,0 +1,37 @@ +## @file +# Instance of Cache Maintenance Library using emulator thunks to OS sysca= lls +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeEmuCacheMaintenanceLib + FILE_GUID =3D 4ee4f13e-3aab-4654-9af9-36e0fa53107f + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.1 + LIBRARY_CLASS =3D CacheMaintenanceLib|DXE_CORE DXE_DRIV= ER DXE_RUNTIME_DRIVER UEFI_DRIVER UEFI_APPLICATION + +# +# VALID_ARCHITECTURES =3D IA32 X64 ARM +# + +[Sources] + DxeEmuCacheMaintenanceLib.c + +[Packages] + MdePkg/MdePkg.dec + EmulatorPkg/EmulatorPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + HobLib + +[Protocols] + gEmuThunkProtocolGuid + gEmuCacheThunkProtocolGuid diff --git a/EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCacheMaint= enanceLib.c b/EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCacheMain= tenanceLib.c new file mode 100644 index 0000000000..0abf63cd21 --- /dev/null +++ b/EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCacheMaintenanceL= ib.c @@ -0,0 +1,344 @@ +/** @file + Instance of Cache Maintenance Library using emulator thunks to OS syscal= ls + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +PeiGetCacheThunkProtocol ( + OUT EMU_CACHE_THUNK_PROTOCOL **EmuCache + ) +{ + EMU_THUNK_PPI *ThunkPpi; + EMU_THUNK_PROTOCOL *Thunk; + EMU_IO_THUNK_PROTOCOL *EmuIoThunk; + EFI_STATUS Status; + + // + // Locate Unix Thunk Ppi + // + Status =3D PeiServicesLocatePpi ( + &gEmuThunkPpiGuid, + 0, + NULL, + (VOID **)&ThunkPpi + ); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Get the Unix Thunk Protocol so we can retrieve I/O Thunk Protocols + // + Thunk =3D (EMU_THUNK_PROTOCOL *)ThunkPpi->Thunk (); + if (Thunk =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + // + // Locate the I/O Thunk Protocol representing the Cache Thunk Protocol + // + for (Status =3D EFI_SUCCESS, EmuIoThunk =3D NULL; !EFI_ERROR (Status); )= { + Status =3D Thunk->GetNextProtocol (FALSE, &EmuIoThunk); + if (EFI_ERROR (Status)) { + break; + } + + if (EmuIoThunk->Instance =3D=3D 0) { + if (CompareGuid (EmuIoThunk->Protocol, &gEmuCacheThunkProtocolGuid))= { + // + // Open the I/O Thunk Protocol to retrieve the Cache Thunk Protocol + // + Status =3D EmuIoThunk->Open (EmuIoThunk); + if (EFI_ERROR (Status)) { + return Status; + } + *EmuCache =3D (EMU_CACHE_THUNK_PROTOCOL *) EmuIoThunk->Interface; + return EFI_SUCCESS; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->InvalidateInstructionCache (); + } +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->InvalidateInstructionCacheRange (Address, Length); + } + return NULL; +} + +/** + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->WriteBackInvalidateDataCache (); + } +} + +/** + Writes Back and Invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->WriteBackInvalidateDataCacheRange (Address, Length); + } + return NULL; +} + +/** + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->WriteBackDataCache (); + } +} + +/** + Writes Back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes Back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->WriteBackDataCacheRange (Address, Length); + } + return NULL; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + EmuCache->InvalidateDataCache (); + } +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, the no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + EMU_CACHE_THUNK_PROTOCOL *EmuCache; + EFI_STATUS Status; + + Status =3D PeiGetCacheThunkProtocol (&EmuCache); + if (!EFI_ERROR (Status) && EmuCache !=3D NULL) { + return EmuCache->InvalidateDataCacheRange (Address, Length); + } + return NULL; +} diff --git a/EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCacheMaint= enanceLib.inf b/EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCacheMa= intenanceLib.inf new file mode 100644 index 0000000000..4e8b05e8a7 --- /dev/null +++ b/EmulatorPkg/Library/PeiEmuCacheMaintenanceLib/PeiEmuCacheMaintenanceL= ib.inf @@ -0,0 +1,39 @@ +## @file +# Instance of Cache Maintenance Library using emulator thunks to OS sysca= lls +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiEmuCacheMaintenanceLib + FILE_GUID =3D 00b3e408-f999-4cf4-ba95-166678fc867c + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.1 + LIBRARY_CLASS =3D CacheMaintenanceLib|PEI_CORE PEIM + +# +# VALID_ARCHITECTURES =3D IA32 X64 ARM +# + +[Sources] + PeiEmuCacheMaintenanceLib.c + +[Packages] + MdePkg/MdePkg.dec + EmulatorPkg/EmulatorPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PeiServicesLib + +[Ppis] + gEmuThunkPpiGuid # PPI ALWAYS_CONSUMED + +[Protocols] + gEmuCacheThunkProtocolGuid diff --git a/EmulatorPkg/Unix/Host/CacheMaintenance.c b/EmulatorPkg/Unix/Ho= st/CacheMaintenance.c new file mode 100644 index 0000000000..13dccda9bb --- /dev/null +++ b/EmulatorPkg/Unix/Host/CacheMaintenance.c @@ -0,0 +1,284 @@ +/** @file + Invoke syscalls for cache maintenance on platforms that require kernel + mode to manage the instruction cache. ARM and RISC-V for example. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Host.h" + +extern UINTN gSystemMemoryCount; +extern EMU_SYSTEM_MEMORY *gSystemMemory; + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +EmuInvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + __builtin___clear_cache ((char*)Address, ((char*)Address) + Length); + + return Address; +} + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +EmuInvalidateInstructionCache ( + VOID + ) +{ + UINTN Index; + + if (gSystemMemory !=3D NULL) { + for (Index =3D 0; Index < gSystemMemoryCount; Index++) { + if (gSystemMemory[Index].Memory !=3D 0) { + EmuInvalidateInstructionCacheRange ((VOID *)(UINTN)gSystemMemory[I= ndex].Memory, gSystemMemory[Index].Size); + } + } + } +} + +/** + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes Back and Invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +EmuWriteBackInvalidateDataCache ( + VOID + ) +{ + EmuInvalidateInstructionCache (); +} + +/** + Writes Back and Invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +EmuWriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + return EmuInvalidateInstructionCacheRange (Address, Length); +} + +/** + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes Back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +EmuWriteBackDataCache ( + VOID + ) +{ + EmuWriteBackInvalidateDataCache (); +} + +/** + Writes Back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes Back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +EmuWriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + return EmuWriteBackInvalidateDataCacheRange (Address, Length); +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +EmuInvalidateDataCache ( + VOID + ) +{ + EmuWriteBackInvalidateDataCache (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, the no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +EmuInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + return EmuWriteBackInvalidateDataCacheRange (Address, Length); +} + +EMU_CACHE_THUNK_PROTOCOL gEmuCacheThunk =3D { + EmuInvalidateInstructionCache, + EmuInvalidateInstructionCacheRange, + EmuWriteBackInvalidateDataCache, + EmuWriteBackInvalidateDataCacheRange, + EmuWriteBackDataCache, + EmuWriteBackDataCacheRange, + EmuInvalidateDataCache, + EmuInvalidateDataCacheRange +}; + +EFI_STATUS +EFIAPI +CacheOpen ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + if (This->Instance !=3D 0) { + // Only single instance is supported + return EFI_NOT_FOUND; + } + + This->Interface =3D &gEmuCacheThunk; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +CacheClose ( + IN EMU_IO_THUNK_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +EMU_IO_THUNK_PROTOCOL gCacheThunkIo =3D { + &gEmuCacheThunkProtocolGuid, + NULL, + NULL, + 0, + CacheOpen, + CacheClose, + NULL +}; diff --git a/EmulatorPkg/Unix/Host/Host.c b/EmulatorPkg/Unix/Host/Host.c index 1f29dd00a3..06241c7127 100644 --- a/EmulatorPkg/Unix/Host/Host.c +++ b/EmulatorPkg/Unix/Host/Host.c @@ -1,6 +1,6 @@ /*++ @file =20 -Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2011, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -165,6 +165,9 @@ main ( // Emulator other Thunks // AddThunkProtocol (&gPthreadThunkIo, (CHAR16 *)PcdGetPtr (PcdEmuApCount),= FALSE); +#if defined (MDE_CPU_ARM) + AddThunkProtocol (&gCacheThunkIo, (CHAR16 *)PcdGetPtr (PcdEmuCache), FAL= SE); +#endif =20 // EmuSecLibConstructor (); =20 diff --git a/EmulatorPkg/Unix/Host/Host.h b/EmulatorPkg/Unix/Host/Host.h index 0c81cdfc01..95d482d8d2 100644 --- a/EmulatorPkg/Unix/Host/Host.h +++ b/EmulatorPkg/Unix/Host/Host.h @@ -115,6 +115,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include @@ -356,5 +357,6 @@ extern EMU_IO_THUNK_PROTOCOL gPosixFileSystemThunkIo; extern EMU_IO_THUNK_PROTOCOL gPthreadThunkIo; extern EMU_IO_THUNK_PROTOCOL gBlockIoThunkIo; extern EMU_IO_THUNK_PROTOCOL gSnpThunkIo; +extern EMU_IO_THUNK_PROTOCOL gCacheThunkIo; =20 #endif diff --git a/EmulatorPkg/Unix/Host/Host.inf b/EmulatorPkg/Unix/Host/Host.inf index effd0a3217..6cb6e12b00 100644 --- a/EmulatorPkg/Unix/Host/Host.inf +++ b/EmulatorPkg/Unix/Host/Host.inf @@ -80,6 +80,7 @@ gEmuThreadThunkProtocolGuid gEmuBlockIoProtocolGuid gEmuSnpProtocolGuid + gEmuCacheThunkProtocolGuid gEfiSimpleFileSystemProtocolGuid =20 [Guids] @@ -99,6 +100,7 @@ gEmulatorPkgTokenSpaceGuid.PcdEmuGop|L"GOP Window" gEmulatorPkgTokenSpaceGuid.PcdEmuFileSystem gEmulatorPkgTokenSpaceGuid.PcdEmuSerialPort + gEmulatorPkgTokenSpaceGuid.PcdEmuCache gEmulatorPkgTokenSpaceGuid.PcdEmuNetworkInterface gEmulatorPkgTokenSpaceGuid.PcdNetworkPacketFilterSize =20 --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100708): https://edk2.groups.io/g/devel/message/100708 Mute This Topic: https://groups.io/mt/97414912/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-