From nobody Tue Feb 10 05:10:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100686+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100686+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1677837834; cv=none; d=zohomail.com; s=zohoarc; b=ANZ6fDU7LuPffULBhLtqQHGV6MzE2HsXTREefcFVrgD9tBfxIRyPMadknDG9rwDZao3BnCMC5QDIlIHVoNWpBbzVTaH7HmobZo8U8u4dZ98IzuCjMqM9O0HN7wh1Wc7Cllodcw4B91IJaQwTVM6zpxX2vWjG7uI7z8pyW8eLBYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677837834; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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d="scan'208";a="318831677" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 02:03:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="818420998" X-IronPort-AV: E=Sophos;i="5.98,230,1673942400"; d="scan'208";a="818420998" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2023 02:03:52 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH 2/6] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Fri, 3 Mar 2023 18:03:32 +0800 Message-Id: <20230303100336.2138-3-dun.tan@intel.com> In-Reply-To: <20230303100336.2138-1-dun.tan@intel.com> References: <20230303100336.2138-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: tIoKeTT3vgPOm24qXOIhbYtGx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677837834; bh=Ig3+v5xDgC3O9FaPhkLZZrFvdjMlm7OXTuP0ovzdOps=; h=Cc:Date:From:Reply-To:Subject:To; b=exL8fq7yy/IraxerSG0PCUFp2nc0VfY6keycK9OPs/x+VA+ogDeauZVZGFlaLq6CiFD K9A6W/YssjdoYhvBSjI/rAbszYHTHXDj0aoWqGA+U2vWEI1nO+gykaYwd8zSg5YnJ3i1Q TJ5zMVP9h8yhkxyMHaQ6ofLsn+TGNn1pFrQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677837836436100005 Content-Type: text/plain; charset="utf-8" Fix the non-1:1 mapping issue in PageTableMap () of CpuPageTableLib Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 27 ++++++++++++++++= +---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 47027917d9..d2f35aa375 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,13 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). + // + BitStart =3D 12 + (Level - 1) * 9; + PagingEntryIndex =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitS= tart, BitStart + 9 - 1); + RegionLength =3D REGION_LENGTH (Level); + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. @@ -325,8 +333,11 @@ PageTableLibMapInLevel ( // the actual attributes of grand-parents when determing the memory ty= pe. // PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && + ( (Mask->Bits.PageTableBaseAddress =3D=3D 0) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) + =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) { // // This function is called when the memory length is less than the r= egion length of the parent level. @@ -353,8 +364,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); =20 - RegionLength =3D REGION_LENGTH (Level); - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; SubOffset +=3D RegionLength; @@ -425,14 +435,11 @@ PageTableLibMapInLevel ( } =20 // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLe= ngth and lower than (LinearAddress + Offset). // - BitStart =3D 12 + (Level - 1) * 9; - Index =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart= , BitStart + 9 - 1); - RegionLength =3D LShiftU64 (1, BitStart); - RegionMask =3D RegionLength - 1; - RegionStart =3D (LinearAddress + Offset) & ~RegionMask; + Index =3D PagingEntryIndex; + RegionMask =3D RegionLength - 1; + RegionStart =3D (LinearAddress + Offset) & ~RegionMask; =20 ParentAttribute->Uint64 =3D PageTableLibGetPnleMapAttribute (&ParentPagi= ngEntry->Pnle, ParentAttribute); =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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