From nobody Thu May 2 13:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100459+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100459+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1677175581; cv=none; d=zohomail.com; s=zohoarc; b=Ps9Jfv2HFcdfvUeCzo1OTM4LY2RwBwfd1Unl3CAmsPUHuE3N2vMrLNXzj7ACg8hqOrE1m645OOe6z4zpJU1oLSY+SfdnPZOFTju1/wSmgV/bs5czXVjKyjjPhVnpdNnaw/a0vH6ifXxnYCvVxj6R8zXJVyqIkI7L7Smo5bIQRXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677175581; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/OEX2uyAmgbE4r+SO9SSGT8sIjjU5JJnWcq4dx2MxZ8=; b=A8Zv6qyumbDaguexHB+GyV2CbZE7wEEUlid0yL///yoyvFkO67qeFACat5Ld0dvHqwjo/BFhLG0L+H1exxopcaeon3LlWP1VWRm7P7lDRiLAPzjet/5X3slj5V4AWfkgbX1cnjat47uvsXJqxIKU427id+t1Fo3OBET4wR7fouE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100459+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1677175581015889.4565465902713; Thu, 23 Feb 2023 10:06:21 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id oGr4YY1788612xDjX1GK726o; Thu, 23 Feb 2023 10:06:20 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.18315.1677175578044889092 for ; Thu, 23 Feb 2023 10:06:20 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="333288059" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="333288059" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:05:57 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="918106808" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="918106808" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.166]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:05:55 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [Patch V3 1/6] UefiCpuPkg: Move AsmRelocateApLoop to AmdSev.nasm. Date: Fri, 24 Feb 2023 02:05:30 +0800 Message-Id: <20230223180535.10383-2-yuanhao.xie@intel.com> In-Reply-To: <20230223180535.10383-1-yuanhao.xie@intel.com> References: <20230223180535.10383-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: jFoBV3UactVjISb4EWX8gJApx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677175580; bh=vJn+AQBXqXracxUBeAei7euiWldN8BojAkKYatlX1qo=; h=Cc:Date:From:Reply-To:Subject:To; b=ika7Ol3tpsjvLN/3YUdMeLvSIpe/JGyD1PpTb1IMJ2Ps3qFy28ZcmTvREOyNAVM9n3W VzIoPLL87mug86xX4OgJmsrmFkX9JH5p5VeKskLgdjIiC9iC2rJySkanCXpZ4sHxjkXit U2uRSjkmWmDvvI16KerrJHvSFzdQioAdcMM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677175581423100006 Content-Type: text/plain; charset="utf-8" AMD processors with SEV-ES enabled follow the original logic, for the other cases the APs will be put in 64-bit mode before handing off the boot process to the OS. In order to do so, in this patch, AsmRelocateApLoop is moved to AmdSev.nasm. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie Test-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 168 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 170 +---------------------= ---------------------------------------------------------------------------= ------------------------------------------------------------------------- 2 files changed, 169 insertions(+), 169 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Libr= ary/MpInitLib/X64/AmdSev.nasm index 7c2469f9c5..c1e8a045a4 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -346,3 +346,171 @@ PM16Mode: iret =20 SwitchToRealProcEnd: +;-------------------------------------------------------------------------= ------------ +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +;-------------------------------------------------------------------------= ------------ +AsmRelocateApLoopStart: +BITS 64 + cmp qword [rsp + 56], 0 ; SevEsAPJumpTable + je NoSevEs + + ; + ; Perform some SEV-ES related setup before leaving 64-bit mode + ; + push rcx + push rdx + + ; + ; Get the RDX reset value using CPUID + ; + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for RDX + + ; + ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call + ; - Must be done while in 64-bit long mode so that writes to + ; the GHCB memory will be unencrypted. + ; - No NAE events can be generated once this is set otherwise + ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. + ; + mov rcx, 0xc0010130 + rdmsr ; Retrieve current GHCB address + shl rdx, 32 + or rdx, rax + + mov rdi, rdx + xor rax, rax + mov rcx, 0x800 + shr rcx, 3 + rep stosq ; Clear the GHCB + + mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD + mov [rdx + 0x390], rax + mov rax, 114 ; Set SwExitCode valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo1 valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo2 valid bit + bts [rdx + 0x3f0], rax + + pop rdx + pop rcx + +NoSevEs: + cli ; Disable interrupt before switching to 3= 2-bit mode + mov rax, [rsp + 40] ; CountTofinish + lock dec dword [rax] ; (*CountTofinish)-- + + mov r10, [rsp + 48] ; Pm16CodeSegment + mov rax, [rsp + 56] ; SevEsAPJumpTable + mov rbx, [rsp + 64] ; WakeupBuffer + mov rsp, r9 ; TopOfApStack + + push rax ; Save SevEsAPJumpTable + push rbx ; Save WakeupBuffer + push r10 ; Save Pm16CodeSegment + push rcx ; Save MwaitSupport + push rdx ; Save ApTargetCState + + lea rax, [PmEntry] ; rax <- The start address of transition = code + + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; + retfq + +BITS 32 +PmEntry: + mov eax, cr0 + btr eax, 31 ; Clear CR0.PG + mov cr0, eax ; Disable paging and caches + + mov ecx, 0xc0000080 + rdmsr + and ah, ~ 1 ; Clear LME + wrmsr + mov eax, cr4 + and al, ~ (1 << 5) ; Clear PAE + mov cr4, eax + + pop edx + add esp, 4 + pop ecx, + add esp, 4 + +MwaitCheck: + cmp cl, 1 ; Check mwait-monitor support + jnz HltLoop + mov ebx, edx ; Save C-State to ebx +MwaitLoop: + cli + mov eax, esp ; Set Monitor Address + xor ecx, ecx ; ecx =3D 0 + xor edx, edx ; edx =3D 0 + monitor + mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] + shl eax, 4 + mwait + jmp MwaitLoop + +HltLoop: + pop edx ; PM16CodeSegment + add esp, 4 + pop ebx ; WakeupBuffer + add esp, 4 + pop eax ; SevEsAPJumpTable + add esp, 4 + cmp eax, 0 ; Check for SEV-ES + je DoHlt + + cli + ; + ; SEV-ES is enabled, use VMGEXIT (GHCB information already + ; set by caller) + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Back from VMGEXIT AP_HLT_LOOP + ; Push the FLAGS/CS/IP values to use + ; + push word 0x0002 ; EFLAGS + xor ecx, ecx + mov cx, [eax + 2] ; CS + push cx + mov cx, [eax] ; IP + push cx + push word 0x0000 ; For alignment, will be discarded + + push edx + push ebx + + mov edx, esi ; Restore RDX reset value + + retf + +DoHlt: + cli + hlt + jmp DoHlt + +BITS 64 +AsmRelocateApLoopEnd: diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 5d71995bf8..eb42bbff96 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -278,174 +278,6 @@ CProcedureInvoke: =20 RendezvousFunnelProcEnd: =20 -;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); -;-------------------------------------------------------------------------= ------------ -AsmRelocateApLoopStart: -BITS 64 - cmp qword [rsp + 56], 0 ; SevEsAPJumpTable - je NoSevEs - - ; - ; Perform some SEV-ES related setup before leaving 64-bit mode - ; - push rcx - push rdx - - ; - ; Get the RDX reset value using CPUID - ; - mov rax, 1 - cpuid - mov rsi, rax ; Save off the reset value for RDX - - ; - ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call - ; - Must be done while in 64-bit long mode so that writes to - ; the GHCB memory will be unencrypted. - ; - No NAE events can be generated once this is set otherwise - ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. - ; - mov rcx, 0xc0010130 - rdmsr ; Retrieve current GHCB address - shl rdx, 32 - or rdx, rax - - mov rdi, rdx - xor rax, rax - mov rcx, 0x800 - shr rcx, 3 - rep stosq ; Clear the GHCB - - mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD - mov [rdx + 0x390], rax - mov rax, 114 ; Set SwExitCode valid bit - bts [rdx + 0x3f0], rax - inc rax ; Set SwExitInfo1 valid bit - bts [rdx + 0x3f0], rax - inc rax ; Set SwExitInfo2 valid bit - bts [rdx + 0x3f0], rax - - pop rdx - pop rcx - -NoSevEs: - cli ; Disable interrupt before switching to 3= 2-bit mode - mov rax, [rsp + 40] ; CountTofinish - lock dec dword [rax] ; (*CountTofinish)-- - - mov r10, [rsp + 48] ; Pm16CodeSegment - mov rax, [rsp + 56] ; SevEsAPJumpTable - mov rbx, [rsp + 64] ; WakeupBuffer - mov rsp, r9 ; TopOfApStack - - push rax ; Save SevEsAPJumpTable - push rbx ; Save WakeupBuffer - push r10 ; Save Pm16CodeSegment - push rcx ; Save MwaitSupport - push rdx ; Save ApTargetCState - - lea rax, [PmEntry] ; rax <- The start address of transition = code - - push r8 - push rax - - ; - ; Clear R8 - R15, for reset, before going into 32-bit mode - ; - xor r8, r8 - xor r9, r9 - xor r10, r10 - xor r11, r11 - xor r12, r12 - xor r13, r13 - xor r14, r14 - xor r15, r15 - - ; - ; Far return into 32-bit mode - ; - retfq - -BITS 32 -PmEntry: - mov eax, cr0 - btr eax, 31 ; Clear CR0.PG - mov cr0, eax ; Disable paging and caches - - mov ecx, 0xc0000080 - rdmsr - and ah, ~ 1 ; Clear LME - wrmsr - mov eax, cr4 - and al, ~ (1 << 5) ; Clear PAE - mov cr4, eax - - pop edx - add esp, 4 - pop ecx, - add esp, 4 - -MwaitCheck: - cmp cl, 1 ; Check mwait-monitor support - jnz HltLoop - mov ebx, edx ; Save C-State to ebx -MwaitLoop: - cli - mov eax, esp ; Set Monitor Address - xor ecx, ecx ; ecx =3D 0 - xor edx, edx ; edx =3D 0 - monitor - mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] - shl eax, 4 - mwait - jmp MwaitLoop - -HltLoop: - pop edx ; PM16CodeSegment - add esp, 4 - pop ebx ; WakeupBuffer - add esp, 4 - pop eax ; SevEsAPJumpTable - add esp, 4 - cmp eax, 0 ; Check for SEV-ES - je DoHlt - - cli - ; - ; SEV-ES is enabled, use VMGEXIT (GHCB information already - ; set by caller) - ; -BITS 64 - rep vmmcall -BITS 32 - - ; - ; Back from VMGEXIT AP_HLT_LOOP - ; Push the FLAGS/CS/IP values to use - ; - push word 0x0002 ; EFLAGS - xor ecx, ecx - mov cx, [eax + 2] ; CS - push cx - mov cx, [eax] ; IP - push cx - push word 0x0000 ; For alignment, will be discarded - - push edx - push ebx - - mov edx, esi ; Restore RDX reset value - - retf - -DoHlt: - cli - hlt - jmp DoHlt - -BITS 64 -AsmRelocateApLoopEnd: =20 ;-------------------------------------------------------------------------= ------------ ; AsmGetAddressMap (&AddressMap); --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100459): https://edk2.groups.io/g/devel/message/100459 Mute This Topic: https://groups.io/mt/97188906/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100460+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100460+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1677175582; cv=none; d=zohomail.com; s=zohoarc; b=KKP0zGuivZ7V+SDIEu2Ez0yeC2l+Fslb9E/ckp42g43BVy2Nq+cwLijTntyx9Ak7zmgTvRDbj6unx/0GfI2enM+OShZ5HFHFeKuejYRPtvplXmxb54hckVbxVz62NzTRnzl3ixByI9pqHXlK1E/LkvChrmdoRWfoMuHWsGUfheA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677175582; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=SO9HiwADFf7FRGIdmVgOugSVOPpV2oomE+YgX0EQ9do=; b=F5Gs9ZwWIUCExQfhXU/Ve+DGfJ548YB6yLlNWYTZc67ylMlFg8TEkp6znYt8FZ5fsmBwEoGGOGxwZhspk9EH4xj+5M3nlN3TBKfvIq2VLFnyzAq3+VOcv7njS3EMZwws1i8F5nYKKNgOVfac3GW9VTHbyeaQFlMnll3TtsALYz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100460+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1677175582206803.7832001902324; Thu, 23 Feb 2023 10:06:22 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2a2WYY1788612xTU9dDfjA58; Thu, 23 Feb 2023 10:06:21 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.18315.1677175578044889092 for ; Thu, 23 Feb 2023 10:06:21 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="333288079" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="333288079" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:00 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="918106859" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="918106859" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.166]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:05:58 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [Patch V3 2/6] UefiCpuPkg: Duplicate AsmRelocateApLoopAmd. Date: Fri, 24 Feb 2023 02:05:31 +0800 Message-Id: <20230223180535.10383-3-yuanhao.xie@intel.com> In-Reply-To: <20230223180535.10383-1-yuanhao.xie@intel.com> References: <20230223180535.10383-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: afwpZaIFZcx3NywoZCVFyDNsx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677175581; bh=nBAw8EWYho8/ElRnlN0SnhX7ldY7aUA9s80IoSxRIY8=; h=Cc:Date:From:Reply-To:Subject:To; b=kqMWfkUKO21IkgmEcfeBCZE8GcrW9kl33lZWtBGPOCP+/9jfu4nfgc+ymm8zLdyM3DM bXEWPf9nTuTctQY/IvyHQpQLA3rmJV/vP120wstWa2I3XyRqmW5ETDscvU3lY+t0ncu7e GyummhuYVicI5SfpovVzpzN4p8fxN62CMy8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677175583413100009 Content-Type: text/plain; charset="utf-8" Duplicate AsmRelocateApLoopAmd for non-SEV-ES enabled processors. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie Test-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 68 ++++++++++++++++++++++= ++++++++++++++++++++++------------------------ UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 22 ++++++++++++---------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 31 ++++++++++++++++++++++= +++++++-- UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 33 +++++++++++++++++-----= ----------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 171 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 273 insertions(+), 52 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index a84e9e33ba..dd935a79d3 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -1,7 +1,7 @@ /** @file MP initialize support functions for DXE phase. =20 - Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -378,32 +378,44 @@ RelocateApLoop ( IN OUT VOID *Buffer ) { - CPU_MP_DATA *CpuMpData; - BOOLEAN MwaitSupport; - ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; - UINTN ProcessorNumber; - UINTN StackStart; + CPU_MP_DATA *CpuMpData; + BOOLEAN MwaitSupport; + ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; + ASM_RELOCATE_AP_LOOP_AMDSEV AsmRelocateApLoopFuncAmdSev; + UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); if (CpuMpData->UseSevEsAPMethod) { - StackStart =3D CpuMpData->SevEsAPResetStackStart; + StackStart =3D CpuMpData->SevEsAPResetStackStart; + AsmRelocateApLoopFuncAmdSev =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReserved= ApLoopFunc; + AsmRelocateApLoopFuncAmdSev ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } else { - StackStart =3D mReservedTopOfApStack; + StackStart =3D mReservedTopOfApStack; + AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoop= Func; + AsmRelocateApLoopFunc ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } =20 - AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFu= nc; - AsmRelocateApLoopFunc ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); // // It should never reach here // @@ -582,11 +594,19 @@ InitMpGlobalData ( =20 mReservedTopOfApStack =3D (UINTN)Address + ApSafeBufferSize; ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddress, - CpuMpData->AddressMap.RelocateApLoopFuncSize - ); + if (CpuMpData->UseSevEsAPMethod) { + CopyMem ( + mReservedApLoopFunc, + CpuMpData->AddressMap.RelocateApLoopFuncAddressAmdSev, + CpuMpData->AddressMap.RelocateApLoopFuncSizeAmdSev + ); + } else { + CopyMem ( + mReservedApLoopFunc, + CpuMpData->AddressMap.RelocateApLoopFuncAddress, + CpuMpData->AddressMap.RelocateApLoopFuncSize + ); + } =20 Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/Mp= InitLib/MpEqu.inc index ebadcc6fb3..6730f2f411 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -21,15 +21,17 @@ CPU_SWITCH_STATE_LOADED equ 2 ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP ; struc MP_ASSEMBLY_ADDRESS_MAP - .RendezvousFunnelAddress CTYPE_UINTN 1 - .ModeEntryOffset CTYPE_UINTN 1 - .RendezvousFunnelSize CTYPE_UINTN 1 - .RelocateApLoopFuncAddress CTYPE_UINTN 1 - .RelocateApLoopFuncSize CTYPE_UINTN 1 - .ModeTransitionOffset CTYPE_UINTN 1 - .SwitchToRealNoNxOffset CTYPE_UINTN 1 - .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 - .SwitchToRealPM16ModeSize CTYPE_UINTN 1 + .RendezvousFunnelAddress CTYPE_UINTN 1 + .ModeEntryOffset CTYPE_UINTN 1 + .RendezvousFunnelSize CTYPE_UINTN 1 + .RelocateApLoopFuncAddress CTYPE_UINTN 1 + .RelocateApLoopFuncSize CTYPE_UINTN 1 + .RelocateApLoopFuncAddressAmdSev CTYPE_UINTN 1 + .RelocateApLoopFuncSizeAmdSev CTYPE_UINTN 1 + .ModeTransitionOffset CTYPE_UINTN 1 + .SwitchToRealNoNxOffset CTYPE_UINTN 1 + .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 + .SwitchToRealPM16ModeSize CTYPE_UINTN 1 endstruc =20 ; diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index f5086e497e..5011533302 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -1,7 +1,7 @@ /** @file Common header file for MP Initialize Library. =20 - Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -179,6 +179,8 @@ typedef struct { UINTN RendezvousFunnelSize; UINT8 *RelocateApLoopFuncAddress; UINTN RelocateApLoopFuncSize; + UINT8 *RelocateApLoopFuncAddressAmdSev; + UINTN RelocateApLoopFuncSizeAmdSev; UINTN ModeTransitionOffset; UINTN SwitchToRealNoNxOffset; UINTN SwitchToRealPM16ModeOffset; @@ -311,7 +313,7 @@ typedef struct { =20 #define AP_SAFE_STACK_SIZE 128 #define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE - +STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) =3D=3D 0, = "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT"); #pragma pack(1) =20 typedef struct { @@ -373,6 +375,31 @@ typedef IN UINTN WakeupBuffer ); =20 +/** + Assembly code to place AP into safe loop mode for Amd processors with Se= v enabled. + Place AP into targeted C-State if MONITOR is supported, otherwise + place AP into hlt state. + Place AP in protected mode if the current is long mode. Due to AP maybe + wakeup by some hardware event. It could avoid accessing page table that + may not available during booting to OS. + @param[in] MwaitSupport TRUE indicates MONITOR is supported. + FALSE indicates MONITOR is not supported. + @param[in] ApTargetCState Target C-State value. + @param[in] PmCodeSegment Protected mode code segment value. +**/ +typedef + VOID +(EFIAPI *ASM_RELOCATE_AP_LOOP_AMDSEV)( + IN BOOLEAN MwaitSupport, + IN UINTN ApTargetCState, + IN UINTN PmCodeSegment, + IN UINTN TopOfApStack, + IN UINTN NumberToFinish, + IN UINTN Pm16CodeSegment, + IN UINTN SevEsAPJumpTable, + IN UINTN WakeupBuffer + ); + /** Assembly code to get starting address and size of the rendezvous entry f= or APs. Information for fixing a jump instruction in the code is also returned. diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Libr= ary/MpInitLib/X64/AmdSev.nasm index c1e8a045a4..6b48913306 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -347,12 +347,13 @@ PM16Mode: =20 SwitchToRealProcEnd: ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +; AsmRelocateApLoopAmdSev (MwaitSupport, ApTargetCState, PmCodeSegment, T= opOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer= ); ;-------------------------------------------------------------------------= ------------ -AsmRelocateApLoopStart: + +AsmRelocateApLoopStartAmdSev: BITS 64 cmp qword [rsp + 56], 0 ; SevEsAPJumpTable - je NoSevEs + je NoSevEsAmdSev =20 ; ; Perform some SEV-ES related setup before leaving 64-bit mode @@ -397,7 +398,7 @@ BITS 64 pop rdx pop rcx =20 -NoSevEs: +NoSevEsAmdSev: cli ; Disable interrupt before switching to 3= 2-bit mode mov rax, [rsp + 40] ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- @@ -413,7 +414,7 @@ NoSevEs: push rcx ; Save MwaitSupport push rdx ; Save ApTargetCState =20 - lea rax, [PmEntry] ; rax <- The start address of transition = code + lea rax, [PmEntryAmdSev] ; rax <- The start address of trans= ition code =20 push r8 push rax @@ -433,10 +434,10 @@ NoSevEs: ; ; Far return into 32-bit mode ; - retfq +o64 retf =20 BITS 32 -PmEntry: +PmEntryAmdSev: mov eax, cr0 btr eax, 31 ; Clear CR0.PG mov cr0, eax ; Disable paging and caches @@ -454,11 +455,11 @@ PmEntry: pop ecx, add esp, 4 =20 -MwaitCheck: +MwaitCheckAmdSev: cmp cl, 1 ; Check mwait-monitor support - jnz HltLoop + jnz HltLoopAmdSev mov ebx, edx ; Save C-State to ebx -MwaitLoop: +MwaitLoopAmdSev: cli mov eax, esp ; Set Monitor Address xor ecx, ecx ; ecx =3D 0 @@ -467,9 +468,9 @@ MwaitLoop: mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] shl eax, 4 mwait - jmp MwaitLoop + jmp MwaitLoopAmdSev =20 -HltLoop: +HltLoopAmdSev: pop edx ; PM16CodeSegment add esp, 4 pop ebx ; WakeupBuffer @@ -477,7 +478,7 @@ HltLoop: pop eax ; SevEsAPJumpTable add esp, 4 cmp eax, 0 ; Check for SEV-ES - je DoHlt + je DoHltAmdSev =20 cli ; @@ -507,10 +508,10 @@ BITS 32 =20 retf =20 -DoHlt: +DoHltAmdSev: cli hlt - jmp DoHlt + jmp DoHltAmdSev =20 BITS 64 -AsmRelocateApLoopEnd: +AsmRelocateApLoopEndAmdSev: diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index eb42bbff96..d36f8ba06d 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -278,6 +278,174 @@ CProcedureInvoke: =20 RendezvousFunnelProcEnd: =20 +;-------------------------------------------------------------------------= ------------ +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +;-------------------------------------------------------------------------= ------------ +AsmRelocateApLoopStart: +BITS 64 + cmp qword [rsp + 56], 0 ; SevEsAPJumpTable + je NoSevEs + + ; + ; Perform some SEV-ES related setup before leaving 64-bit mode + ; + push rcx + push rdx + + ; + ; Get the RDX reset value using CPUID + ; + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for RDX + + ; + ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call + ; - Must be done while in 64-bit long mode so that writes to + ; the GHCB memory will be unencrypted. + ; - No NAE events can be generated once this is set otherwise + ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. + ; + mov rcx, 0xc0010130 + rdmsr ; Retrieve current GHCB address + shl rdx, 32 + or rdx, rax + + mov rdi, rdx + xor rax, rax + mov rcx, 0x800 + shr rcx, 3 + rep stosq ; Clear the GHCB + + mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD + mov [rdx + 0x390], rax + mov rax, 114 ; Set SwExitCode valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo1 valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo2 valid bit + bts [rdx + 0x3f0], rax + + pop rdx + pop rcx + +NoSevEs: + cli ; Disable interrupt before switching to 3= 2-bit mode + mov rax, [rsp + 40] ; CountTofinish + lock dec dword [rax] ; (*CountTofinish)-- + + mov r10, [rsp + 48] ; Pm16CodeSegment + mov rax, [rsp + 56] ; SevEsAPJumpTable + mov rbx, [rsp + 64] ; WakeupBuffer + mov rsp, r9 ; TopOfApStack + + push rax ; Save SevEsAPJumpTable + push rbx ; Save WakeupBuffer + push r10 ; Save Pm16CodeSegment + push rcx ; Save MwaitSupport + push rdx ; Save ApTargetCState + + lea rax, [PmEntry] ; rax <- The start address of transition = code + + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; + retfq + +BITS 32 +PmEntry: + mov eax, cr0 + btr eax, 31 ; Clear CR0.PG + mov cr0, eax ; Disable paging and caches + + mov ecx, 0xc0000080 + rdmsr + and ah, ~ 1 ; Clear LME + wrmsr + mov eax, cr4 + and al, ~ (1 << 5) ; Clear PAE + mov cr4, eax + + pop edx + add esp, 4 + pop ecx, + add esp, 4 + +MwaitCheck: + cmp cl, 1 ; Check mwait-monitor support + jnz HltLoop + mov ebx, edx ; Save C-State to ebx +MwaitLoop: + cli + mov eax, esp ; Set Monitor Address + xor ecx, ecx ; ecx =3D 0 + xor edx, edx ; edx =3D 0 + monitor + mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] + shl eax, 4 + mwait + jmp MwaitLoop + +HltLoop: + pop edx ; PM16CodeSegment + add esp, 4 + pop ebx ; WakeupBuffer + add esp, 4 + pop eax ; SevEsAPJumpTable + add esp, 4 + cmp eax, 0 ; Check for SEV-ES + je DoHlt + + cli + ; + ; SEV-ES is enabled, use VMGEXIT (GHCB information already + ; set by caller) + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Back from VMGEXIT AP_HLT_LOOP + ; Push the FLAGS/CS/IP values to use + ; + push word 0x0002 ; EFLAGS + xor ecx, ecx + mov cx, [eax + 2] ; CS + push cx + mov cx, [eax] ; IP + push cx + push word 0x0000 ; For alignment, will be discarded + + push edx + push ebx + + mov edx, esi ; Restore RDX reset value + + retf + +DoHlt: + cli + hlt + jmp DoHlt + +BITS 64 +AsmRelocateApLoopEnd: =20 ;-------------------------------------------------------------------------= ------------ ; AsmGetAddressMap (&AddressMap); @@ -291,6 +459,9 @@ ASM_PFX(AsmGetAddressMap): lea rax, [AsmRelocateApLoopStart] mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], rax mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart + lea rax, [AsmRelocateApLoopStartAmdSev] + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= essAmdSev], rax + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= AmdSev], AsmRelocateApLoopEndAmdSev - AsmRelocateApLoopStartAmdSev mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], PM16Mode - RendezvousFunnelProcStart --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100460): https://edk2.groups.io/g/devel/message/100460 Mute This Topic: https://groups.io/mt/97188907/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100461+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100461+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1677175583; cv=none; d=zohomail.com; s=zohoarc; b=NJhXzRMJfld6h6zsSFOLWWUvjfkIG0gRikYRoll+jKx89Ft6EO4m8fOK49YTNehPbtDAJhnVEOqtpxC1hqalRYTbmDRA/3/tpVZbr9qucqjeZLUZRXL5J/YlJziO5voGG7rFNNC5ixrEHGpG8o3mllTczHb8naMKIcoxTmEwDbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677175583; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Dk0ZhWk4qsOqS1FmQR1rGOUqpys38rlXN0+z7D6JkjY=; b=lTovv8WScbDJoK0abB/Pw+jK5S+aqyYG2YQ8SRSzSp8h6G6eAMh+0KkYs7PzgdJhHlO6DdidBSW5ZDpypqraj+sMKDJhHi0hmr9yxjiUXcY5QhNPgRzQKBUq37jf4PUmM0SoDOfr/LhRqq0vLPVBVXifgxidrmUwcX7KiqeeXkQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100461+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1677175583781936.4819418779128; Thu, 23 Feb 2023 10:06:23 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id d687YY1788612x2s9PHzvxMk; Thu, 23 Feb 2023 10:06:23 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.18315.1677175578044889092 for ; Thu, 23 Feb 2023 10:06:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="333288092" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="333288092" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:02 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="918106899" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="918106899" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.166]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:01 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [Patch V3 3/6] UefiCpuPkg: Contiguous memory allocation and code clean-up. Date: Fri, 24 Feb 2023 02:05:32 +0800 Message-Id: <20230223180535.10383-4-yuanhao.xie@intel.com> In-Reply-To: <20230223180535.10383-1-yuanhao.xie@intel.com> References: <20230223180535.10383-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: p3oBpNz7uHtsolt3NRYlOHbbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677175583; bh=SUNwiM8WsQPpbOZTIzvxIVqvcT+7l+4uYxVACEETeBo=; h=Cc:Date:From:Reply-To:Subject:To; b=rT5ssfPX/r3Fj1msI6r0EQp1AKRjiSA6aAa7Cuh+0MYlm+uEnujkgXrl73/ZUgyNVfy MzrdSKO9Paccx1QwDO2i5yJGPs47zSh2ena6Oo0kMVsYeA1LJQ12H50yLaQwRE8AUuK7z buYlut+DHRRDJmaErWyVawpBwE2pV28NZ2c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677175585372100013 Content-Type: text/plain; charset="utf-8" This patch includes the code refactoring to eliminate the duplication, non-descriptive variable, etc. The memory is calculated taking into account the size difference of RelocateApLoopFunc under different cases. Allocate the memory for stacks and APs loop at contiguous address. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie Test-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 157 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++------------------------------= ------------------------------------------------------ UefiCpuPkg/Library/MpInitLib/MpLib.h | 6 ++++++ 2 files changed, 79 insertions(+), 84 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index dd935a79d3..c095ee9f13 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -20,14 +20,15 @@ =20 #define AP_SAFE_STACK_SIZE 128 =20 -CPU_MP_DATA *mCpuMpData =3D NULL; -EFI_EVENT mCheckAllApsEvent =3D NULL; -EFI_EVENT mMpInitExitBootServicesEvent =3D NULL; -EFI_EVENT mLegacyBootEvent =3D NULL; -volatile BOOLEAN mStopCheckAllApsStatus =3D TRUE; -VOID *mReservedApLoopFunc =3D NULL; -UINTN mReservedTopOfApStack; -volatile UINT32 mNumberToFinish =3D 0; +CPU_MP_DATA *mCpuMpData =3D NULL; +EFI_EVENT mCheckAllApsEvent =3D NULL; +EFI_EVENT mMpInitExitBootServicesEvent =3D NULL; +EFI_EVENT mLegacyBootEvent =3D NULL; +volatile BOOLEAN mStopCheckAllApsStatus =3D TRUE; +UINTN mReservedTopOfApStack; +volatile UINT32 mNumberToFinish =3D 0; +RELOCATE_AP_LOOP_ENTRY mReservedApLoop; + =20 // // Begin wakeup buffer allocation below 0x88000 @@ -380,8 +381,6 @@ RelocateApLoop ( { CPU_MP_DATA *CpuMpData; BOOLEAN MwaitSupport; - ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; - ASM_RELOCATE_AP_LOOP_AMDSEV AsmRelocateApLoopFuncAmdSev; UINTN ProcessorNumber; UINTN StackStart; =20 @@ -389,31 +388,29 @@ RelocateApLoop ( CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); if (CpuMpData->UseSevEsAPMethod) { - StackStart =3D CpuMpData->SevEsAPResetStackStart; - AsmRelocateApLoopFuncAmdSev =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReserved= ApLoopFunc; - AsmRelocateApLoopFuncAmdSev ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); + StackStart =3D CpuMpData->SevEsAPResetStackStart; + mReservedApLoop.AmdSevEntry ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } else { - StackStart =3D mReservedTopOfApStack; - AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoop= Func; - AsmRelocateApLoopFunc ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); + StackStart =3D mReservedTopOfApStack; + mReservedApLoop.GenericEntry ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } =20 // @@ -477,12 +474,16 @@ InitMpGlobalData ( ) { EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Address; - UINTN ApSafeBufferSize; + MP_ASSEMBLY_ADDRESS_MAP *AddressMap; + UINTN StackPages; + UINTN FuncPages; UINTN Index; EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc; UINTN StackBase; CPU_INFO_IN_HOB *CpuInfoInHob; + EFI_PHYSICAL_ADDRESS Address; + UINT8 *ApLoopFunc; + UINTN ApLoopFuncSize; =20 SaveCpuMpData (CpuMpData); =20 @@ -537,6 +538,15 @@ InitMpGlobalData ( } } =20 + AddressMap =3D &CpuMpData->AddressMap; + if (CpuMpData->UseSevEsAPMethod) { + ApLoopFunc =3D AddressMap->RelocateApLoopFuncAddressAmdSev; + ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSizeAmdSev; + } else { + ApLoopFunc =3D AddressMap->RelocateApLoopFuncAddress; + ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSize; + } + // // Avoid APs access invalid buffer data which allocated by BootServices, // so we will allocate reserved data for AP loop code. We also need to @@ -545,26 +555,31 @@ InitMpGlobalData ( // Allocating it in advance since memory services are not available in // Exit Boot Services callback function. // - ApSafeBufferSize =3D EFI_PAGES_TO_SIZE ( - EFI_SIZE_TO_PAGES ( - CpuMpData->AddressMap.RelocateApLoopFuncSize - ) - ); - Address =3D BASE_4GB - 1; - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiReservedMemoryType, - EFI_SIZE_TO_PAGES (ApSafeBufferSize), - &Address - ); - ASSERT_EFI_ERROR (Status); + // +------------+ (TopOfApStack) + // | Stack * N | + // +------------+ + // | Padding | + // +------------+ + // | Ap Loop | + // +------------+ (low address ) + // =20 - mReservedApLoopFunc =3D (VOID *)(UINTN)Address; - ASSERT (mReservedApLoopFunc !=3D NULL); + Address =3D BASE_4GB - 1; + StackPages =3D EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * AP_SAFE_STACK_SI= ZE); + FuncPages =3D EFI_SIZE_TO_PAGES (ApLoopFuncSize); =20 - // - // Make sure that the buffer memory is executable if NX protection is en= abled - // for EfiReservedMemoryType. + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + StackPages+FuncPages, + &Address + ); + ASSERT_EFI_ERROR (Status); + // If a memory range has the EFI_MEMORY_XP attribute, OS loader + // may set the IA32_EFER.NXE (No-eXecution Enable) bit in IA32_EFER MSR, + // then set the XD (eXecution Disable) bit in the CPU PAE page table. + // Here is to make sure that the memory is executable if NX protection is + // enabled for EfiReservedMemoryType. // // TODO: Check EFI_MEMORY_XP bit set or not once it's available in DXE G= CD // service. @@ -573,41 +588,15 @@ InitMpGlobalData ( if (!EFI_ERROR (Status)) { gDS->SetMemorySpaceAttributes ( Address, - ApSafeBufferSize, + ALIGN_VALUE (ApLoopFuncSize, EFI_PAGE_SIZE), MemDesc.Attributes & (~EFI_MEMORY_XP) ); } =20 - ApSafeBufferSize =3D EFI_PAGES_TO_SIZE ( - EFI_SIZE_TO_PAGES ( - CpuMpData->CpuCount * AP_SAFE_STACK_SIZE - ) - ); - Address =3D BASE_4GB - 1; - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiReservedMemoryType, - EFI_SIZE_TO_PAGES (ApSafeBufferSize), - &Address - ); - ASSERT_EFI_ERROR (Status); - - mReservedTopOfApStack =3D (UINTN)Address + ApSafeBufferSize; + mReservedTopOfApStack =3D (UINTN)Address + EFI_PAGES_TO_SIZE (StackPages= +FuncPages); ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); - if (CpuMpData->UseSevEsAPMethod) { - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddressAmdSev, - CpuMpData->AddressMap.RelocateApLoopFuncSizeAmdSev - ); - } else { - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddress, - CpuMpData->AddressMap.RelocateApLoopFuncSize - ); - } - + mReservedApLoop.Data =3D (VOID *)(UINTN)Address; + CopyMem (mReservedApLoop.Data, ApLoopFunc, ApLoopFuncSize); Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY, diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 5011533302..f0daa2c5af 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -400,6 +400,12 @@ typedef IN UINTN WakeupBuffer ); =20 +typedef union { + VOID *Data; + ASM_RELOCATE_AP_LOOP_AMDSEV AmdSevEntry; // 64-bit AMD Sev processors + ASM_RELOCATE_AP_LOOP GenericEntry; // Intel processors (32-bit= or 64-bit), 32-bit AMD processors, or AMD non-Sev processors +} RELOCATE_AP_LOOP_ENTRY; + /** Assembly code to get starting address and size of the rendezvous entry f= or APs. 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View/Reply Online (#100461): https://edk2.groups.io/g/devel/message/100461 Mute This Topic: https://groups.io/mt/97188908/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100462+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100462+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1677175584; cv=none; d=zohomail.com; s=zohoarc; b=ZhJlnGev68WKbDq5wbVUlVCR9wMKPZjVkmi8ud48kwmHevgAQ2LsxzIlrQ6FeLB+e1xSQclFNnQno055u94nNAFX3V6MlZzxDhnUSmCzBf1v5IYA2TJOepFQoyEFxeRxNaFiV0FMod3FK8l/pMBVjqJXi9na5VjD0YF5Oe7ATmk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677175584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=gGP9FBckDF7zepQkcQC3IYxvJP2JOlN35+oD1cFwtr0=; b=FEE3O3y4sDfSLq2Ef5xAYbVYeEuBLoWIJKYi1tl3OJP0Xy6sFRTnnvC5EM9a8+znPJxMhwxpunvmAF3R72F31f2MhrZ3bCMVy0/+OQ02kXGA6UGa1YEHucVfyDg03Qb74mm67MFdbjlm/kzRJNzadvpkcQ3Hvl+0YNUoIBgZ4MQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100462+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1677175584420763.6489935210362; Thu, 23 Feb 2023 10:06:24 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id DjnNYY1788612xC2iKKxwYYH; Thu, 23 Feb 2023 10:06:24 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.18315.1677175578044889092 for ; Thu, 23 Feb 2023 10:06:23 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="333288112" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="333288112" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="918106953" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="918106953" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.166]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:03 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 4/6] OvmfPkg: Add CpuPageTableLib required by MpInitLib. Date: Fri, 24 Feb 2023 02:05:33 +0800 Message-Id: <20230223180535.10383-5-yuanhao.xie@intel.com> In-Reply-To: <20230223180535.10383-1-yuanhao.xie@intel.com> References: <20230223180535.10383-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: xbWdsREXb0V6obYNUVQhF2qqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677175584; bh=NNVrXQXP/oKpgQrVopha8u6RBMwyQTVJF3GHoZcCsFk=; h=Cc:Date:From:Reply-To:Subject:To; b=V483Kh3b4D2X6Q7Edjch4irRiiZYchVhZgSD6obkoUtFe3N5yvulS2D0JQHVVpvkpqO ygJbZ/BUpnfGFeEUdbOZBG4hlYyDhncnQUxFULW+5jvN/zl65kELdWzGjy8ETZ6wfqeKK Ss02iH0qiPFJARnV9UC62a5QPBrUNbRnNzM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677175585377100014 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by MpInitLib in OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Yuanhao Xie --- OvmfPkg/AmdSev/AmdSevX64.dsc | 3 ++- OvmfPkg/CloudHv/CloudHvX64.dsc | 3 ++- OvmfPkg/IntelTdx/IntelTdxX64.dsc | 4 +++- OvmfPkg/Microvm/MicrovmX64.dsc | 3 ++- OvmfPkg/OvmfPkgIa32X64.dsc | 3 ++- OvmfPkg/OvmfPkgX64.dsc | 4 +++- OvmfPkg/OvmfXen.dsc | 3 ++- 7 files changed, 16 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 1cebd6b4bc..f0c4dc2310 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -3,7 +3,7 @@ # virtual machine remote attestation and secret injection # # Copyright (c) 2020 James Bottomley, IBM Corporation. -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -353,6 +353,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index fda7d2b9e5..327f53ff3c 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -404,6 +404,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX6= 4.dsc index 95b9594ddc..d093660283 100644 --- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc +++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -320,6 +320,7 @@ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxDxeLib.inf PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf @@ -590,6 +591,7 @@ # Directly use DxeMpInitLib. It depends on DxeMpInitLibMpDepLib which # checks the Protocol of gEfiMpInitLibMpDepProtocolGuid. # + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.i= nf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NULL|OvmfPkg/Library/MpInitLibDepLib/DxeMpInitLibMpDepLib.inf } diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 0d65d21e65..76fc548650 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -403,6 +403,7 @@ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 6b539814bd..51db692b10 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -414,6 +414,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index e3c64456df..04d50704c7 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -435,6 +435,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf @@ -826,6 +827,7 @@ # Directly use DxeMpInitLib. It depends on DxeMpInitLibMpDepLib which # checks the Protocol of gEfiMpInitLibMpDepProtocolGuid. # + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.i= nf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NULL|OvmfPkg/Library/MpInitLibDepLib/DxeMpInitLibMpDepLib.inf } diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index c328987e84..f1f02d969f 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) 2019, Citrix Systems, Inc. # Copyright (c) Microsoft Corporation. @@ -339,6 +339,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Date: Fri, 24 Feb 2023 02:05:34 +0800 Message-Id: <20230223180535.10383-6-yuanhao.xie@intel.com> In-Reply-To: <20230223180535.10383-1-yuanhao.xie@intel.com> References: <20230223180535.10383-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: scrSmVAQWoRPFp5ACNnreEp3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677175586; bh=8Dk4wZdk+hTFpaQ4I8RTM4egB7xQIKrmuL3E3ou36rg=; h=Cc:Date:From:Reply-To:Subject:To; b=aZDZBgz+VZSUHH3ALmvUX88MDnpriJCsHi6Pjf+8zWNV4qb54spADapFDeajn+UMAB5 X+hiwq9FTy0+J7OQX97jGld4wVU7cjlNZoqUHnuuImgtPr5S+eSrgQEfLfVW4DY3mMVkb zQvUz6mZoLOX9KeTx0IInX7+h3wR9LlO8MI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677175587344100021 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by MpInitLib in UefiPayloadPkg. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie --- UefiPayloadPkg/UefiPayloadPkg.dsc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index 2dbd875f37..8cbbbe9a05 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -3,7 +3,7 @@ # # Provides drivers and definitions to create uefi payload for bootloaders. # -# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) Microsoft Corporation. # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -340,6 +340,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf !if $(PERFORMANCE_MEASUREMENT_ENABLE) PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100463): https://edk2.groups.io/g/devel/message/100463 Mute This Topic: https://groups.io/mt/97188910/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100464+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100464+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1677175588; cv=none; d=zohomail.com; s=zohoarc; b=KPs2gpIS/T83JUPP7nreKrqVCNwa+JkOiHsTjCv3SOyW1gM9o01jStFzm7lGofVwL/Kdy1WAewa1cZKILGtCgf6PuUM6eUMnoQklLZoFIYzsJ+IB+u76HjObVwHpGq/MFiMulnFSfntCQeteeUUPUd/uB3Q7vRmPaWFeLw5ho8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677175588; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5dBoYaPUtgm6IZMbvH+P+AAbVRwSVogxSCMtOIZtVfw=; b=VRsMBhPDrnhW4Dp97t2utPMj/wR5rw32E5BLYorRyHJMWitA4/XckKK6F8YC8iPKBNPAx2EtukDZza9lb4/DST9D4GhhDUMLLkNgYiD3/DKHKP8JIbYxEAV3lQTssknJ5UGUV8ig9Qzqz3Do+I4DO6rHaynWj7ihM57A6sO3BoY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100464+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1677175588140682.8691243611249; Thu, 23 Feb 2023 10:06:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id YmQ1YY1788612xdwF7JYnogb; Thu, 23 Feb 2023 10:06:27 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.18315.1677175578044889092 for ; Thu, 23 Feb 2023 10:06:27 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="333288156" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="333288156" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:10 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="918107079" X-IronPort-AV: E=Sophos;i="5.97,322,1669104000"; d="scan'208";a="918107079" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.166]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 10:06:08 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [Patch V3 6/6] UefiCpuPkg: Put APs in 64 bit mode before handoff to OS. Date: Fri, 24 Feb 2023 02:05:35 +0800 Message-Id: <20230223180535.10383-7-yuanhao.xie@intel.com> In-Reply-To: <20230223180535.10383-1-yuanhao.xie@intel.com> References: <20230223180535.10383-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: wcwUw3uLlfH5uqgQobs10dzmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1677175587; bh=H00n6ZdEwXUKvdFFmKbmjgsAkA1dWlyVDc1LXWyWrQI=; h=Cc:Date:From:Reply-To:Subject:To; b=FWyQcOeTFVrOy4LyJFe2HXffbwAQXC+FAa5V/0bSVu+4UlvQ6FzH7xtB0/rkJUQi2w+ eEEN8+wH+Ra4skbLllNrNvkscbxu8CWeQqejLguzdhuX/Rr80z1zXFiCvufxmmFCrMh8K lAlw/mmOPLfy9WtAg5CzIrepxv4mSccey2w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1677175589379100025 Content-Type: text/plain; charset="utf-8" Only keep 4GB limitation of memory allocation for the case APs still need to be transferred to 32-bit mode before OS. Remove the unused arguments of AsmRelocateApLoopStart, updated the stack offset. Create PageTable for the allocated reserved memory. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie Test-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 6 +++++- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 40 ++++++++++++++++= ++++++++++++++---------- UefiCpuPkg/Library/MpInitLib/Ia32/CreatePageTable.c | 23 ++++++++++++++++= +++++++ UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm | 11 ++++------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 17 +++++++++++++---- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 82 ++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 173 ++++++++++++++++= ++++++++++++---------------------------------------------------------------= ---------------------------------------------------------------------------= ------- UefiCpuPkg/UefiCpuPkg.dsc | 3 ++- 8 files changed, 187 insertions(+), 168 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index cd07de3a3c..4285dd06b4 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -1,7 +1,7 @@ ## @file # MP Initialize Library instance for DXE driver. # -# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -24,10 +24,12 @@ [Sources.IA32] Ia32/AmdSev.c Ia32/MpFuncs.nasm + Ia32/CreatePageTable.c =20 [Sources.X64] X64/AmdSev.c X64/MpFuncs.nasm + X64/CreatePageTable.c =20 [Sources.common] AmdSev.c @@ -56,6 +58,8 @@ PcdLib CcExitLib MicrocodeLib +[LibraryClasses.X64] + CpuPageTableLib =20 [Protocols] gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index c095ee9f13..fef91ecc3b 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -28,7 +28,7 @@ volatile BOOLEAN mStopCheckAllApsStatus =3D = TRUE; UINTN mReservedTopOfApStack; volatile UINT32 mNumberToFinish =3D 0; RELOCATE_AP_LOOP_ENTRY mReservedApLoop; - +UINTN mApPageTable; =20 // // Begin wakeup buffer allocation below 0x88000 @@ -379,15 +379,18 @@ RelocateApLoop ( IN OUT VOID *Buffer ) { - CPU_MP_DATA *CpuMpData; - BOOLEAN MwaitSupport; - UINTN ProcessorNumber; - UINTN StackStart; + CPU_MP_DATA *CpuMpData; + BOOLEAN MwaitSupport; + UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); if (CpuMpData->UseSevEsAPMethod) { + // + // 64-bit AMD processors with SEV-ES + // StackStart =3D CpuMpData->SevEsAPResetStackStart; mReservedApLoop.AmdSevEntry ( MwaitSupport, @@ -400,16 +403,16 @@ RelocateApLoop ( CpuMpData->WakeupBuffer ); } else { + // + // Intel processors (32-bit or 64-bit), 32-bit AMD processors, or 64-b= it AMD processors without SEV-ES + // StackStart =3D mReservedTopOfApStack; mReservedApLoop.GenericEntry ( MwaitSupport, CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer + mApPageTable ); } =20 @@ -540,9 +543,17 @@ InitMpGlobalData ( =20 AddressMap =3D &CpuMpData->AddressMap; if (CpuMpData->UseSevEsAPMethod) { + // + // 64-bit AMD processors with SEV-ES + // + Address =3D BASE_4GB - 1; ApLoopFunc =3D AddressMap->RelocateApLoopFuncAddressAmdSev; ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSizeAmdSev; } else { + // + // Intel processors (32-bit or 64-bit), 32-bit AMD processors, or 64-b= it AMD processors without SEV-ES + // + Address =3D MAX_ADDRESS; ApLoopFunc =3D AddressMap->RelocateApLoopFuncAddress; ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSize; } @@ -564,7 +575,6 @@ InitMpGlobalData ( // +------------+ (low address ) // =20 - Address =3D BASE_4GB - 1; StackPages =3D EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * AP_SAFE_STACK_SI= ZE); FuncPages =3D EFI_SIZE_TO_PAGES (ApLoopFuncSize); =20 @@ -597,6 +607,16 @@ InitMpGlobalData ( ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); mReservedApLoop.Data =3D (VOID *)(UINTN)Address; CopyMem (mReservedApLoop.Data, ApLoopFunc, ApLoopFuncSize); + if (!CpuMpData->UseSevEsAPMethod) { + // + // processors without SEV-ES + // + mApPageTable =3D CreatePageTable ( + (UINTN)Address, + EFI_PAGES_TO_SIZE (StackPages+FuncPages) + ); + } + Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY, diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/CreatePageTable.c b/UefiCpuP= kg/Library/MpInitLib/Ia32/CreatePageTable.c new file mode 100644 index 0000000000..bec9b247c0 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/CreatePageTable.c @@ -0,0 +1,23 @@ +/** @file + Function to create page talbe. + Only create page table for x64, and leave the CreatePageTable empty for = Ia32. + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Only create page table for x64, and leave the CreatePageTable empty for = Ia32. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @return The page table to be created. +**/ +UINTN +CreatePageTable ( + IN UINTN Address, + IN UINTN Length + ) +{ + return 0; +} diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index bfcdbd31c1..c65a825a23 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -219,20 +219,17 @@ SwitchToRealProcEnd: RendezvousFunnelProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); -; -; The last three parameters (Pm16CodeSegment, SevEsAPJumpTable and Wakeup= Buffer) are -; specific to SEV-ES support and are not applicable on IA32. +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, TopOfApStack, CountTof= inish, Cr3); ;-------------------------------------------------------------------------= ------------ AsmRelocateApLoopStart: mov eax, esp - mov esp, [eax + 16] ; TopOfApStack + mov esp, [eax + 12] ; TopOfApStack push dword [eax] ; push return address for stack trace push ebp mov ebp, esp mov ebx, [eax + 8] ; ApTargetCState mov ecx, [eax + 4] ; MwaitSupport - mov eax, [eax + 20] ; CountTofinish + mov eax, [eax + 16] ; CountTofinish lock dec dword [eax] ; (*CountTofinish)-- cmp cl, 1 ; Check mwait-monitor support jnz HltLoop diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index f0daa2c5af..ba7ec5bba3 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -367,12 +367,9 @@ typedef (EFIAPI *ASM_RELOCATE_AP_LOOP)( IN BOOLEAN MwaitSupport, IN UINTN ApTargetCState, - IN UINTN PmCodeSegment, IN UINTN TopOfApStack, IN UINTN NumberToFinish, - IN UINTN Pm16CodeSegment, - IN UINTN SevEsAPJumpTable, - IN UINTN WakeupBuffer + IN UINTN Cr3 ); =20 /** @@ -497,6 +494,18 @@ GetSevEsAPMemory ( VOID ); =20 +/** + Create 1:1 mapping page table in reserved memory to map the specified ad= dress range. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @return The page table to be created. +**/ +UINTN +CreatePageTable ( + IN UINTN Address, + IN UINTN Length + ); + /** This function will be called by BSP to wakeup AP. =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c new file mode 100644 index 0000000000..7cf91ed9c4 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -0,0 +1,82 @@ +/** @file + Function to create page talbe. + Only create page table for x64, and leave the CreatePageTable empty for = Ia32. + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include +#include +#include +#include +#include + +/** + Create 1:1 mapping page table in reserved memory to map the specified ad= dress range. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @return The page table to be created. +**/ +UINTN +CreatePageTable ( + IN UINTN Address, + IN UINTN Length + ) +{ + EFI_STATUS Status; + VOID *PageTableBuffer; + UINTN PageTableBufferSize; + UINTN PageTable; + PAGING_MODE PagingMode; + IA32_CR4 Cr4; + + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + + MapAttribute.Uint64 =3D Address; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + + MapMask.Bits.PageTableBaseAddress =3D 1; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; + + PageTable =3D 0; + PageTableBufferSize =3D 0; + + Cr4.UintN =3D AsmReadCr4 (); + + if (Cr4.Bits.LA57 =3D=3D 1) { + PagingMode =3D Paging5Level; + } else { + PagingMode =3D Paging4Level; + } + + Status =3D PageTableMap ( + &PageTable, + PagingMode, + NULL, + &PageTableBufferSize, + Address, + Length, + &MapAttribute, + &MapMask + ); + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); + + PageTableBuffer =3D AllocateReservedPages (EFI_SIZE_TO_PAGES (PageTableB= ufferSize)); + ASSERT (PageTableBuffer !=3D NULL); + Status =3D PageTableMap ( + &PageTable, + PagingMode, + PageTableBuffer, + &PageTableBufferSize, + Address, + Length, + &MapAttribute, + &MapMask + ); + ASSERT_EFI_ERROR (Status); + return PageTable; +} diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index d36f8ba06d..2bce04d99c 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -279,172 +279,55 @@ CProcedureInvoke: RendezvousFunnelProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, TopOfApStack, CountTof= inish, Cr3); +; This function is called during the finalizaiton of Mp initialization be= fore booting +; to OS, and aim to put Aps either in Mwait or HLT. ;-------------------------------------------------------------------------= ------------ -AsmRelocateApLoopStart: -BITS 64 - cmp qword [rsp + 56], 0 ; SevEsAPJumpTable - je NoSevEs - - ; - ; Perform some SEV-ES related setup before leaving 64-bit mode - ; - push rcx - push rdx - - ; - ; Get the RDX reset value using CPUID - ; - mov rax, 1 - cpuid - mov rsi, rax ; Save off the reset value for RDX - - ; - ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call - ; - Must be done while in 64-bit long mode so that writes to - ; the GHCB memory will be unencrypted. - ; - No NAE events can be generated once this is set otherwise - ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. - ; - mov rcx, 0xc0010130 - rdmsr ; Retrieve current GHCB address - shl rdx, 32 - or rdx, rax - - mov rdi, rdx - xor rax, rax - mov rcx, 0x800 - shr rcx, 3 - rep stosq ; Clear the GHCB - - mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD - mov [rdx + 0x390], rax - mov rax, 114 ; Set SwExitCode valid bit - bts [rdx + 0x3f0], rax - inc rax ; Set SwExitInfo1 valid bit - bts [rdx + 0x3f0], rax - inc rax ; Set SwExitInfo2 valid bit - bts [rdx + 0x3f0], rax +; +----------------+ +; | Cr3 | rsp+40 +; +----------------+ +; | CountTofinish | r9 +; +----------------+ +; | TopOfApStack | r8 +; +----------------+ +; | ApTargetCState | rdx +; +----------------+ +; | MwaitSupport | rcx +; +----------------+ +; | the return | +; +----------------+ low address =20 - pop rdx - pop rcx - -NoSevEs: - cli ; Disable interrupt before switching to 3= 2-bit mode - mov rax, [rsp + 40] ; CountTofinish +AsmRelocateApLoopStart: + mov rax, r9 ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- =20 - mov r10, [rsp + 48] ; Pm16CodeSegment - mov rax, [rsp + 56] ; SevEsAPJumpTable - mov rbx, [rsp + 64] ; WakeupBuffer - mov rsp, r9 ; TopOfApStack - - push rax ; Save SevEsAPJumpTable - push rbx ; Save WakeupBuffer - push r10 ; Save Pm16CodeSegment - push rcx ; Save MwaitSupport - push rdx ; Save ApTargetCState - - lea rax, [PmEntry] ; rax <- The start address of transition = code - - push r8 - push rax - - ; - ; Clear R8 - R15, for reset, before going into 32-bit mode - ; - xor r8, r8 - xor r9, r9 - xor r10, r10 - xor r11, r11 - xor r12, r12 - xor r13, r13 - xor r14, r14 - xor r15, r15 - - ; - ; Far return into 32-bit mode - ; - retfq - -BITS 32 -PmEntry: - mov eax, cr0 - btr eax, 31 ; Clear CR0.PG - mov cr0, eax ; Disable paging and caches - - mov ecx, 0xc0000080 - rdmsr - and ah, ~ 1 ; Clear LME - wrmsr - mov eax, cr4 - and al, ~ (1 << 5) ; Clear PAE - mov cr4, eax - - pop edx - add esp, 4 - pop ecx, - add esp, 4 + mov rax, [rsp + 40] ; Cr3 + ; Do not push on old stack, since old stack is not mapped + ; in the page table pointed by cr3 + mov cr3, rax + mov rsp, r8 ; TopOfApStack =20 MwaitCheck: cmp cl, 1 ; Check mwait-monitor support jnz HltLoop - mov ebx, edx ; Save C-State to ebx + mov rbx, rdx ; Save C-State to ebx + MwaitLoop: cli - mov eax, esp ; Set Monitor Address + mov rax, rsp ; Set Monitor Address xor ecx, ecx ; ecx =3D 0 xor edx, edx ; edx =3D 0 monitor - mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] + mov rax, rbx ; Mwait Cx, Target C-State per eax[7:4] shl eax, 4 mwait jmp MwaitLoop =20 HltLoop: - pop edx ; PM16CodeSegment - add esp, 4 - pop ebx ; WakeupBuffer - add esp, 4 - pop eax ; SevEsAPJumpTable - add esp, 4 - cmp eax, 0 ; Check for SEV-ES - je DoHlt - - cli - ; - ; SEV-ES is enabled, use VMGEXIT (GHCB information already - ; set by caller) - ; -BITS 64 - rep vmmcall -BITS 32 - - ; - ; Back from VMGEXIT AP_HLT_LOOP - ; Push the FLAGS/CS/IP values to use - ; - push word 0x0002 ; EFLAGS - xor ecx, ecx - mov cx, [eax + 2] ; CS - push cx - mov cx, [eax] ; IP - push cx - push word 0x0000 ; For alignment, will be discarded - - push edx - push ebx - - mov edx, esi ; Restore RDX reset value - - retf - -DoHlt: cli hlt - jmp DoHlt + jmp HltLoop =20 -BITS 64 AsmRelocateApLoopEnd: =20 ;-------------------------------------------------------------------------= ------------ diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index a7318d3fe9..105c2e9313 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -1,7 +1,7 @@ ## @file # UefiCpuPkg Package # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -94,6 +94,7 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegi= sterCpuFeaturesLib.inf CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100464): https://edk2.groups.io/g/devel/message/100464 Mute This Topic: https://groups.io/mt/97188911/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-