From nobody Mon Feb 9 13:22:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100354+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100354+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676870450; cv=none; d=zohomail.com; s=zohoarc; b=SSgxlaqYQEDYIpweXn3hOCVeqtqvMKapzSWO2z7hCf0fBz0BnDdgGOziWJGpUBhDZWEefmQnp7qPgnmjaOvhC7IyO7qnvQ7DFTmRycGpsR2yjjLv+g3RQEZr5FIibHp4H1105BrzTkESPyjuN44CqS4QCUVdhStW4CKGt9fUrvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676870450; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=R428ISQzAn2NHLhazqKfy712dYa8P8qP9qdNR+LxrKw=; b=Mj/IO7sPTZfQFiMSemLbETLiAydN2t2n/lxv/im0IyBS5RdQG9DdAVKknZzL2unl49BBigdaS+uoJnZn6fpRyAe1Yxkp0w+PGy8ppGYhxyLwMtZwIgYtao/IKpaXnGp0ZnGEvoNwGoScEMpIdY2xjrVrowzsJPg8UMdVNhqxHUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100354+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676870450066179.21306250913335; Sun, 19 Feb 2023 21:20:50 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id rpZQYY1788612x0W5N0PHvut; Sun, 19 Feb 2023 21:20:49 -0800 X-Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.6790.1676870445058179079 for ; Sun, 19 Feb 2023 21:20:49 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="311957514" X-IronPort-AV: E=Sophos;i="5.97,311,1669104000"; d="scan'208";a="311957514" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2023 21:20:48 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="701556238" X-IronPort-AV: E=Sophos;i="5.97,311,1669104000"; d="scan'208";a="701556238" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.166]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2023 21:20:46 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo , Gerd Hoffmann , Tom Lendacky , Laszlo Ersek Subject: [edk2-devel] [Patch V2 1/5] UefiCpuPkg: Duplicate RelocateApLoop for the processors with SEV-ES. Date: Mon, 20 Feb 2023 13:20:18 +0800 Message-Id: <20230220052022.9290-2-yuanhao.xie@intel.com> In-Reply-To: <20230220052022.9290-1-yuanhao.xie@intel.com> References: <20230220052022.9290-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: FeZuDlh37vd0xFbvrepm758nx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676870449; bh=dqdo4wJvzSNXzyAquUm10/4p1ZzNrB1PjleQjXpVtDY=; h=Cc:Date:From:Reply-To:Subject:To; b=u0Jtl90+KOL4WikRCIqbe4DdFIwxd3T5f7Dntuz0adLvaSySRBvUF0jr+1urRE/2s1i P6jB+boD1WU7bUaR0h51rQ8NrvO6TV4sOMtCYRPgknvmxdX7iIq1v4FxlnnzCcCoIDPvI gfQJ34j5cCumA20GaDER63tlJTxhkyvBIr8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676870451354100001 Content-Type: text/plain; charset="utf-8" The processors with SEV-ES enabled follow the original logic, for the other cases the APs will be put in 64-bit mode before handing off the boot process to the OS. To achieve this purpose, this patch duplicate RelocateApLoop and other related code for the processors with SEV-ES. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Cc: Gerd Hoffmann Cc: Tom Lendacky Cc: Laszlo Ersek Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 68 ++++++++++++++++++++++= ++++++++++++++++++++++------------------------ UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 22 ++++++++++++---------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 30 ++++++++++++++++++++++= +++++++- UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 169 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 5 ++++- 5 files changed, 258 insertions(+), 36 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index a84e9e33ba..dd935a79d3 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -1,7 +1,7 @@ /** @file MP initialize support functions for DXE phase. =20 - Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -378,32 +378,44 @@ RelocateApLoop ( IN OUT VOID *Buffer ) { - CPU_MP_DATA *CpuMpData; - BOOLEAN MwaitSupport; - ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; - UINTN ProcessorNumber; - UINTN StackStart; + CPU_MP_DATA *CpuMpData; + BOOLEAN MwaitSupport; + ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; + ASM_RELOCATE_AP_LOOP_AMDSEV AsmRelocateApLoopFuncAmdSev; + UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); if (CpuMpData->UseSevEsAPMethod) { - StackStart =3D CpuMpData->SevEsAPResetStackStart; + StackStart =3D CpuMpData->SevEsAPResetStackStart; + AsmRelocateApLoopFuncAmdSev =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReserved= ApLoopFunc; + AsmRelocateApLoopFuncAmdSev ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } else { - StackStart =3D mReservedTopOfApStack; + StackStart =3D mReservedTopOfApStack; + AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoop= Func; + AsmRelocateApLoopFunc ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } =20 - AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFu= nc; - AsmRelocateApLoopFunc ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); // // It should never reach here // @@ -582,11 +594,19 @@ InitMpGlobalData ( =20 mReservedTopOfApStack =3D (UINTN)Address + ApSafeBufferSize; ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddress, - CpuMpData->AddressMap.RelocateApLoopFuncSize - ); + if (CpuMpData->UseSevEsAPMethod) { + CopyMem ( + mReservedApLoopFunc, + CpuMpData->AddressMap.RelocateApLoopFuncAddressAmdSev, + CpuMpData->AddressMap.RelocateApLoopFuncSizeAmdSev + ); + } else { + CopyMem ( + mReservedApLoopFunc, + CpuMpData->AddressMap.RelocateApLoopFuncAddress, + CpuMpData->AddressMap.RelocateApLoopFuncSize + ); + } =20 Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/Mp= InitLib/MpEqu.inc index ebadcc6fb3..1472ef2024 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -21,15 +21,17 @@ CPU_SWITCH_STATE_LOADED equ 2 ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP ; struc MP_ASSEMBLY_ADDRESS_MAP - .RendezvousFunnelAddress CTYPE_UINTN 1 - .ModeEntryOffset CTYPE_UINTN 1 - .RendezvousFunnelSize CTYPE_UINTN 1 - .RelocateApLoopFuncAddress CTYPE_UINTN 1 - .RelocateApLoopFuncSize CTYPE_UINTN 1 - .ModeTransitionOffset CTYPE_UINTN 1 - .SwitchToRealNoNxOffset CTYPE_UINTN 1 - .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 - .SwitchToRealPM16ModeSize CTYPE_UINTN 1 + .RendezvousFunnelAddress CTYPE_UINTN 1 + .ModeEntryOffset CTYPE_UINTN 1 + .RendezvousFunnelSize CTYPE_UINTN 1 + .RelocateApLoopFuncAddress CTYPE_UINTN 1 + .RelocateApLoopFuncSize CTYPE_UINTN 1 + .RelocateApLoopFuncAddressAmdSev CTYPE_UINTN 1 + .RelocateApLoopFuncSizeAmdSev CTYPE_UINTN 1 + .ModeTransitionOffset CTYPE_UINTN 1 + .SwitchToRealNoNxOffset CTYPE_UINTN 1 + .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 + .SwitchToRealPM16ModeSize CTYPE_UINTN 1 endstruc =20 ; diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index f5086e497e..fe60084333 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -1,7 +1,7 @@ /** @file Common header file for MP Initialize Library. =20 - Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -179,6 +179,8 @@ typedef struct { UINTN RendezvousFunnelSize; UINT8 *RelocateApLoopFuncAddress; UINTN RelocateApLoopFuncSize; + UINT8 *RelocateApLoopFuncAddressAmdSev; + UINTN RelocateApLoopFuncSizeAmdSev; UINTN ModeTransitionOffset; UINTN SwitchToRealNoNxOffset; UINTN SwitchToRealPM16ModeOffset; @@ -311,6 +313,7 @@ typedef struct { =20 #define AP_SAFE_STACK_SIZE 128 #define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE +STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) =3D=3D 0, = "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT"); =20 #pragma pack(1) =20 @@ -373,6 +376,31 @@ typedef IN UINTN WakeupBuffer ); =20 +/** + Assembly code to place AP into safe loop mode for Amd processors with Se= v enabled. + Place AP into targeted C-State if MONITOR is supported, otherwise + place AP into hlt state. + Place AP in protected mode if the current is long mode. Due to AP maybe + wakeup by some hardware event. It could avoid accessing page table that + may not available during booting to OS. + @param[in] MwaitSupport TRUE indicates MONITOR is supported. + FALSE indicates MONITOR is not supported. + @param[in] ApTargetCState Target C-State value. + @param[in] PmCodeSegment Protected mode code segment value. +**/ +typedef + VOID +(EFIAPI *ASM_RELOCATE_AP_LOOP_AMDSEV)( + IN BOOLEAN MwaitSupport, + IN UINTN ApTargetCState, + IN UINTN PmCodeSegment, + IN UINTN TopOfApStack, + IN UINTN NumberToFinish, + IN UINTN Pm16CodeSegment, + IN UINTN SevEsAPJumpTable, + IN UINTN WakeupBuffer + ); + /** Assembly code to get starting address and size of the rendezvous entry f= or APs. Information for fixing a jump instruction in the code is also returned. diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Libr= ary/MpInitLib/X64/AmdSev.nasm index 7c2469f9c5..6b48913306 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -346,3 +346,172 @@ PM16Mode: iret =20 SwitchToRealProcEnd: +;-------------------------------------------------------------------------= ------------ +; AsmRelocateApLoopAmdSev (MwaitSupport, ApTargetCState, PmCodeSegment, T= opOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer= ); +;-------------------------------------------------------------------------= ------------ + +AsmRelocateApLoopStartAmdSev: +BITS 64 + cmp qword [rsp + 56], 0 ; SevEsAPJumpTable + je NoSevEsAmdSev + + ; + ; Perform some SEV-ES related setup before leaving 64-bit mode + ; + push rcx + push rdx + + ; + ; Get the RDX reset value using CPUID + ; + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for RDX + + ; + ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call + ; - Must be done while in 64-bit long mode so that writes to + ; the GHCB memory will be unencrypted. + ; - No NAE events can be generated once this is set otherwise + ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. + ; + mov rcx, 0xc0010130 + rdmsr ; Retrieve current GHCB address + shl rdx, 32 + or rdx, rax + + mov rdi, rdx + xor rax, rax + mov rcx, 0x800 + shr rcx, 3 + rep stosq ; Clear the GHCB + + mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD + mov [rdx + 0x390], rax + mov rax, 114 ; Set SwExitCode valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo1 valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo2 valid bit + bts [rdx + 0x3f0], rax + + pop rdx + pop rcx + +NoSevEsAmdSev: + cli ; Disable interrupt before switching to 3= 2-bit mode + mov rax, [rsp + 40] ; CountTofinish + lock dec dword [rax] ; (*CountTofinish)-- + + mov r10, [rsp + 48] ; Pm16CodeSegment + mov rax, [rsp + 56] ; SevEsAPJumpTable + mov rbx, [rsp + 64] ; WakeupBuffer + mov rsp, r9 ; TopOfApStack + + push rax ; Save SevEsAPJumpTable + push rbx ; Save WakeupBuffer + push r10 ; Save Pm16CodeSegment + push rcx ; Save MwaitSupport + push rdx ; Save ApTargetCState + + lea rax, [PmEntryAmdSev] ; rax <- The start address of trans= ition code + + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; +o64 retf + +BITS 32 +PmEntryAmdSev: + mov eax, cr0 + btr eax, 31 ; Clear CR0.PG + mov cr0, eax ; Disable paging and caches + + mov ecx, 0xc0000080 + rdmsr + and ah, ~ 1 ; Clear LME + wrmsr + mov eax, cr4 + and al, ~ (1 << 5) ; Clear PAE + mov cr4, eax + + pop edx + add esp, 4 + pop ecx, + add esp, 4 + +MwaitCheckAmdSev: + cmp cl, 1 ; Check mwait-monitor support + jnz HltLoopAmdSev + mov ebx, edx ; Save C-State to ebx +MwaitLoopAmdSev: + cli + mov eax, esp ; Set Monitor Address + xor ecx, ecx ; ecx =3D 0 + xor edx, edx ; edx =3D 0 + monitor + mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] + shl eax, 4 + mwait + jmp MwaitLoopAmdSev + +HltLoopAmdSev: + pop edx ; PM16CodeSegment + add esp, 4 + pop ebx ; WakeupBuffer + add esp, 4 + pop eax ; SevEsAPJumpTable + add esp, 4 + cmp eax, 0 ; Check for SEV-ES + je DoHltAmdSev + + cli + ; + ; SEV-ES is enabled, use VMGEXIT (GHCB information already + ; set by caller) + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Back from VMGEXIT AP_HLT_LOOP + ; Push the FLAGS/CS/IP values to use + ; + push word 0x0002 ; EFLAGS + xor ecx, ecx + mov cx, [eax + 2] ; CS + push cx + mov cx, [eax] ; IP + push cx + push word 0x0000 ; For alignment, will be discarded + + push edx + push ebx + + mov edx, esi ; Restore RDX reset value + + retf + +DoHltAmdSev: + cli + hlt + jmp DoHltAmdSev + +BITS 64 +AsmRelocateApLoopEndAmdSev: diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 5d71995bf8..d36f8ba06d 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -459,6 +459,9 @@ ASM_PFX(AsmGetAddressMap): lea rax, [AsmRelocateApLoopStart] mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], rax mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart + lea rax, [AsmRelocateApLoopStartAmdSev] + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= essAmdSev], rax + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= AmdSev], AsmRelocateApLoopEndAmdSev - AsmRelocateApLoopStartAmdSev mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], PM16Mode - RendezvousFunnelProcStart --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100354): https://edk2.groups.io/g/devel/message/100354 Mute This Topic: https://groups.io/mt/97081028/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-