From nobody Fri May 17 14:34:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100275+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100275+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676528202; cv=none; d=zohomail.com; s=zohoarc; b=PTn+FR3ifs11gPZd4BPdg7dkUSVgkPsmpdl/AYn4qxSYung5xy+HjPG270GcAyL23oUb/3jcOOWfrHC09dtnO1zq2VmX/wI17y+DjXvILhR4LJ6AmYsKregyzQmgCkXNvCa3GJUHL2xSBcB4tQ1+DrJFrTjI32HfS1lNmpGCXck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676528202; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=uOz0TC7pHvhxUdOX0F5/08kPGfmy6vEMgTW8yZD7Ls8=; b=KQ6uSQkcz4XvwOjEjZejwwGQHgP5s7UhTTPRB4lOJnIF/qCkzQ/lqBC7QIQSgnmJ3l99s2SpBNXIdm31aw2/8LHITiFefHz9ufmxGMixO7NiETXfq1899v5qBSt6cN6qrOgSW+C/dmzuACCj1/bg1uLcMz5AwKyMsBPTmQU32F0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100275+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676528202247568.8200589410009; Wed, 15 Feb 2023 22:16:42 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id EwiYYY1788612xbp65zYqTF7; Wed, 15 Feb 2023 22:16:41 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:41 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057136" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057136" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556561" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556561" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:38 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v9 1/6] UefiCpuPkg/PiSmmCpuDxeSmm: Fix invalid InitializeMpSyncData call Date: Thu, 16 Feb 2023 14:16:28 +0800 Message-Id: <20230216061633.9196-2-jiaxin.wu@intel.com> In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: cQaIodkBTKzsiZe6Wb5UkwK5x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676528201; bh=ABii+jFxwpUZMHAtvKsubUhTO3LZlnoCFAirbzbJvFI=; h=Cc:Date:From:Reply-To:Subject:To; b=lossOhWrEr+Cp2k4Hv0MQ57NLdkCTaQlNJegDsba/Fp89I6yg6cqeYrX/pmhhP2n7BY 3pz/GqK8Ln5bIOiqLdWcHk6JHDK7/nGQrZev1oSAsbGk220ABlbGalQ4RBfpHn/brtOTL vYoNv9/wpdV+7XqHN9j5pJ4GFhfK3V/OXH8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676528203234100006 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4338 No need call InitializeMpSyncData during normal boot SMI init, because mSmmMpSyncData is NULL at that time. mSmmMpSyncData is allocated in InitializeMpServiceData, which is invoked after normal boot SMI init (SmmRelocateBases). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..2ac655d032 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1,9 +1,9 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -369,13 +369,11 @@ SmmInitHandler ( if (!mSmmS3Flag) { // // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); - } - - if (mIsBsp) { + } else if (mIsBsp) { // // BSP rebase is already done above. // Initialize private data during S3 resume // InitializeMpSyncData (); --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100275): https://edk2.groups.io/g/devel/message/100275 Mute This Topic: https://groups.io/mt/97001111/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 14:34:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100276+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100276+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676528204; cv=none; d=zohomail.com; s=zohoarc; b=Fxl90dnfRg8/squcEZ43eNiFYy/dlewRH5n0Anr/W/dx2IjnKE/zhwg80Hti8EY749h/SQl7pOFbJ5BqzqbBcY676yaReXN9213ZynadQGnBct+M6ZJahr6YqE0xIZAfvRx8PW+aSSX2/dHTBuKNVC6sVpX4b/ma/aeyjE7tA2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676528204; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=cydO215rV9e7tCuowSTJhr/87jIc7SbQ2Ao5/6jU92Q=; b=e/GvkO1W8mLl8+bEvPBGWejZgFNxniux8ebAtvoVN4JRPdqSbYicuYerPcLFJ4ciN6gvyJx0Trto71F398ej+HAxuTYqzoXM84+e+pv8jflmN1WNUdjM8YFTjK5H+KH1m2TNgT44xUGWBnx9agnHNjD4ucnKJw2WjTpteKeZBmA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100276+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676528204458892.8523585510122; Wed, 15 Feb 2023 22:16:44 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id TU1qYY1788612xYX5odtMSaG; Wed, 15 Feb 2023 22:16:44 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:43 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057158" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057158" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556569" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556569" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:41 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v9 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Replace mIsBsp by mBspApicId check Date: Thu, 16 Feb 2023 14:16:29 +0800 Message-Id: <20230216061633.9196-3-jiaxin.wu@intel.com> In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: o2R3rHHYJmfbzGvhCV6td4BVx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676528204; bh=hdPfecips2UdX4CoxU/H9zsdhQA+ogSAvxMPsdpTbNY=; h=Cc:Date:From:Reply-To:Subject:To; b=cITp3gg68MP1Ekzff5YraOxgYzfadG8H4KYqo9PJ5D0khdL1uRNWOd3kscx0CcGl27O T7p3rCaOpXpV83H6sQ9in9lef35btzPWOLxVeGAHdhlDu1OdhppOTKu7zgxH5hdPv9HAX iEp4es6Vrg736SwzMnkHS+jVchg45bARswI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676528205272100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to replace mIsBsp by mBspApicId check. mIsBsp becomes the local variable (IsBsp), then it can be checked dynamically in the function. Instead, we define the mBspApicId, which is to record the BSP ApicId used for compare in SmmInitHandler. With this change, SmmInitHandler can be run in parallel during SMM init. Note: This patch is the per-prepared work by refining the SmmInitHandler, then, we can do the next step to combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler will call the SmmInitHandler in parallel to do the init. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni Reviewed-by: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 2ac655d032..6e795d1756 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -57,11 +57,10 @@ SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate =3D &mSmmCpuPriva= teData; =20 // // SMM Relocation variables // volatile BOOLEAN *mRebased; -volatile BOOLEAN mIsBsp; =20 /// /// Handle for the SMM CPU Protocol /// EFI_HANDLE mSmmCpuHandle =3D NULL; @@ -83,10 +82,12 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribut= e =3D { EdkiiSmmClearMemoryAttributes }; =20 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; =20 +UINT32 mBspApicId =3D 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -341,39 +342,42 @@ VOID EFIAPI SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; + BOOLEAN IsBsp; =20 // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId =3D GetApicId (); =20 + IsBsp =3D (BOOLEAN)(mBspApicId =3D=3D ApicId); + ASSERT (mNumberOfCpus <=3D mMaxNumberOfCpus); =20 for (Index =3D 0; Index < mNumberOfCpus; Index++) { if (ApicId =3D=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Process= orId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsBsp, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); =20 if (!mSmmS3Flag) { // // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); - } else if (mIsBsp) { + } else if (IsBsp) { // // BSP rebase is already done above. // Initialize private data during S3 resume // InitializeMpSyncData (); @@ -405,11 +409,10 @@ SmmRelocateBases ( { UINT8 BakBuf[BACK_BUF_SIZE]; SMRAM_SAVE_STATE_MAP BakBuf2; SMRAM_SAVE_STATE_MAP *CpuStatePtr; UINT8 *U8Ptr; - UINT32 ApicId; UINTN Index; UINTN BspIndex; =20 // // Make sure the reserved size is large enough for procedure SmmInitTemp= late. @@ -446,21 +449,20 @@ SmmRelocateBases ( CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize); =20 // // Retrieve the local APIC ID of current processor // - ApicId =3D GetApicId (); + mBspApicId =3D GetApicId (); =20 // // Relocate SM bases for all APs // This is APs' 1st SMI - rebase will be done here, and APs' default SMI= handler will be overridden by gcSmmInitTemplate // - mIsBsp =3D FALSE; BspIndex =3D (UINTN)-1; for (Index =3D 0; Index < mNumberOfCpus; Index++) { mRebased[Index] =3D FALSE; - if (ApicId !=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Processor= Id) { + if (mBspApicId !=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Proce= ssorId) { SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId= ); // // Wait for this AP to finish its 1st SMI // while (!mRebased[Index]) { @@ -475,12 +477,11 @@ SmmRelocateBases ( =20 // // Relocate BSP's SMM base // ASSERT (BspIndex !=3D (UINTN)-1); - mIsBsp =3D TRUE; - SendSmiIpi (ApicId); + SendSmiIpi (mBspApicId); // // Wait for the BSP to finish its 1st SMI // while (!mRebased[BspIndex]) { } --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100276): https://edk2.groups.io/g/devel/message/100276 Mute This Topic: https://groups.io/mt/97001112/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 14:34:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100277+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100277+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676528206; cv=none; d=zohomail.com; s=zohoarc; b=d19Il2JsR7VMmboRRKwQ65N7JjLin4dHALh99DfAmmSfrMBfVOHrxiXvs1FuZXoBWTnf/3R9Sn86wxjyGY/NNy/ZM+TsGJie7Iw037XjoUDbile/BFJqTZy5vHT384n4bb/Iuzp8ylVckI3tiHcynsVI/Qenc6LDiDSWJSSoVe8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676528206; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=z71No2NZ4nNxwA2+LVWT4cdZtRFMNRlZAyvXuj8wBHI=; b=mZSEAbyb1DiXTVJYFq6vD55tc/aPYV+f3EA1kzCa/LocAUmRRwS+Xn/nAanTn8+5F9QGmuMT1cMjDeiLEwmMcUoQPVDbzTqurmnOli1E0O4Lyy5bG30e1tnhfvZLPsJtiXOPhJxfmqgvoMSFV66XTbQySrHkk3o1PgquoFGC//U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100277+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676528206655992.2191420370414; Wed, 15 Feb 2023 22:16:46 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id qvEBYY1788612xZSLgAVAr32; Wed, 15 Feb 2023 22:16:46 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:45 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057179" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057179" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556575" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556575" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:43 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v9 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Thu, 16 Feb 2023 14:16:30 +0800 Message-Id: <20230216061633.9196-4-jiaxin.wu@intel.com> In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: MvC6CqomdSg3wxogjThiXKpVx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676528206; bh=UNSSrbxwB3L15hYVgl5ShWmR1RAl9Hkl6HCju7YruvQ=; h=Cc:Date:From:Reply-To:Subject:To; b=oT4Ca7VVZHgjj/d+cDXHxHF9eHPsm8dTUGR0xULD/ZSjdFOirm5i1DWhUyswJOmLBtx DbIyfUynamaIdEcd+H2DcnngK5bpbEoDcleuWIAQN7liKGbLUeM551bT9hsVmPL0mAish VJEje0cIozxlL4cIdZLd0N5phOVuvkVhu9A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676528207291100014 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4337 The default SMBASE for the x86 processor is 0x30000. When SMI happens, processor runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from processor perspective is to relocate and program the new SMBASE (in TSEG range) for each processor. When the SMBASE relocation happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program the new SMBASE itself. This patch adds the SMM Base HOB for any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for each processor. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 75 ++++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 5 ++- 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid= /SmmBaseHob.h new file mode 100644 index 0000000000..115e749348 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,75 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase address in array for each processor. + + The default Smbase for the x86 processor is 0x30000. When SMI happens, p= rocessor + runs the SMI handler at Smbase+0x8000. Also, the SMM save state area is = within + Smbase+0x10000. Since it's the start address to store the processor save= state + and code for the SMI entry point, those info are tiled within an SMRAM a= llocated + or reserved buffer. This tile size shall be enough to cover 3 parts: + 1. Processor SMRAM Save State Map starts at Smbase + 0xfc00 + 2. Extra processor specific context start starts at Smbase + 0xfb00 + 3. SMI entry point starts at Smbase + 0x8000. + Besides, This size should be rounded up to nearest power of 2. The Smm B= ase HOB + producer should be responsible for reserving enough size. + + One of the SMM initialization from processor perspective is to relocate = and program + the new Smbase (in TSEG range) for each processor thread. When the Smbas= e relocation + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB i= n HOB database + which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) abou= t the new + Smbase for each processor. PiSmmCpuDxeSmm driver installs the SMI handle= r at the + SMM_BASE_HOB.Smbase[Index]+0x8000 for processor index. When the HOB does= n't exist, + PiSmmCpuDxeSmm driver shall relocate and program the new Smbase itself. + + Note: + 1. Smbase relocation process needs to program the vender specific hardwa= re + interface to set Smbase, it might be in the thread scope. It's doable to + program the hardware interface using DXE MP service protocol in PiSmmCpu= DxeSmm + entry point. But, considering the standalone MM environment where the Cp= uMm + driver runs in a isolated environment and it cannot invoke any DXE or PE= I MP + service, we recommend to put the hardware interface programming in a sep= arate + PEI module instead of in the PiSmmCpuDxeSmm driver. + + 2. There is the hard requirement that SMI Entry Size <=3D 0x1000, data S= ize <=3D + 0x1000 in PiSmmCpuDxeSmm. So, this require the allocated or reserved buf= fer in + SMRAM should be >=3D 0x2000. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d,= 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// ProcessorIndex tells which processor range this specific HOB instanc= e described. + /// If ProcessorIndex is set to 0, it indicats the HOB describes the pro= cessor from + /// 0 to NumberOfProcessors - 1. The HOB list may contains multiple this= HOB + /// instances. Each HOB instances describe the information for processor= from + /// ProcessorIndex to ProcessorIndex + NumberOfProcessors - 1. The insta= nce order in + /// the HOB list is random so consumer can not assume the ProcessorIndex= of first + /// instance is 0. + /// + UINT32 ProcessorIndex; + /// + /// Describes the Number of all max supported processors. + /// + UINT32 NumberOfProcessors; + /// + /// Pointer to SmBase address for each processor. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..7003a2ba77 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,9 +1,9 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} =20 + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid =3D { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c= , 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94= , 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid =3D { 0xaa00d50b, 0x4911, 0x428f, { 0= xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100277): https://edk2.groups.io/g/devel/message/100277 Mute This Topic: https://groups.io/mt/97001113/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 14:34:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100278+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100278+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676528209; cv=none; d=zohomail.com; s=zohoarc; b=LCsdUayG9DazyRfe61KOSpetxUBp6xif7+wNkuafEIdjaUKwRhuTI0ya33PROQ/PEiHoG/Sh2NzR+Oaa65Rco8K03u8mdP18JZaZ4ZEGL008wZ7TwDrvzuQqGQN8cm16Gy85JcGBS1+QW8NYP6Bo5f4Etjxb2MzFo1X37HktaBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676528209; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=XHko0q5dxmtMWh1VpV2UCY9wJvJMh2sMc2OVc9cRp7o=; b=HJRnbhiujvFkFp50WyfwdSQGKGPRiBuAe4MS+ETwPbYkTTfZQj8c1KdP2pK2k0ArNX0NAwiLyfwsf0IJhMT4V1eCUhp8jRtgD7F4HEJknVkoYN6N2/0XFLvOLZcR4+rPoQN6ByALCJ14gaU2McVQ+qU+4qI+QIhA9NjEuaUQfS8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100278+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676528209281142.68442280833995; Wed, 15 Feb 2023 22:16:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zBJBYY1788612xEOuBwEfptN; Wed, 15 Feb 2023 22:16:48 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:48 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057196" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057196" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556582" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556582" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:45 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v9 4/6] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info Date: Thu, 16 Feb 2023 14:16:31 +0800 Message-Id: <20230216061633.9196-5-jiaxin.wu@intel.com> In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: QUmYFS7pdmkYqnOzerGHBBjGx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676528208; bh=B8bZIzwk4Kc8p7FzhudWV2IEBq6OPiP0WadwkMHdUYg=; h=Cc:Date:From:Reply-To:Subject:To; b=wBFanrSCYpyXcGWu9FARF3QvrJLg3Hs/JcCu1rmmLxpAfEuVR3xt4Qjp2PvRccOmk9a XYmZO5TScx6VZb/36ndPfjXhOscRL2n75hvfV5m+nnEaQZXCDjiAhoeVS052jpibvdX5M ZmJOj+D+7TkyICX4hYfYLNa6OW3CXmZiOa0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676528211301100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4337 Existing SMBASE Relocation is in the PiSmmCpuDxeSmm driver, which will relocate the SMBASE of each processor by setting the SMBASE field in the saved state map (at offset 7EF8h) to a new value. The RSM instruction reloads the internal SMBASE register with the value in SMBASE field when each time it exits SMM. All subsequent SMI requests will use the new SMBASE to find the starting address for the SMI handler (at SMBASE + 8000h). Due to the default SMBASE for all x86 processors is 0x30000, the APs' 1st SMI for rebase has to be executed one by one to avoid the processors over-writing each other's SMM Save State Area (see existing SmmRelocateBases() function), which means the next AP has to wait for the previous AP to finish its 1st SMI, then it can call into its 1st SMI for rebase via Smi Ipi command, thus leading the existing SMBASE Relocation has to be running in series. Besides, it needs very complex code to handle the AP exit semaphore (mRebased[Index]), which will hook return address of SMM Save State so that semaphore code can be executed immediately after AP exits SMM for SMBASE relocation (see existing SemaphoreHook() function). With SMM Base Hob support, PiSmmCpuDxeSmm does not need the RSM instruction to do the SMBASE Relocation. SMBASE Register for each processors have already been programmed and all SMBASE address have recorded in SMM Base Hob. So the same default SMBASE Address (0x30000) will not be used, thus the processors over-writing each other's SMM Save State Area will not happen in PiSmmCpuDxeSmm driver. This way makes the first SMI init can be executed in parallel and save boot time on multi-core system. Besides, Semaphore Hook code logic is also not required, which will greatly simplify the SMBASE Relocation flow. Mainly changes as below: * Assume the biggest possibility of tile size is 8k. * Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. * Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for first SMI init before normal SMI sources happen. * Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 31 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 25 +++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 166 ++++++++++++++++++++++-= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 3 +- 5 files changed, 214 insertions(+), 37 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index fb4a44eab6..d408b3f9f7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,9 +1,9 @@ /** @file Code for Processor S3 restoration =20 -Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 #include "PiSmmCpuDxeSmm.h" @@ -822,13 +822,38 @@ SmmRestoreCpu ( // InitializeCpuBeforeRebase (); } =20 // - // Restore SMBASE for BSP and all APs + // Make sure the gSmmBaseHobGuid existence status is the same between no= rmal and S3 boot. // - SmmRelocateBases (); + ASSERT (mSmmRelocated =3D=3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid= ) !=3D NULL)); + if (mSmmRelocated !=3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) !=3D= NULL)) { + DEBUG (( + DEBUG_ERROR, + "gSmmBaseHobGuid %a produced in normal boot but %a in S3 boot!", + mSmmRelocated ? "is" : "is not", + mSmmRelocated ? "is not" : "is" + )); + CpuDeadLoop (); + } + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! + // + if (!mSmmRelocated) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execut= e first SMI init. + // + ExecuteFirstSmiInit (); + } =20 // // Skip initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index a0967eb69c..baf827cf9d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1,9 +1,9 @@ /** @file SMM MP service implementation =20 -Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -1721,17 +1721,40 @@ SmiRendezvous ( UINTN Index; UINTN Cr2; =20 ASSERT (CpuIndex < mMaxNumberOfCpus); =20 + if (mSmmRelocated) { + ASSERT (mSmmInitialized !=3D NULL); + } + // // Save Cr2 because Page Fault exception in SMM may override its value, // when using on-demand paging for above 4G memory. // Cr2 =3D 0; SaveCr2 (&Cr2); =20 + if (mSmmRelocated && !mSmmInitialized[CpuIndex]) { + // + // Perform SmmInitHandler for CpuIndex + // + SmmInitHandler (); + + // + // Restore Cr2 + // + RestoreCr2 (Cr2); + + // + // Mark the first SMI init for CpuIndex has been done so as to avoid t= he reentry. + // + mSmmInitialized[CpuIndex] =3D TRUE; + + return; + } + // // Call the user register Startup function first. // if (mSmmMpSyncData->StartupProcedure !=3D NULL) { mSmmMpSyncData->StartupProcedure (mSmmMpSyncData->StartupProcArgs); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 6e795d1756..d2d0950f3b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -82,10 +82,12 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribut= e =3D { EdkiiSmmClearMemoryAttributes }; =20 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; =20 +BOOLEAN mSmmRelocated =3D FALSE; +volatile BOOLEAN *mSmmInitialized =3D NULL; UINT32 mBspApicId =3D 0; =20 // // SMM stack information // @@ -381,22 +383,69 @@ SmmInitHandler ( // Initialize private data during S3 resume // InitializeMpSyncData (); } =20 - // - // Hook return after RSM to set SMM re-based flag - // - SemaphoreHook (Index, &mRebased[Index]); + if (!mSmmRelocated) { + // + // Hook return after RSM to set SMM re-based flag + // + SemaphoreHook (Index, &mRebased[Index]); + } =20 return; } } =20 ASSERT (FALSE); } =20 +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute firs= t SMI init. + +**/ +VOID +ExecuteFirstSmiInit ( + VOID + ) +{ + UINTN Index; + + if (mSmmInitialized =3D=3D NULL) { + mSmmInitialized =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * mMaxNu= mberOfCpus); + } + + ASSERT (mSmmInitialized !=3D NULL); + if (mSmmInitialized =3D=3D NULL) { + return; + } + + // + // Reset the mSmmInitialized to false. + // + ZeroMem ((VOID *)mSmmInitialized, sizeof (BOOLEAN) * mMaxNumberOfCpus); + + // + // Get the BSP ApicId. + // + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (!(BOOLEAN)mSmmInitialized[Index]) { + } + } +} + /** Relocate SmmBases for each processor. =20 Execute on first boot and all S3 resumes =20 @@ -560,10 +609,15 @@ PiCpuSmmEntry ( UINT32 RegEcx; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; UINT32 Cr3; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + + GuidHob =3D NULL; + SmmBaseHobData =3D NULL; =20 // // Initialize address fixup // PiSmmCpuSmmInitFixupAddress (); @@ -788,30 +842,58 @@ PiCpuSmmEntry ( // context must be reduced. // ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // - // Allocate buffer for all of the tiles. - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.11 SMBASE Relocation - // For Pentium and Intel486 processors, the SMBASE values must be - // aligned on a 32-KByte boundary or the processor will enter shutdown - // state during the execution of a RSM instruction. - // - // Intel486 processors: FamilyId is 4 - // Pentium processors : FamilyId is 5 + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. // - BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfC= pus - 1)); - if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + GuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); + if (GuidHob !=3D NULL) { + // + // Check whether the Required TileSize is enough. + // + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- = Required TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE= _8KB)); + CpuDeadLoop (); + return RETURN_BUFFER_TOO_SMALL; + } + + SmmBaseHobData =3D GET_GUID_HOB_DATA (GuidHob); + + // + // Assume single instance of HOB produced, expect the HOB.NumberOfProc= essors equals to the mMaxNumberOfCpus. + // + ASSERT (SmmBaseHobData->NumberOfProcessors =3D=3D (UINT32)mMaxNumberOf= Cpus && SmmBaseHobData->ProcessorIndex =3D=3D 0); + mSmmRelocated =3D TRUE; } else { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); - } + // + // When the HOB doesn't exist, allocate new SMBASE itself. + // + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + // + // Allocate buffer for all of the tiles. + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.11 SMBASE Relocation + // For Pentium and Intel486 processors, the SMBASE values must be + // aligned on a 32-KByte boundary or the processor will enter shutdo= wn + // state during the execution of a RSM instruction. + // + // Intel486 processors: FamilyId is 4 + // Pentium processors : FamilyId is 5 + // + BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberO= fCpus - 1)); + if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + } else { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); + } =20 - ASSERT (Buffer !=3D NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer,= EFI_PAGES_TO_SIZE (BufferPages))); + ASSERT (Buffer !=3D NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%= 08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } =20 // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // gSmmCpuPrivate->ProcessorInfo =3D (EFI_PROCESSOR_INFORMATION *)AllocateP= ool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); @@ -842,11 +924,12 @@ PiCpuSmmEntry ( // Retrieve APIC ID of each enabled processor from the MP Services proto= col. // Also compute the SMBASE address, CPU Save State address, and CPU Save= state // size for each CPU in the platform // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Ti= leSize - SMM_HANDLER_OFFSET; + mCpuHotPlugData.SmBase[Index] =3D mSmmRelocated ? (UINTN)SmmBaseHobDat= a->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof (SMRAM_SAVE_STATE_M= AP); gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { @@ -955,21 +1038,27 @@ PiCpuSmmEntry ( // Initialize IDT // InitializeSmmIdt (); =20 // - // Relocate SMM Base addresses to the ones allocated from SMRAM + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberO= fCpus); - ASSERT (mRebased !=3D NULL); - SmmRelocateBases (); + if (!mSmmRelocated) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumbe= rOfCpus); + ASSERT (mRebased !=3D NULL); + SmmRelocateBases (); =20 - // - // Call hook for BSP to perform extra actions in normal mode after all - // SMM base addresses have been relocated on all CPUs - // - SmmCpuFeaturesSmmRelocationComplete (); + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } =20 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); =20 // // SMM Time initialization @@ -996,10 +1085,25 @@ PiCpuSmmEntry ( ); } } } =20 + // + // For relocated SMBASE, some MSRs & CSRs are still required to be confi= gured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM I= PI) to execute first SMI init. + // + if (mSmmRelocated) { + ExecuteFirstSmiInit (); + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + // // Fill in SMM Reserved Regions // gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart =3D 0; gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize =3D 0; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 5f0a38e400..c3731f174b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1,9 +1,9 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -23,10 +23,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =20 #include #include #include +#include =20 #include #include #include #include @@ -346,10 +347,29 @@ SmmWriteSaveState ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer ); =20 +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID + ); + +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute firs= t SMI init. + +**/ +VOID +ExecuteFirstSmiInit ( + VOID + ); + /** Read a CPU Save State register on the target processor. =20 This function abstracts the differences that whether the CPU Save State re= gister is in the IA32 CPU Save State Map or X64 CPU Save State Map. @@ -400,10 +420,14 @@ WriteSaveStateRegister ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ); =20 +extern BOOLEAN mSmmRelocated; +extern volatile BOOLEAN *mSmmInitialized; +extern UINT32 mBspApicId; + extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; extern UINT32 mSmmCr0; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index b4b327f60c..9bfa8c1a76 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -2,11 +2,11 @@ # CPU SMM driver. # # This SMM driver performs SMM initialization, deploy SMM Entry Vector, # provides CPU specific services in SMM. # -# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -112,10 +112,11 @@ =20 [Guids] gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # = it is used for S3 boot. gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONS= UMES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100278): https://edk2.groups.io/g/devel/message/100278 Mute This Topic: https://groups.io/mt/97001114/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 14:34:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100279+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100279+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676528211; cv=none; d=zohomail.com; s=zohoarc; b=eV9fik1QFXWbnuqvYpqgPhlIpG63lbCEHgacACTdofU+IgISk7cU25lJApraJ+ZsoyqcqB8P+iDXSx3sMOq+7f1C7vEKi9ePvMOORCldUIML66C2yY7dMs1jD0bdfF6h/OFFLf1ZhRoW4xFWT0AiZqhd9t8iq2Mb9AP0c1RfSUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676528211; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=g+nqINm/An4faqWM9HpsG5LWM0F/7uqLzf3ztPmHpcs=; b=i+vYxP9EBBiCMlmTUXIDAOedZu7jcjpaE50FmIvnIKKjFBFqiKOBBCIlTjNICdO+WqYEQAdCMvmnIT0eHtjeM1dmno0stIqFWPauHBCyVj6vA9ba4kZExXkJYAWTyFHHaienIWS+UqiK6oTWAS1oSBwQ0/HumxufYtptIlAV6dE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100279+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676528211618126.364436827252; Wed, 15 Feb 2023 22:16:51 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZhUSYY1788612xD73mBDMhIh; Wed, 15 Feb 2023 22:16:51 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057217" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057217" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556585" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556585" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:48 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v9 5/6] UefiCpuPkg/SmmCpuFeaturesLib: Skip SMBASE configuration Date: Thu, 16 Feb 2023 14:16:32 +0800 Message-Id: <20230216061633.9196-6-jiaxin.wu@intel.com> In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: vfeYHQfAeVxmWe46a2RspRRex1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676528211; bh=xPVh6+XYeSHQ398xTPurEGMZLzsnX+RqYiUB6OMt4cM=; h=Cc:Date:From:Reply-To:Subject:To; b=pAzqUDoeUaC6X/f9E3hkZB2Pk9H8cMDoTKnh5krRgRjv61+mIXLz9dSbfkHPYh3h5zr WsQskXCmYTgt5itEgbrpYrUCA9zA4uHkame0nrE4B9oO97dYVegIhwE/wKRIXZCGTypJx CfExVGLDy2mGPrqxpWN3LOhMAhjtT59FO2M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676528213341100006 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4337 This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h | 2 ++ .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c | 25 ++++++++++++++++++= ---- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 6 +++++- .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 3 +-- .../StandaloneMmCpuFeaturesLib.inf | 6 +++++- 6 files changed, 36 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h index fd3e902547..c2e4fbe96b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h @@ -7,15 +7,17 @@ **/ =20 #ifndef CPU_FEATURES_LIB_H_ #define CPU_FEATURES_LIB_H_ =20 +#include #include #include #include #include #include +#include =20 /** Performs library initialization. =20 This initialization function contains common functionality shared betwen= all diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index d5eaaa7a99..1a2c706fa1 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -1,9 +1,9 @@ /** @file Implementation shared across all library instances. =20 -Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 @@ -36,10 +36,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmmCpuFeaturesSmmRelocated; + // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs =3D TRUE; =20 @@ -142,10 +148,16 @@ CpuFeaturesLibInitialization ( // // Allocate array for state of SMRR enable on all CPUs // mSmrrEnabled =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLo= gicalProcessorNumber ()); ASSERT (mSmrrEnabled !=3D NULL); + + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + mSmmCpuFeaturesSmmRelocated =3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobG= uid) !=3D NULL); } =20 /** Called during the very first SMI into System Management Mode to initiali= ze CPU features, including SMBASE, for the currently executing CPU. Since = this @@ -185,14 +197,19 @@ SmmCpuFeaturesInitializeProcessor ( UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmCpuFeaturesSmmRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_S= MBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily // diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9ac7dde78f..46ae2bf85e 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -1,9 +1,9 @@ ## @file # The CPU specific programming for PiSmmCpuDxeSmm module. # -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 [Defines] @@ -31,10 +31,14 @@ [LibraryClasses] BaseLib PcdLib MemoryAllocationLib DebugLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 86d367e0a0..51322ff189 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -1,10 +1,10 @@ ## @file # The CPU specific programming for PiSmmCpuDxeSmm module when STM support # is included. # -# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 [Defines] @@ -62,10 +62,11 @@ =20 [Guids] gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## System= Table gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## System= Table + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOME= TIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 3cf162ada0..6cb1c515c0 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -1,16 +1,15 @@ /** @file SMM STM support functions =20 - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 #include #include -#include #include #include #include #include #include diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLi= b.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index b1f60a5505..c836939d33 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -1,9 +1,9 @@ ## @file # Standalone MM CPU specific programming. # -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 @@ -32,10 +32,14 @@ [LibraryClasses] BaseLib DebugLib MemoryAllocationLib PcdLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100279): https://edk2.groups.io/g/devel/message/100279 Mute This Topic: https://groups.io/mt/97001115/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 14:34:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100280+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100280+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676528213; cv=none; d=zohomail.com; s=zohoarc; b=at2h4nqalhJFG1pbA4lLot9cHXdLFGWzA40y1WNUUVD/QpClS43yg8zhFb+7wFN15/HaoJmqzywZoInAknuFkP9uICtgkkGnoGGGq05NjEqKjNVMzWsvRuxneoTcmZF8Jfggz1jus7AvS9RodVdPN7qTbgW7WOTh8YPVkMU5Rec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676528213; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=euvh/zpckaaGD3xlo8qILcpk7UrSg1xbtZWS9cn6E9E=; b=Knjm93DynJxvmo74u0lPmbsGCKeZChMdLLxz7RdrsoWB+K1SEOKq03Y2vLrsSW6xwWuYdNDdga4OwNkU4AWh40RKV1IaA2Y9XSvx9OaqrxaHpX/oQJ31fJqEaaw6Gjw//JDkQiaCKiCee7390nKlebMLuLZi5rfrQa93hCGqS6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100280+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676528213791911.2614044934644; Wed, 15 Feb 2023 22:16:53 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id TznWYY1788612xumH0QEBa6n; Wed, 15 Feb 2023 22:16:53 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4368.1676528199491436564 for ; Wed, 15 Feb 2023 22:16:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="394057233" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="394057233" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 22:16:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="647556591" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="647556591" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 15 Feb 2023 22:16:50 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v9 6/6] OvmfPkg/SmmCpuFeaturesLib: Check SmBase relocation supported or not Date: Thu, 16 Feb 2023 14:16:33 +0800 Message-Id: <20230216061633.9196-7-jiaxin.wu@intel.com> In-Reply-To: <20230216061633.9196-1-jiaxin.wu@intel.com> References: <20230216061633.9196-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: 4oy7YExuLi5pCSsKDqfxPfuKx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676528213; bh=ovW+nBlASXXvXDSsnHpMnT1dvSjWHhKAPssTnWP4u14=; h=Cc:Date:From:Reply-To:Subject:To; b=D8e5GacoVFEJCcS2JtoMYJm1N6TKvNxhpD5+LppRHoygws0pgfLD3VJO1QznftNI5Y+ zzIEpQdb9LL4J+1f72MgxiNySiswzR1K/vSHT4f8hxeLBRMsiSUN3BfERV8xZQslj3Nxy gfNnVg61fEcroObdtpJmEpk3xXrUTTnlKpM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676528215317100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4337 This patch is to check SmBase relocation supported or not. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. ASSERT it's not supported in OVMF. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Gerd Hoffmann Reviewed-by: Ray Ni --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 10 +++++++++- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 6 +++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 6693666d04..a1dd10c9f2 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -1,9 +1,9 @@ /** @file The CPU specific programming for PiSmmCpuDxeSmm module. =20 - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 #include @@ -15,14 +15,16 @@ #include #include #include #include #include +#include #include #include #include #include +#include =20 // // EFER register LMA bit // #define LMA BIT10 @@ -41,10 +43,16 @@ EFIAPI SmmCpuFeaturesLibConstructor ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. ASSERT it's not supported in OVMF. + // + ASSERT (GetFirstGuidHob (&gSmmBaseHobGuid) =3D=3D NULL); + // // No need to program SMRRs on our virtual platform. // return EFI_SUCCESS; } diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 8a426a4c10..2697a90525 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -1,9 +1,9 @@ ## @file # The CPU specific programming for PiSmmCpuDxeSmm module. # -# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 @@ -33,10 +33,14 @@ MemoryAllocationLib PcdLib SafeIntLib SmmServicesTableLib UefiBootServicesTableLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100280): https://edk2.groups.io/g/devel/message/100280 Mute This Topic: https://groups.io/mt/97001116/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-