From nobody Sun Feb 8 22:07:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99983+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99983+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032255; cv=none; d=zohomail.com; s=zohoarc; b=aGQm9R91QlRXGddinG8XMnwvBajidlRb44kXODx5oUNM1ojlW9j8XmLKCNapOv0McyiFegapMQTfaCWwRgFgsXCsU7ulkMSGV7GNYWYg9OW9LXydkPt2vrtlVDsDm+7XgmElvSHUYn7xbVPagCuLNjJ5onZwXF1WzwWgphBQ2zg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032255; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZvRyTrHV8lf6jQx8jQK15TAicm7OfPg4iDReYe4yFZU=; b=azK6mzXAdZ5Tlc+ZznvI/gmmeANmspy4eYEIi04wg3uws5Ik3U/Opsw2nQ2HIJg/2PpQLOM9idnzVrEKz1IuABmtB0dsx9d3MnN/vlzNWA3uQ8hbIviDdF5TFJ05GYPD86xAhhV4auihOfDJWJXXf29xBsFf2bli3Rov+wq43MY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99983+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032255347142.76294520248462; Fri, 10 Feb 2023 04:30:55 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id HEIiYY1788612x0ZdpYEvOok; Fri, 10 Feb 2023 04:30:55 -0800 X-Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web11.13153.1676032254471690814 for ; Fri, 10 Feb 2023 04:30:54 -0800 X-Received: by mail-pj1-f43.google.com with SMTP id d13-20020a17090ad3cd00b0023127b2d602so5383170pjw.2 for ; Fri, 10 Feb 2023 04:30:54 -0800 (PST) X-Gm-Message-State: IfVFIyzVBvnG3oOU6cp2Zu1Vx1787277AA= X-Google-Smtp-Source: AK7set9x0w+avBODfFC984qPIPV2iIJ20cq7MCxJj8szPKeaYeIX5GwvcDjITudmYxmgKdxMDfv5og== X-Received: by 2002:a17:902:e38a:b0:198:fd58:ee43 with SMTP id g10-20020a170902e38a00b00198fd58ee43mr10815854ple.12.1676032253751; Fri, 10 Feb 2023 04:30:53 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:30:53 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 02/19] MdePkg/BaseLib: RISC-V: Add few more helper functions Date: Fri, 10 Feb 2023 18:00:24 +0530 Message-Id: <20230210123041.1489506-3-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032255; bh=Sinq8v1jDP2zSgrRKuDeG/ofMDCb9ZW+UmUrRvodAWc=; h=Cc:Date:From:Reply-To:Subject:To; b=mjpnRms+6X4yEed5LR3MmNXS1SLSq9EYg1xWDNnnmk77Gy6cNBk54v4IU5SatllxjX6 FlXwNgR8hvACRnNrzGEBstUWmh2fC0NqYzGClpplzs4o/ENGkCkL+eeiPx9lH3GA08JMh UvU+Z9xh6C5jylFEhVcRBH/RZTNLVfuIB2E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032256959100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Daniel Schaefer Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Reviewed-by: Michael D Kinney --- MdePkg/Library/BaseLib/BaseLib.inf | 3 ++ MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++ MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++-- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 +++++++++ 6 files changed, 179 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 9ed46a584a14..3a48492b1a01 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,9 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuScratch.S | GCC + RiscV64/ReadTimer.S | GCC + RiscV64/RiscVMmu.S | GCC =20 [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index f3f59f21c2ea..8f2df76c29a3 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -151,6 +151,56 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID +RiscVSetSupervisorScratch ( + IN UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID +RiscVSetSupervisorStvec ( + IN UINT64 + ); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +UINT64 +RiscVGetSupervisorTrapCause ( + VOID + ); + +VOID +RiscVSetSupervisorAddressTranslationRegister ( + IN UINT64 + ); + +UINT64 +RiscVReadTimer ( + VOID + ); + +VOID +RiscVEnableTimerInterrupt ( + VOID + ); + +VOID +RiscVDisableTimerInterrupt ( + VOID + ); + +VOID +RiscVClearPendingTimerInterrupt ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/B= aseLib/RiscV64/CpuScratch.S new file mode 100644 index 000000000000..5492a500eb5e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrw CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/Ba= seLib/RiscV64/ReadTimer.S new file mode 100644 index 000000000000..39a06efa51ef --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// Read CPU timer +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Read TIME CSR. +// @retval a0 : 64-bit timer. +// +ASM_FUNC (RiscVReadTimer) + csrr a0, CSR_TIME + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S index 87b3468fc7fd..6a1b90a7e45c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -8,13 +8,13 @@ // //------------------------------------------------------------------------= ------ =20 +#include + ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) =20 -#define SSTATUS_SIE 0x00000002 -#define CSR_SSTATUS 0x100 - #define SSTATUS_SPP_BIT_POSITION 8 +#define SSTATUS_SPP_BIT_POSITION 8 =20 // // This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap: ret =20 // +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, CSR_STVEC, a0 + ret + +// +// Get Supervisor mode trap vector. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, CSR_STVEC + ret + +// +// Get Supervisor trap cause CSR. +// +ASM_FUNC (RiscVGetSupervisorTrapCause) + csrrs a0, CSR_SCAUSE, 0 + ret +// // This routine returns supervisor mode interrupt // status. // -ASM_PFX(RiscVGetSupervisorModeInterrupts): +ASM_FUNC (RiscVGetSupervisorModeInterrupts) csrr a0, CSR_SSTATUS andi a0, a0, SSTATUS_SIE ret =20 +// +// This routine disables supervisor mode timer interrupt +// +ASM_FUNC (RiscVDisableTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIE, a0 + ret + +// +// This routine enables supervisor mode timer interrupt +// +ASM_FUNC (RiscVEnableTimerInterrupt) + li a0, SIP_STIP + csrs CSR_SIE, a0 + ret + +// +// This routine clears pending supervisor mode timer interrupt +// +ASM_FUNC (RiscVClearPendingTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIP, a0 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/Bas= eLib/RiscV64/RiscVMmu.S new file mode 100644 index 000000000000..ac8f92f38aed --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) + csrw CSR_SATP, a0 + ret --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99983): https://edk2.groups.io/g/devel/message/99983 Mute This Topic: https://groups.io/mt/96874980/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-