From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99982+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99982+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032253; cv=none; d=zohomail.com; s=zohoarc; b=Ld3L7yVQG0ZXdNxpSshiqVE0I6Za1aW/vCGz0w+ma2yptfLYAfRr6e/04h/Y3zoPL9F7UTYhTlBMPXXKr+L3Vg2qWny/B7QV9fYD+rJwE6n5TC+AHiH/Iiwynl54JRxa/Ux2KZO6DPFkfqR4QKCntSnHuRdL2ajTJ7l4kZqZCkM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032253; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=WRD/lzXWvpBefg5/F5UKDvLwsb9A7nSih9+ME99dqVI=; b=EOFIF2rNQFLSuIUjn0Y6ZCXX0pAygG+uv43QnroAduVfwOdrR3tzTGl/nuvlCUcQ8AFbS0uKcEIlstOnxTK3PA746dchzCRFxjXQ98M9F1jZADKAdNwtvmj4m8Nv2vk7IcJkNQ8WqNJtOmloyv+PPa30DYw2y6InTdvXqrPE56E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99982+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167603225333384.40596160441987; Fri, 10 Feb 2023 04:30:53 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2b1iYY1788612xpyToWHiG7p; Fri, 10 Feb 2023 04:30:53 -0800 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web11.13152.1676032252358193350 for ; Fri, 10 Feb 2023 04:30:52 -0800 X-Received: by mail-pl1-f170.google.com with SMTP id o8so3926581pls.11 for ; Fri, 10 Feb 2023 04:30:52 -0800 (PST) X-Gm-Message-State: aOrDcjm560cVfSux8LLVSMPUx1787277AA= X-Google-Smtp-Source: AK7set8lUPaNnv4+rgOFlEnIowIaSHlVazmVz06zPy7Jb3gh/LdeVKUM7FP4qul5zOJjnP33Y7cbnA== X-Received: by 2002:a17:902:d4d1:b0:198:fc83:9139 with SMTP id o17-20020a170902d4d100b00198fc839139mr5120656plg.55.1676032251197; Fri, 10 Feb 2023 04:30:51 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:30:50 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 01/19] MdePkg/Register: Add register definition header files for RISC-V Date: Fri, 10 Feb 2023 18:00:23 +0530 Message-Id: <20230210123041.1489506-2-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032253; bh=WSx+/TvKzOqD6RkuzmSySHhvZp9UDU7iGhlgQ1CUDY8=; h=Cc:Date:From:Reply-To:Subject:To; b=B730j27hMc41goEp9Z8MURun9lsPonbUM4l76rWlo1WMz1SQIDYD0/o4KqlkKbSDvoZ /s1aryVYRtH0hd8hIoD+QOtkgKV9i0GCu9hqFOKMZh77AObjifdBDAAfCqWlKJXIXuzBH 8hNZ2cRTpWRRHWUV+5ph639iPrfT1Z0nWJc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032254870100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Reviewed-by: Michael D Kinney Acked-by: Ard Biesheuvel --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 ++++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ 2 files changed, 144 insertions(+) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..5c2989b797bf --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,119 @@ +/** @file + RISC-V CSR encodings + + Copyright (c) 2019, Western Digital Corporation or its affiliates. All r= ights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_ENCODING_H_ +#define RISCV_ENCODING_H_ + +#define MSTATUS_SIE 0x00000002UL +#define MSTATUS_MIE 0x00000008UL +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE 0x00000040UL +#define MSTATUS_MPIE 0x00000080UL +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (1UL << IRQ_S_SOFT) +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) +#define MIP_MSIP (1UL << IRQ_M_SOFT) +#define MIP_STIP (1UL << IRQ_S_TIMER) +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) +#define MIP_MTIP (1UL << IRQ_M_TIMER) +#define MIP_SEIP (1UL << IRQ_S_EXT) +#define MIP_VSEIP (1UL << IRQ_VS_EXT) +#define MIP_MEIP (1UL << IRQ_M_EXT) +#define MIP_SGEIP (1UL << IRQ_S_GEXT) +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0UL +#define PRV_S 1UL +#define PRV_M 3UL + +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL + +#define SATP_MODE_OFF 0UL +#define SATP_MODE_SV32 1UL +#define SATP_MODE_SV39 8UL +#define SATP_MODE_SV48 9UL +#define SATP_MODE_SV57 10UL +#define SATP_MODE_SV64 11UL + +#define SATP_MODE SATP64_MODE + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* Trap/Exception Causes */ +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..ee5c2ba60377 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,25 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_IMPL_H_ +#define RISCV_IMPL_H_ + +#include + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99982): https://edk2.groups.io/g/devel/message/99982 Mute This Topic: https://groups.io/mt/96874979/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99983+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99983+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032255; cv=none; d=zohomail.com; s=zohoarc; b=aGQm9R91QlRXGddinG8XMnwvBajidlRb44kXODx5oUNM1ojlW9j8XmLKCNapOv0McyiFegapMQTfaCWwRgFgsXCsU7ulkMSGV7GNYWYg9OW9LXydkPt2vrtlVDsDm+7XgmElvSHUYn7xbVPagCuLNjJ5onZwXF1WzwWgphBQ2zg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032255; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZvRyTrHV8lf6jQx8jQK15TAicm7OfPg4iDReYe4yFZU=; b=azK6mzXAdZ5Tlc+ZznvI/gmmeANmspy4eYEIi04wg3uws5Ik3U/Opsw2nQ2HIJg/2PpQLOM9idnzVrEKz1IuABmtB0dsx9d3MnN/vlzNWA3uQ8hbIviDdF5TFJ05GYPD86xAhhV4auihOfDJWJXXf29xBsFf2bli3Rov+wq43MY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99983+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032255347142.76294520248462; Fri, 10 Feb 2023 04:30:55 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id HEIiYY1788612x0ZdpYEvOok; Fri, 10 Feb 2023 04:30:55 -0800 X-Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web11.13153.1676032254471690814 for ; Fri, 10 Feb 2023 04:30:54 -0800 X-Received: by mail-pj1-f43.google.com with SMTP id d13-20020a17090ad3cd00b0023127b2d602so5383170pjw.2 for ; Fri, 10 Feb 2023 04:30:54 -0800 (PST) X-Gm-Message-State: IfVFIyzVBvnG3oOU6cp2Zu1Vx1787277AA= X-Google-Smtp-Source: AK7set9x0w+avBODfFC984qPIPV2iIJ20cq7MCxJj8szPKeaYeIX5GwvcDjITudmYxmgKdxMDfv5og== X-Received: by 2002:a17:902:e38a:b0:198:fd58:ee43 with SMTP id g10-20020a170902e38a00b00198fd58ee43mr10815854ple.12.1676032253751; Fri, 10 Feb 2023 04:30:53 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:30:53 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 02/19] MdePkg/BaseLib: RISC-V: Add few more helper functions Date: Fri, 10 Feb 2023 18:00:24 +0530 Message-Id: <20230210123041.1489506-3-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032255; bh=Sinq8v1jDP2zSgrRKuDeG/ofMDCb9ZW+UmUrRvodAWc=; h=Cc:Date:From:Reply-To:Subject:To; b=mjpnRms+6X4yEed5LR3MmNXS1SLSq9EYg1xWDNnnmk77Gy6cNBk54v4IU5SatllxjX6 FlXwNgR8hvACRnNrzGEBstUWmh2fC0NqYzGClpplzs4o/ENGkCkL+eeiPx9lH3GA08JMh UvU+Z9xh6C5jylFEhVcRBH/RZTNLVfuIB2E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032256959100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Daniel Schaefer Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel Reviewed-by: Michael D Kinney --- MdePkg/Library/BaseLib/BaseLib.inf | 3 ++ MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++ MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++-- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 +++++++++ 6 files changed, 179 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 9ed46a584a14..3a48492b1a01 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,9 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuScratch.S | GCC + RiscV64/ReadTimer.S | GCC + RiscV64/RiscVMmu.S | GCC =20 [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index f3f59f21c2ea..8f2df76c29a3 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -151,6 +151,56 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID +RiscVSetSupervisorScratch ( + IN UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID +RiscVSetSupervisorStvec ( + IN UINT64 + ); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +UINT64 +RiscVGetSupervisorTrapCause ( + VOID + ); + +VOID +RiscVSetSupervisorAddressTranslationRegister ( + IN UINT64 + ); + +UINT64 +RiscVReadTimer ( + VOID + ); + +VOID +RiscVEnableTimerInterrupt ( + VOID + ); + +VOID +RiscVDisableTimerInterrupt ( + VOID + ); + +VOID +RiscVClearPendingTimerInterrupt ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/B= aseLib/RiscV64/CpuScratch.S new file mode 100644 index 000000000000..5492a500eb5e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrw CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/Ba= seLib/RiscV64/ReadTimer.S new file mode 100644 index 000000000000..39a06efa51ef --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// Read CPU timer +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Read TIME CSR. +// @retval a0 : 64-bit timer. +// +ASM_FUNC (RiscVReadTimer) + csrr a0, CSR_TIME + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S index 87b3468fc7fd..6a1b90a7e45c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -8,13 +8,13 @@ // //------------------------------------------------------------------------= ------ =20 +#include + ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) =20 -#define SSTATUS_SIE 0x00000002 -#define CSR_SSTATUS 0x100 - #define SSTATUS_SPP_BIT_POSITION 8 +#define SSTATUS_SPP_BIT_POSITION 8 =20 // // This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap: ret =20 // +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, CSR_STVEC, a0 + ret + +// +// Get Supervisor mode trap vector. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, CSR_STVEC + ret + +// +// Get Supervisor trap cause CSR. +// +ASM_FUNC (RiscVGetSupervisorTrapCause) + csrrs a0, CSR_SCAUSE, 0 + ret +// // This routine returns supervisor mode interrupt // status. // -ASM_PFX(RiscVGetSupervisorModeInterrupts): +ASM_FUNC (RiscVGetSupervisorModeInterrupts) csrr a0, CSR_SSTATUS andi a0, a0, SSTATUS_SIE ret =20 +// +// This routine disables supervisor mode timer interrupt +// +ASM_FUNC (RiscVDisableTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIE, a0 + ret + +// +// This routine enables supervisor mode timer interrupt +// +ASM_FUNC (RiscVEnableTimerInterrupt) + li a0, SIP_STIP + csrs CSR_SIE, a0 + ret + +// +// This routine clears pending supervisor mode timer interrupt +// +ASM_FUNC (RiscVClearPendingTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIP, a0 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/Bas= eLib/RiscV64/RiscVMmu.S new file mode 100644 index 000000000000..ac8f92f38aed --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) + csrw CSR_SATP, a0 + ret --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99983): https://edk2.groups.io/g/devel/message/99983 Mute This Topic: https://groups.io/mt/96874980/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99984+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99984+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032258; cv=none; d=zohomail.com; s=zohoarc; b=fJjvnLwDafJ2EGI7Csb3vs2FVQz3jpza1TZ1kLkmRysJgL6/J4f+/fgk4fdh3G+o4j4SnzwOMv0UmjpFjMfWXNOjhtjKLHhiJMgj2ZiYt4mzQVpdf5CL9a7cPQd8OmaciVwUSxjYc7S90QtaghH/gs4W7CoTE+G06pt2j2MV8Xs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032258; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6U6PdP6063UjVPxYmrpCrG6YuZzX29OvO1tykE2nEts=; b=buIM+p5zzUAzDYYhGXP9/aLDWjsYzvngctr9jxV6jCPW5CwFuWScjtw2DZUeA765Ymyei58kOhIug7CB3mKA79FLNS19gpNiRxW+ww2aX9rudBCC09ByLnMFsptIIUJnezt9DSqEII+3ZjVDhQuh2mG6YD8fdPUQsVz+CpMcH1Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99984+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032258105422.39311845414693; Fri, 10 Feb 2023 04:30:58 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9fUlYY1788612xi5h3bfHJvZ; Fri, 10 Feb 2023 04:30:57 -0800 X-Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web10.13398.1676032256853730884 for ; Fri, 10 Feb 2023 04:30:56 -0800 X-Received: by mail-pj1-f43.google.com with SMTP id gj9-20020a17090b108900b0023114156d36so9189519pjb.4 for ; Fri, 10 Feb 2023 04:30:56 -0800 (PST) X-Gm-Message-State: fuLtKG461XH6VUTitQfajUCPx1787277AA= X-Google-Smtp-Source: AK7set8l/P8ML7O5oVLd9bKSzPv6x+BhMQJ226ZYEYluJdf+mIPvRTbivZzva+o4ceB0Jsy+q5Q0Hw== X-Received: by 2002:a17:902:e1cc:b0:199:554c:1153 with SMTP id t12-20020a170902e1cc00b00199554c1153mr5512470pla.18.1676032256198; Fri, 10 Feb 2023 04:30:56 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:30:55 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 03/19] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Date: Fri, 10 Feb 2023 18:00:25 +0530 Message-Id: <20230210123041.1489506-4-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032257; bh=R52OAOkgnbCmSoEVbP+Y3qPHtp/fYsvt3u4zMJiHRfQ=; h=Cc:Date:From:Reply-To:Subject:To; b=PSg+CA+V/oidN8GxP2xUfz6TiczHcucdms36Uv95lvU5YclK3TkPCAhRUQUOMsPkIU3 HkbxKXVnUjo+IzHyrFXjX8nsw2bVfQ9puEyvIBliYH8wPxr0tKsApDma1sbcGfUGFOL+A ug0VbnkxQiGRd5DTPEWPvPi49ssCg1CpIHI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032258950100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This library is required to make SBI ecalls from the S-mode EDK2. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel Reviewed-by: Michael D Kinney --- MdePkg/MdePkg.dec | 4 + MdePkg/MdePkg.dsc | 3 + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf | 26 +++ MdePkg/Include/Library/BaseRiscVSbiLib.h | 154 +++++++++++++ MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 231 +++++++++++++++++= +++ MdePkg/Library/BaseRiscVSbiLib/RiscVSbiEcall.S | 42 ++++ 6 files changed, 460 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 3d08f20d15b0..ca2e4dcf815c 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -316,6 +316,10 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides function to support TDX processing. TdxLib|Include/Library/TdxLib.h =20 +[LibraryClasses.RISCV64] + ## @libraryclass Provides function to make ecalls to SBI + BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h + [Guids] # # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 32a852dc466e..0ac7618b4623 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -190,4 +190,7 @@ [Components.ARM, Components.AARCH64] MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf =20 +[Components.RISCV64] + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + [BuildOptions] diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf b/MdePkg/Li= brary/BaseRiscVSbiLib/BaseRiscVSbiLib.inf new file mode 100644 index 000000000000..d6fd3f663af1 --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf @@ -0,0 +1,26 @@ +## @file +# RISC-V Library to call SBI ecalls +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D BaseRiscVSbiLib + FILE_GUID =3D D742CF3D-E600-4009-8FB5-318073008508 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSbiLib + +[Sources] + BaseRiscVSbiLib.c + RiscVSbiEcall.S + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib diff --git a/MdePkg/Include/Library/BaseRiscVSbiLib.h b/MdePkg/Include/Libr= ary/BaseRiscVSbiLib.h new file mode 100644 index 000000000000..e75520b4b888 --- /dev/null +++ b/MdePkg/Include/Library/BaseRiscVSbiLib.h @@ -0,0 +1,154 @@ +/** @file + Library to call the RISC-V SBI ecalls + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Hart - Hardware Thread, similar to a CPU core + + Currently, EDK2 needs to call SBI only to set the time and to do system = reset. + +**/ + +#ifndef RISCV_SBI_LIB_H_ +#define RISCV_SBI_LIB_H_ + +#include + +/* SBI Extension IDs */ +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 + +/* SBI function IDs for TIME extension*/ +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for SRST extension */ +#define SBI_EXT_SRST_RESET 0x0 + +#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0 +#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1 +#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2 + +#define SBI_SRST_RESET_REASON_NONE 0x0 +#define SBI_SRST_RESET_REASON_SYSFAIL 0x1 + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + VOID *PrePiHobList; // Pre PI Hob List + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree +} EFI_RISCV_FIRMWARE_CONTEXT; + +// +// EDK2 OpenSBI firmware extension return status. +// +typedef struct { + UINTN Error; ///< SBI status code + UINTN Value; ///< Value returned +} SBI_RET; + +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ); + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ); + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ); + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ); + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ); + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ); + +/** + Make ECALL in assembly + + Switch to M-mode + + @param[in,out] Arg0 + @param[in,out] Arg1 + @param[in] Arg2 + @param[in] Arg3 + @param[in] Arg4 + @param[in] Arg5 + @param[in] FID + @param[in] EXT +**/ +VOID +EFIAPI +RiscVSbiEcall ( + IN OUT UINTN *Arg0, + IN OUT UINTN *Arg1, + IN UINTN Arg2, + IN UINTN Arg3, + IN UINTN Arg4, + IN UINTN Arg5, + IN UINTN Fid, + IN UINTN Ext + ); + +#endif diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c b/MdePkg/Libr= ary/BaseRiscVSbiLib/BaseRiscVSbiLib.c new file mode 100644 index 000000000000..2ba8f5ed366a --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c @@ -0,0 +1,231 @@ +/** @file + Instance of the SBI ecall library. + + It allows calling an SBI function via an ecall from S-Mode. + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +// +// Maximum arguments for SBI ecall +#define SBI_CALL_MAX_ARGS 6 + +/** + Call SBI call using ecall instruction. + + Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS. + + @param[in] ExtId SBI extension ID. + @param[in] FuncId SBI function ID. + @param[in] NumArgs Number of arguments to pass to the ecall. + @param[in] ... Argument list for the ecall. + + @retval Returns SBI_RET structure with value and error code. + +**/ +STATIC +SBI_RET +EFIAPI +SbiCall ( + IN UINTN ExtId, + IN UINTN FuncId, + IN UINTN NumArgs, + ... + ) +{ + UINTN I; + SBI_RET Ret; + UINTN Args[SBI_CALL_MAX_ARGS]; + VA_LIST ArgList; + + VA_START (ArgList, NumArgs); + + if (NumArgs > SBI_CALL_MAX_ARGS) { + Ret.Error =3D SBI_ERR_INVALID_PARAM; + Ret.Value =3D -1; + return Ret; + } + + for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) { + if (I < NumArgs) { + Args[I] =3D VA_ARG (ArgList, UINTN); + } else { + // Default to 0 for all arguments that are not given + Args[I] =3D 0; + } + } + + VA_END (ArgList); + + // ECALL updates the a0 and a1 registers as return values. + RiscVSbiEcall ( + &Args[0], + &Args[1], + Args[2], + Args[3], + Args[4], + Args[5], + (UINTN)(FuncId), + (UINTN)(ExtId) + ); + + Ret.Error =3D Args[0]; + Ret.Value =3D Args[1]; + return Ret; +} + +/** + Translate SBI error code to EFI status. + + @param[in] SbiError SBI error code + @retval EFI_STATUS +**/ +STATIC +EFI_STATUS +EFIAPI +TranslateError ( + IN UINTN SbiError + ) +{ + switch (SbiError) { + case SBI_SUCCESS: + return EFI_SUCCESS; + case SBI_ERR_FAILED: + return EFI_DEVICE_ERROR; + break; + case SBI_ERR_NOT_SUPPORTED: + return EFI_UNSUPPORTED; + break; + case SBI_ERR_INVALID_PARAM: + return EFI_INVALID_PARAMETER; + break; + case SBI_ERR_DENIED: + return EFI_ACCESS_DENIED; + break; + case SBI_ERR_INVALID_ADDRESS: + return EFI_LOAD_ERROR; + break; + case SBI_ERR_ALREADY_AVAILABLE: + return EFI_ALREADY_STARTED; + break; + default: + // + // Reaches here only if SBI has defined a new error type + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + break; + } +} + +/** + Clear pending timer interrupt bit and set timer for next event after Tim= e. + + To clear the timer without scheduling a timer event, set Time to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] Time The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ) +{ + SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time); +} + +/** + Reset the system using SRST SBI extenion + + @param[in] ResetType The SRST System Reset Type. + @param[in] ResetReason The SRST System Reset Reason. +**/ +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ) +{ + SBI_RET Ret; + + Ret =3D SbiCall ( + SBI_EXT_SRST, + SBI_EXT_SRST_RESET, + 2, + ResetType, + ResetReason + ); + + return TranslateError (Ret.Error); +} + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ) +{ + *FirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT *)RiscVGetSupervisorScr= atch (); +} + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + RiscVSetSupervisorScratch ((UINT64)FirmwareContext); +} + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + GetFirmwareContext (FirmwareContextPtr); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + SetFirmwareContext (FirmwareContextPtr); +} diff --git a/MdePkg/Library/BaseRiscVSbiLib/RiscVSbiEcall.S b/MdePkg/Librar= y/BaseRiscVSbiLib/RiscVSbiEcall.S new file mode 100644 index 000000000000..8ba69f8512a5 --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/RiscVSbiEcall.S @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------= ------ +// +// Make ECALL to SBI +// +// Copyright (c) 2023, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Make ECALL to SBI +// ecall updates the same a0 and a1 registers with +// return values. Hence, the C function which calls +// this should pass the address of Arg0 and Arg1. +// This routine saves the address and updates it +// with a0 and a1 once ecall returns. +// +// @param a0 : Pointer to Arg0 +// @param a1 : Pointer to Arg1 +// @param a2 : Arg2 +// @param a3 : Arg3 +// @param a4 : Arg4 +// @param a5 : Arg5 +// @param a6 : FunctionID +// @param a7 : ExtensionId +// +ASM_FUNC (RiscVSbiEcall) + mv t0, a0 + mv t1, a1 + ld a0, 0(a0) + ld a1, 0(a1) + ecall + sd a0, 0(t0) + sd a1, 0(t1) + ret --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99984): https://edk2.groups.io/g/devel/message/99984 Mute This Topic: https://groups.io/mt/96874981/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99985+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99985+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032260; cv=none; d=zohomail.com; s=zohoarc; b=UCtiVypWmsZJ0dxoVDppWxzNmYfABniKqMlKOjTmrl0mauk63V8KXY1yamXhGB9F18JdGF3qpzd4an3ZJpsD3RcKvmJlkDRH3qRu6d+kMFVTkSi6LiHOkjPMRUw0zgayHR5DC3klQSx8Ig8jrnZIkp/3vIBrJzhzCDNyuL/Wtf4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032260; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0OxoTTYbpNAhkCnzn/Foj85UPqNqql3pLtYYwic0Mh4=; b=WiFR9YmuxH1N83KG/P7FILwstlPhn+Qj1q0jhgPf5+Fs40sC9wh3j+rZ7uIrPuMeuVPC1mBbo+LybOcKH+nGpsqtZpNR5yLIuHHPicfhiCdVOtUyBK7WgGG1B/2MTtZFSw/jgkwkqV5JLcW5bIQLXV0G8plKgIMp6ZjbzBV81XA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99985+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032260827306.03969924460307; Fri, 10 Feb 2023 04:31:00 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7mynYY1788612xV45vuUJoVI; Fri, 10 Feb 2023 04:31:00 -0800 X-Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mx.groups.io with SMTP id smtpd.web10.13404.1676032259676605953 for ; Fri, 10 Feb 2023 04:30:59 -0800 X-Received: by mail-pj1-f48.google.com with SMTP id z14-20020a17090abd8e00b00233bb9d6bdcso189288pjr.4 for ; Fri, 10 Feb 2023 04:30:59 -0800 (PST) X-Gm-Message-State: wuleNX8wD9S1fZI5s3xJ78OQx1787277AA= X-Google-Smtp-Source: AK7set/V8VrVolNbFEsQ3Fg+zG4Vzjd3KZx10qyAEyQemD8os4sz5kL863ZImvo3GhnMLs9OTsDFsQ== X-Received: by 2002:a17:902:dac6:b0:196:59a0:bffe with SMTP id q6-20020a170902dac600b0019659a0bffemr17589488plx.17.1676032259014; Fri, 10 Feb 2023 04:30:59 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:30:58 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Gerd Hoffmann , Abner Chang , Heinrich Schuchardt , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 04/19] UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Date: Fri, 10 Feb 2023 18:00:26 +0530 Message-Id: <20230210123041.1489506-5-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032260; bh=ybXbNnTQy/hNaUm2nivh9zF6pmTAbTSsEAczSsNHeMs=; h=Cc:Date:From:Reply-To:Subject:To; b=ZUvst/zTgmasERDT7dTV2ogG++D7K6sTjc1O4tvJ4WwAw9/nWoMltBJERMKeG9nwrMH 3bzKbPn90zB1Afxt8dI77qHnheg6yheiY/yxGrnTk2T+J4pMgG8mOt9y2P1HmGPWnblFM cqXGySkSTJe6SaeV+lYPyWSUAYthTnQW7hI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032262940100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Heinrich Schuchardt Reviewed-by: Andrei Warkentin Acked-by: Ray Ni Acked-by: Ard Biesheuvel --- UefiCpuPkg/UefiCpuPkg.dec | 7 ++++ UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h | 34 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d5283e..903ad52da91b 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -86,6 +86,13 @@ [Protocols] ## Include/Protocol/SmMonitorInit.h gEfiSmMonitorInitProtocolGuid =3D { 0x228f344d, 0xb3de, 0x43bb, { 0xa4,= 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }} =20 +[Protocols.RISCV64] + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid =3D { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x9= 5, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }} + # # [Error.gUefiCpuPkgTokenSpaceGuid] # 0x80000001 | Invalid value provided. diff --git a/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h b/UefiCpuPkg/I= nclude/Protocol/RiscVBootProtocol.h new file mode 100644 index 000000000000..ed223b852d34 --- /dev/null +++ b/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,34 @@ +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + @par Revision Reference: + The protocol specification can be found at + https://github.com/riscv-non-isa/riscv-uefi + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_BOOT_PROTOCOL_H_ +#define RISCV_BOOT_PROTOCOL_H_ + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 +#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID)( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99985): https://edk2.groups.io/g/devel/message/99985 Mute This Topic: https://groups.io/mt/96874984/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99986+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99986+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032263; cv=none; d=zohomail.com; s=zohoarc; b=NhG71oJRzI2keq5x3F52QTkDtY6u6yevHoeKkL9ZbxHyldO8y14iTwJsLsuCSLreG23V8R5VLokcZEOLiRxD5c3sFwx6N0QzPTbhcL29f6dTbLCegZy/kraZTp7BC+aFQt4TH8n3lkODqfU87Gr8u0r57M/K4y7vuq6mH7+3a/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032263; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=q4ubFgx5rYUX7RUXu3ZnDA1VamKQk2oqw3eK19o8R0w=; b=jcMh/aYwnIMVTKQYAHL4U6nT+vFlN/C4mFR9S9+2A7OgEtdclJRimYRUAVSsQyAG7iJeZVUdi/hl5PU155A/rdslNfvozDA3F5k9Wql4howCNr9wh2Av7YSKvey9T69bVUPXuTYCQPBw6DT60Esm3LOJtp8gQ0VvO1QXbhcn8ak= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99986+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032263778867.3560478868856; Fri, 10 Feb 2023 04:31:03 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id KIrcYY1788612xcgC0NQHeyh; Fri, 10 Feb 2023 04:31:03 -0800 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web10.13406.1676032262651757591 for ; Fri, 10 Feb 2023 04:31:02 -0800 X-Received: by mail-pl1-f170.google.com with SMTP id be8so6296439plb.7 for ; Fri, 10 Feb 2023 04:31:02 -0800 (PST) X-Gm-Message-State: pEODvZolOzRGj2xzNA8FFkGLx1787277AA= X-Google-Smtp-Source: AK7set+uYz04j6WH5lyEpLLiO7S46iIaInK2433EyGHzH7NUEvLbVlfZ91218Iq6UBZbW8FI/Rypfw== X-Received: by 2002:a17:903:1d2:b0:196:2ade:6e21 with SMTP id e18-20020a17090301d200b001962ade6e21mr17796175plh.14.1676032261927; Fri, 10 Feb 2023 04:31:01 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:01 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang , Gerd Hoffmann , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 05/19] UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLib Date: Fri, 10 Feb 2023 18:00:27 +0530 Message-Id: <20230210123041.1489506-6-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032263; bh=eEUmHRE8DqXJoI/TrHeYZ+T2y5GJaWa0rUMkFaKPuiU=; h=Cc:Date:From:Reply-To:Subject:To; b=JXvgs9HkALCAygKYfeg4HbJ2LRmDwwNN0Q7IvE1BChbYk0CZdvOuGE+TZx0tjTBfM7X W5kfRVkEflqLvL2uF7tx++KYxMzQzHI0rDxIT0Ya3N3ObRW7J7MbN7OjIH4xLFIoOmQ2N qhV47AQPj6HO5Ty5iUmfsCKoapRFnhVl3J0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032265001100006 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add Cpu Exception Handler library for RISC-V. This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel Acked-by: Ray Ni --- UefiCpuPkg/UefiCpuPkg.dsc = | 3 + UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExcepti= onHandlerLib.inf | 42 +++++++ UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLi= b.h | 116 +++++++++++++++++ UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLi= b.c | 133 ++++++++++++++++++++ UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExcepti= onHandlerLib.uni | 13 ++ UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler= .S | 105 ++++++++++++++++ 6 files changed, 412 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f9a46089d2c7..35e66d93efa6 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -195,5 +195,8 @@ [Components.IA32, Components.X64] [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandle= rLibUnitTest.inf =20 +[Components.RISCV64] + UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExcep= tionHandlerLib.inf + [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV= 64CpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHa= ndlerLib/BaseRiscV64CpuExceptionHandlerLib.inf new file mode 100644 index 000000000000..d80462943645 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuEx= ceptionHandlerLib.inf @@ -0,0 +1,42 @@ +## @file +# RISC-V CPU Exception Handler Library +# +# Copyright (c) 2022-2023, Ventana Micro Systems Inc. All rights reserved.=
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseRiscV64CpuExceptionHandlerLib + MODULE_UNI_FILE =3D BaseRiscV64CpuExceptionHandlerLib.uni + FILE_GUID =3D 6AB0D5FD-E615-45A3-9374-E284FB061FC9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CpuExceptionHandlerLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + SupervisorTrapHandler.S + CpuExceptionHandlerLib.c + CpuExceptionHandlerLib.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + SerialPortLib + PrintLib + SynchronizationLib + PeCoffGetEntryPointLib + MemoryAllocationLib + DebugLib diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExcept= ionHandlerLib.h b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuE= xceptionHandlerLib.h new file mode 100644 index 000000000000..30f47e87552b --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHand= lerLib.h @@ -0,0 +1,116 @@ +/** @file + + RISC-V Exception Handler library definition file. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_ +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_ + +#include + +/** + Trap Handler for S-mode + +**/ +VOID +SupervisorModeTrap ( + VOID + ); + +// +// Index of SMode trap register +// +#define SMODE_TRAP_REGS_zero 0 +#define SMODE_TRAP_REGS_ra 1 +#define SMODE_TRAP_REGS_sp 2 +#define SMODE_TRAP_REGS_gp 3 +#define SMODE_TRAP_REGS_tp 4 +#define SMODE_TRAP_REGS_t0 5 +#define SMODE_TRAP_REGS_t1 6 +#define SMODE_TRAP_REGS_t2 7 +#define SMODE_TRAP_REGS_s0 8 +#define SMODE_TRAP_REGS_s1 9 +#define SMODE_TRAP_REGS_a0 10 +#define SMODE_TRAP_REGS_a1 11 +#define SMODE_TRAP_REGS_a2 12 +#define SMODE_TRAP_REGS_a3 13 +#define SMODE_TRAP_REGS_a4 14 +#define SMODE_TRAP_REGS_a5 15 +#define SMODE_TRAP_REGS_a6 16 +#define SMODE_TRAP_REGS_a7 17 +#define SMODE_TRAP_REGS_s2 18 +#define SMODE_TRAP_REGS_s3 19 +#define SMODE_TRAP_REGS_s4 20 +#define SMODE_TRAP_REGS_s5 21 +#define SMODE_TRAP_REGS_s6 22 +#define SMODE_TRAP_REGS_s7 23 +#define SMODE_TRAP_REGS_s8 24 +#define SMODE_TRAP_REGS_s9 25 +#define SMODE_TRAP_REGS_s10 26 +#define SMODE_TRAP_REGS_s11 27 +#define SMODE_TRAP_REGS_t3 28 +#define SMODE_TRAP_REGS_t4 29 +#define SMODE_TRAP_REGS_t5 30 +#define SMODE_TRAP_REGS_t6 31 +#define SMODE_TRAP_REGS_sepc 32 +#define SMODE_TRAP_REGS_sstatus 33 +#define SMODE_TRAP_REGS_sie 34 +#define SMODE_TRAP_REGS_last 35 + +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__) +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last) + +#pragma pack(1) +typedef struct { + // + // Below are follow the format of EFI_SYSTEM_CONTEXT + // + UINT64 zero; + UINT64 ra; + UINT64 sp; + UINT64 gp; + UINT64 tp; + UINT64 t0; + UINT64 t1; + UINT64 t2; + UINT64 s0; + UINT64 s1; + UINT64 a0; + UINT64 a1; + UINT64 a2; + UINT64 a3; + UINT64 a4; + UINT64 a5; + UINT64 a6; + UINT64 a7; + UINT64 s2; + UINT64 s3; + UINT64 s4; + UINT64 s5; + UINT64 s6; + UINT64 s7; + UINT64 s8; + UINT64 s9; + UINT64 s10; + UINT64 s11; + UINT64 t3; + UINT64 t4; + UINT64 t5; + UINT64 t6; + // + // Below are the additional information to + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap + // and not public to EFI environment. + // + UINT64 sepc; + UINT64 sstatus; + UINT64 sie; +} SMODE_TRAP_REGISTERS; +#pragma pack() + +#endif diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExcept= ionHandlerLib.c b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuE= xceptionHandlerLib.c new file mode 100644 index 000000000000..f1ee7d236aec --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHand= lerLib.c @@ -0,0 +1,133 @@ +/** @file + RISC-V Exception Handler library implementation. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "CpuExceptionHandlerLib.h" + +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; + +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + RiscVSetSupervisorStvec ((UINT64)SupervisorModeTrap); + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler)); + mInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} + +/** + Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. + + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. + + @retval EFI_SUCCESS The stacks are assigned successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. +**/ +EFI_STATUS +EFIAPI +InitializeSeparateExceptionStacks ( + IN VOID *Buffer, + IN OUT UINTN *BufferSize + ) +{ + return EFI_SUCCESS; +} + +/** + Supervisor mode trap handler. + + @param[in] SmodeTrapReg Registers before trap occurred. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + SMODE_TRAP_REGISTERS *SmodeTrapReg + ) +{ + UINTN SCause; + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg; + // + // Check scasue register. + // + SCause =3D (UINTN)RiscVGetSupervisorTrapCause (); + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) { + // + // This is interrupt event. + // + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1)); + if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) { + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext); + } + } +} diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV= 64CpuExceptionHandlerLib.uni b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHa= ndlerLib/BaseRiscV64CpuExceptionHandlerLib.uni new file mode 100644 index 000000000000..00cca2213096 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuEx= ceptionHandlerLib.uni @@ -0,0 +1,13 @@ +// /** @file +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Except= ion Handler Librarys." + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Except= ion Handler Librarys." + diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/Superviso= rTrapHandler.S b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/Super= visorTrapHandler.S new file mode 100644 index 000000000000..649c4c5becf4 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHa= ndler.S @@ -0,0 +1,105 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuExceptionHandlerLib.h" + + .align 3 + .section .entry, "ax", %progbits + .globl SupervisorModeTrap +SupervisorModeTrap: + addi sp, sp, -SMODE_TRAP_REGS_SIZE + + /* Save all general regisers except SP */ + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + csrr t0, CSR_SSTATUS + and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE) + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + csrr t0, CSR_SEPC + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrr t0, CSR_SIE + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP */ + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrw CSR_SEPC, t0 + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + csrw CSR_SIE, t0 + csrr t0, CSR_SSTATUS + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + or t0, t0, t1 + csrw CSR_SSTATUS, t0 + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + addi sp, sp, SMODE_TRAP_REGS_SIZE + sret --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99986): https://edk2.groups.io/g/devel/message/99986 Mute This Topic: https://groups.io/mt/96874985/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99987+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99987+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032266; cv=none; d=zohomail.com; s=zohoarc; b=LsZAmHNBcFcAaU6SbnGBAAI35X+05+ZlUwjZDksr6AVTFP2Ng2lnstQRPecLozQ7ZwlLqpgg0Dg2i9TwMW5pZYixOohprZ5IBNMOeUd7NN/yFugkGcbb3LFDiZA/hrOMonyIni0Is+Txz0LD7vCIXBMavU41x73UyhKHMJ6CyaQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032266; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4sdnfxX2nn+YTbgiyR69LpiXzRDUmtuCnUGTs1o5A1Q=; b=YQXn00YgoKVXLL8NZ8/G/5qPKTEoyDfABsuFJSqASaHcBMakW50hTt3Ga4OmBeHIxvRru3nPDR+XcQFImpUIaKPIDAZdXYSWZ1JIELlXEi4p5dCFEOkWkyRawfYsQJhzdNC7NTz3U6o7IegkUCDk/qnckovs+sJkBuysSp0RdEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99987+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032266396356.4908393205543; Fri, 10 Feb 2023 04:31:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ivdmYY1788612xWcQGeeRQNY; Fri, 10 Feb 2023 04:31:05 -0800 X-Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mx.groups.io with SMTP id smtpd.web11.13157.1676032265350517424 for ; Fri, 10 Feb 2023 04:31:05 -0800 X-Received: by mail-pj1-f48.google.com with SMTP id rm7-20020a17090b3ec700b0022c05558d22so5350922pjb.5 for ; Fri, 10 Feb 2023 04:31:05 -0800 (PST) X-Gm-Message-State: X6m61UY7uXGzO7IxrlL6TRqfx1787277AA= X-Google-Smtp-Source: AK7set9Fx3ekmz+KZI1a6mECXC5BhSoLmMzoIymZfonmUZCQXKmIDSyAfhLEJQy9urFCANpYV1NGhw== X-Received: by 2002:a17:902:ce86:b0:198:adc4:228b with SMTP id f6-20020a170902ce8600b00198adc4228bmr10222138plg.6.1676032264636; Fri, 10 Feb 2023 04:31:04 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:04 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang , Gerd Hoffmann , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 06/19] UefiCpuPkg: Add BaseRiscV64CpuTimerLib library Date: Fri, 10 Feb 2023 18:00:28 +0530 Message-Id: <20230210123041.1489506-7-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032265; bh=LbtpiNQ8vTON4cfNRmjvZ3tntQpy1qodXhSvqDqulXo=; h=Cc:Date:From:Reply-To:Subject:To; b=FWLu7sg2WtxUdT4rGc6+maXXGJbDHLnQLAkzfpxE1oQrotnPGNQudroo6CDjzF58lgt qX1SvoMV1D/PcHRBoMXrVKq9PB+2R/lPb/iQVv3T6U5nNghAtFKuNzhqsLoAbnq9/Ik+a vpyR1/zeg9HobvtjPS+AVTSbl6iN0TOCAk0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032266972100009 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add the RISC-V instance of the TimerLib. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel Acked-by: Ray Ni --- UefiCpuPkg/UefiCpuPkg.dsc | 1= + UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf | 33= ++++ UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c | 199= ++++++++++++++++++++ UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni | 14= ++ 4 files changed, 247 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 35e66d93efa6..c511403842b8 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -197,6 +197,7 @@ [Components.X64] =20 [Components.RISCV64] UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExcep= tionHandlerLib.inf + UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerL= ib.inf b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.i= nf new file mode 100644 index 000000000000..3d5eaa41716d --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf @@ -0,0 +1,33 @@ +## @file +# RISC-V Base CPU Timer Library Instance +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseRisV64CpuTimerLib + FILE_GUID =3D B635A600-EA24-4199-88E8-5761EEA96A51 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + MODULE_UNI_FILE =3D BaseRisV64CpuTimerLib.uni + +[Sources] + CpuTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c b/Uefi= CpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c new file mode 100644 index 000000000000..9c8efc0f3530 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c @@ -0,0 +1,199 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D RiscVReadTimer () + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS = - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuC= oreCrystalClockFrequency), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= PcdGet64 (PcdCpuCoreCrystalClockFrequency)); + + return NanoSeconds; +} diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerL= ib.uni b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.u= ni new file mode 100644 index 000000000000..bb061f9a8ff0 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni @@ -0,0 +1,14 @@ +// /** @file +// Base CPU Timer Library for RISC-V +// +// Copyright (c) 2023, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Timer = Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti= mer support for RISC-V." + --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99987): https://edk2.groups.io/g/devel/message/99987 Mute This Topic: https://groups.io/mt/96874986/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99988+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99988+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032269; cv=none; d=zohomail.com; s=zohoarc; b=lfCzQOwxD4muDaNbSzonRC43lpc/IlLcO4MFZvWCFj6lkLPU4ZYBICg0QiJdORfaQF9aB8j/bf6sNLi5C9GQ99lLZ6JEbvSjLT0a8Op1mX65WfonqlY1ZLJs+uq7sqBJwaxr6DxQHwXardT5JsTLda4ONh2zXh8nIpSAT4jzhhU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032269; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=LDEqcpjCCuJCboXtdamOkGCvab008gFlio/lNZc54MI=; b=DasvTDyI1j4u/j5jA67bhl3k7AefogdQ4pXsJ2ojqCj9uPVSb7zzt4gChgXVSfVeSD+Ul+GeMseemRoH246FNX7uTipAhA29pXzjc8BLjO+NtWpj31yEe06+hJG9SaIAXO6Vv4zlAEetbEU19UArZZXlhrPV/xgkt32Vlz7SYOQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99988+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032269767966.7737672642062; Fri, 10 Feb 2023 04:31:09 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Kt7VYY1788612xxykvhVnRv7; Fri, 10 Feb 2023 04:31:09 -0800 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web11.13152.1676032252358193350 for ; Fri, 10 Feb 2023 04:31:08 -0800 X-Received: by mail-pl1-f170.google.com with SMTP id o8so3927330pls.11 for ; Fri, 10 Feb 2023 04:31:08 -0800 (PST) X-Gm-Message-State: VEq9sigmgX7PzRc97csLoUpHx1787277AA= X-Google-Smtp-Source: AK7set/R6hciqNKBfYPj6CZuTrwdvZR8xag0763nCB72CoKcdnaH/ec2myoNa9IdYyFKoYEly76orw== X-Received: by 2002:a17:903:4091:b0:19a:73f7:675f with SMTP id z17-20020a170903409100b0019a73f7675fmr1302832plc.60.1676032267587; Fri, 10 Feb 2023 04:31:07 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:07 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 07/19] UefiCpuPkg: Add CpuTimerDxeRiscV64 module Date: Fri, 10 Feb 2023 18:00:29 +0530 Message-Id: <20230210123041.1489506-8-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032269; bh=4BOSf3R8P2RPBTvnQG+oNmJ63V03c1hgCwlhfpjXFoc=; h=Cc:Date:From:Reply-To:Subject:To; b=V4ln9u5wzwKFeAmW4Lt2j9e+YNAx2vNwxuX+29pkwHB5oCNTgmvSd7TbjG1WPGYbPEd IwSy95pchFqG7fYXhoIUYro0YarSwqPNwnlCJ2Ro16OxrIxRt/LdaUs5z79BcWbXbA0mP 9Mwq7WheFFdfCde7QFKKUMztLSNIVIrU2Ps= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032271043100014 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel Acked-by: Ray Ni --- UefiCpuPkg/UefiCpuPkg.dsc | 1 + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 51 ++++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 177 ++++++++++++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 294 +++++++++++++++= +++++ UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimer.uni | 14 + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerExtra.uni | 12 + 6 files changed, 549 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index c511403842b8..aba5ae927586 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -198,6 +198,7 @@ [Components.X64] [Components.RISCV64] UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExcep= tionHandlerLib.inf UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpu= Pkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf new file mode 100644 index 000000000000..2c1f9f10e165 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf @@ -0,0 +1,51 @@ +## @file +# Timer Arch protocol module +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVTimerDxe + MODULE_UNI_FILE =3D RiscVTimer.uni + FILE_GUID =3D 055DDAC6-9142-4013-BF20-FC2E5BC325C9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D TimerDriverInitialize +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + CpuLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Sources.RISCV64] + Timer.h + Timer.c + +[Protocols] + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiTimerArchProtocolGuid ## PRODUCES + +[Depex] + gEfiCpuArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVTimerExtra.uni diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxe= RiscV64/Timer.h new file mode 100644 index 000000000000..586eb0cfadb4 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h @@ -0,0 +1,177 @@ +/** @file + RISC-V Timer Architectural Protocol definitions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TIMER_H_ +#define TIMER_H_ + +#include + +#include +#include + +#include +#include +#include +#include + +// +// RISC-V use 100us timer. +// The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units +// +#define DEFAULT_TIMER_TICK_DURATION 100000 + +extern VOID +RiscvSetTimerPeriod ( + UINT32 TimerPeriod + ); + +// +// Function Prototypes +// + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +; + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +; + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +; + +#endif diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxe= RiscV64/Timer.c new file mode 100644 index 000000000000..db153f715e60 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c @@ -0,0 +1,294 @@ +/** @file + RISC-V Timer Architectural Protocol + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "Timer.h" + +// +// The handle onto which the Timer Architectural Protocol will be installed +// +STATIC EFI_HANDLE mTimerHandle =3D NULL; + +// +// The Timer Architectural Protocol that this driver produces +// +EFI_TIMER_ARCH_PROTOCOL mTimer =3D { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +// +// Pointer to the CPU Architectural Protocol instance +// +EFI_CPU_ARCH_PROTOCOL *mCpu; + +// +// The notification function to call on every timer interrupt. +// A bug in the compiler prevents us from initializing this here. +// +STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; + +// +// The current period of the timer interrupt +// +STATIC UINT64 mTimerPeriod =3D 0; + +/** + Timer Interrupt Handler. + + @param InterruptType The type of interrupt that occured + @param SystemContext A pointer to the system context when the interru= pt occured +**/ +VOID +EFIAPI +TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 RiscvTimer; + + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + if (mTimerNotifyFunction !=3D NULL) { + mTimerNotifyFunction (mTimerPeriod); + } + + RiscVDisableTimerInterrupt (); // Disable SMode timer int + RiscVClearPendingTimerInterrupt (); + if (mTimerPeriod =3D=3D 0) { + gBS->RestoreTPL (OriginalTPL); + RiscVDisableTimerInterrupt (); // Disable SMode timer int + return; + } + + RiscvTimer =3D RiscVReadTimer (); + SbiSetTimer (RiscvTimer +=3D mTimerPeriod); + gBS->RestoreTPL (OriginalTPL); + RiscVEnableTimerInterrupt (); // enable SMode timer int +} + +/** + + This function registers the handler NotifyFunction so it is called every= time + the timer interrupt fires. It also passes the amount of time since the = last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS= is + returned. If the CPU does not support registering a timer interrupt han= dler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a h= andler + when a handler is already registered, then EFI_ALREADY_STARTED is return= ed. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ER= ROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fire= s. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so i= t can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support time= r interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a = handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a hand= ler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be reg= istered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", Notify= Function)); + mTimerNotifyFunction =3D NotifyFunction; + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 RiscvTimer; + + DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod)); + + if (TimerPeriod =3D=3D 0) { + mTimerPeriod =3D 0; + RiscVDisableTimerInterrupt (); // Disable SMode timer int + return EFI_SUCCESS; + } + + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us + RiscvTimer =3D RiscVReadTimer (); + SbiSetTimer (RiscvTimer + mTimerPeriod); + + mCpu->EnableInterrupt (mCpu); + RiscVEnableTimerInterrupt (); // enable SMode timer int + return EFI_SUCCESS; +} + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + *TimerPeriod =3D mTimerPeriod; + return EFI_SUCCESS; +} + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize the pointer to our notify function. + // + mTimerNotifyFunction =3D NULL; + + // + // Make sure the Timer Architectural Protocol is not already installed i= n the system + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid); + + // + // Find the CPU architectural protocol. + // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= )&mCpu); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be disabled + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, 0); + ASSERT_EFI_ERROR (Status); + + // + // Install interrupt handler for RISC-V Timer. + // + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be enabled at its default period + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATI= ON); + ASSERT_EFI_ERROR (Status); + + // + // Install the Timer Architectural Protocol onto a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mTimerHandle, + &gEfiTimerArchProtocolGuid, + &mTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimer.uni b/UefiCpuPkg/CpuTim= erDxeRiscV64/CpuTimer.uni new file mode 100644 index 000000000000..76de1f3f352a --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimer.uni @@ -0,0 +1,14 @@ +// /** @file +// +// Timer Arch protocol strings. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Timer driver that= provides Timer Arch protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "Timer driver that= provides Timer Arch protocol." diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerExtra.uni b/UefiCpuPkg/C= puTimerDxeRiscV64/CpuTimerExtra.uni new file mode 100644 index 000000000000..ceb93a7ce82f --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// Timer Localized Strings and Content +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Timer DXE Driver" --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99988): https://edk2.groups.io/g/devel/message/99988 Mute This Topic: https://groups.io/mt/96874987/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99989+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99989+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032273; cv=none; d=zohomail.com; s=zohoarc; b=IeGAl/wE2j2lR95d54GdneAmJbC9Q5IdhkxCVhpWzTHSL1qttSeC6u8I1f7FaxWQO6NCDyVXqBLTCtE2eYUbV3eK5WH1FTmGTllLMT5UGpSy6Iym9Why9ZYEvJ+2X6chMynLIw8RyDnT5XGlny/L9df8BaPCc60C9HMWDcQP1RQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032273; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=So308fMUoRMpnYriEH7L6YFWG1lpJrd8HHg8bgoWO9w=; b=mQBnRk0EXDUkF+JWc5A9qxQsD0EuNHWbTonc2q++zkI+V6i5Vdutv6bj8hEhRp9t6rgbaNn8wH4GZ9B5/yw4Amzs+01JOHRGVNCcK9TEJQTwVIHAIdyToeuMA0TODvfCQh2SReIP+EDC0iUm7d4t4n4NufyuljWvZsbrvFf/Fnw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99989+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032273639935.705912448901; Fri, 10 Feb 2023 04:31:13 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id pWvdYY1788612xMYegEYACvf; Fri, 10 Feb 2023 04:31:11 -0800 X-Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by mx.groups.io with SMTP id smtpd.web10.13408.1676032271142821502 for ; Fri, 10 Feb 2023 04:31:11 -0800 X-Received: by mail-pj1-f50.google.com with SMTP id n20-20020a17090aab9400b00229ca6a4636so9672259pjq.0 for ; Fri, 10 Feb 2023 04:31:11 -0800 (PST) X-Gm-Message-State: CQ9hHiaBZg70RVoRnfns1Weex1787277AA= X-Google-Smtp-Source: AK7set/cNdVf0plv59iQdr6krXK82J8pjTNE07DbA9cIgw9K5Lb64HbyBQfucgnfg0l2GBRLMqjywg== X-Received: by 2002:a17:902:c40d:b0:199:2f45:1d41 with SMTP id k13-20020a170902c40d00b001992f451d41mr18495197plk.62.1676032270345; Fri, 10 Feb 2023 04:31:10 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:10 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 08/19] UefiCpuPkg: Add CpuDxeRiscV64 module Date: Fri, 10 Feb 2023 18:00:30 +0530 Message-Id: <20230210123041.1489506-9-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032271; bh=Y7nxS0CXChht9PTtNpRbdrcl8Pmk1f4bLH23j4C00U0=; h=Cc:Date:From:Reply-To:Subject:To; b=T215U94paxMiH5NWQbM2YIYar/pRdcHphGWfauOF7XCHqbHLxkIInLFtiVf6U/H6jt3 WtDk4VITJE69nYTSl3Nlik/Xue8kdkNTzJM1v874uFRAfOYsC0Cli1bypjKrvLQc6gVnU LSZ/76GCWxIm+o3gUdhLA5ZcSEpek/5rDJw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032275076100021 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe and added the RISCV_EFI_BOOT_PROTOCOL support. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- UefiCpuPkg/UefiCpuPkg.dsc | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 68 ++++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 199 +++++++++++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 365 ++++++++++++++++++++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.uni | 13 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeExtra.uni | 14 + 6 files changed, 660 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index aba5ae927586..a7318d3fe9db 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -199,6 +199,7 @@ [Components.RISCV64] UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExcep= tionHandlerLib.inf UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxe= RiscV64/CpuDxeRiscV64.inf new file mode 100644 index 000000000000..befe23384c1a --- /dev/null +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf @@ -0,0 +1,68 @@ +## @file +# RISC-V CPU DXE module. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D CpuDxeRiscV64 + MODULE_UNI_FILE =3D CpuDxe.uni + FILE_GUID =3D BDEA19E2-778F-473C-BF82-5E38D6A27765 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeCpu + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + CpuExceptionHandlerLib + HobLib + ReportStatusCodeLib + TimerLib + PeCoffGetEntryPointLib + RiscVSbiLib + +[Sources] + CpuDxe.c + CpuDxe.h + +[Protocols] + gEfiCpuArchProtocolGuid ## PRODUCES + gRiscVEfiBootProtocolGuid ## PRODUCES + +[Guids] + gIdleLoopEventGuid ## CONSUMES ## E= vent + +[Ppis] + gEfiSecPlatformInformation2PpiGuid ## UNDEFINED # HOB + gEfiSecPlatformInformationPpiGuid ## UNDEFINED # HOB + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##= CONSUMES + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + CpuDxeExtra.uni diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/C= puDxe.h new file mode 100644 index 000000000000..49f4e119665a --- /dev/null +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -0,0 +1,199 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef CPU_DXE_H_ +#define CPU_DXE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/C= puDxe.c new file mode 100644 index 000000000000..7551e0653603 --- /dev/null +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -0,0 +1,365 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuDxe.h" + +// +// Global Variables +// +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is = not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + mInterruptState =3D TRUE; + return EFI_SUCCESS; +} + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + mInterruptState =3D FALSE; + return EFI_SUCCESS; +} + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D mInterruptState; + return EFI_SUCCESS; +} + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + if (TimerValue =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (TimerIndex !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + *TimerValue =3D (UINT64)RiscVReadTimer (); + if (TimerPeriod !=3D NULL) { + *TimerPeriod =3D DivU64x32 ( + 1000000000000000u, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ); + } + + return EFI_SUCCESS; +} + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__)); + return EFI_SUCCESS; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + InitializeCpuExceptionHandlers (NULL); + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + // + // Install Boot protocol + // + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, + &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.uni b/UefiCpuPkg/CpuDxeRiscV64= /CpuDxe.uni new file mode 100644 index 000000000000..460141a1aae6 --- /dev/null +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.uni @@ -0,0 +1,13 @@ +// /** @file +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V C= PU Architecture Protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver= installs CPU Architecture Protocol." + diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeExtra.uni b/UefiCpuPkg/CpuDxeRi= scV64/CpuDxeExtra.uni new file mode 100644 index 000000000000..6f819f068e0f --- /dev/null +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeExtra.uni @@ -0,0 +1,14 @@ +// /** @file +// CpuDxe Localized Strings and Content +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"RISC-V Architectural DXE Driver" + + --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99989): https://edk2.groups.io/g/devel/message/99989 Mute This Topic: https://groups.io/mt/96874988/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99990+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99990+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032274; cv=none; d=zohomail.com; s=zohoarc; b=Pr9qAPFBvfywbFSftGjmXAqIKdZESgiTJxsk8g83YYK/Aw2ITudgNVSEdsc9XDlu04NjYF1/Qn9BvyhhwsMEiMi91IXIBr8aBXBoiPDWj2hWWcsK0ftMX9l46AVdqrSHDyO5RJhOhAwsNgqjVkNmaE0jY7RK4b+QZlo3EN8s9ew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032274; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=2d6cE6KRAxds7XZty+IhQ4OrlP99hJfKJYWVmtu34rg=; b=BmMSsiky39gDiq36a/1ph9SXeoIL2LmFVi85VKo2lIuCU+0wUqx8fjXnx9kp7wbUJD+qgo29aQ+j2wUxELv9vLGNZEpkUQviP95FhyfyTVwwSJ/lgKTz6j26Hm1Hn984yePdIKEKP0uT9dXZB/Ghc5eJfyCyJtQD8kd5FK8eopg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99990+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032274540453.47659159079; Fri, 10 Feb 2023 04:31:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZQWWYY1788612xVp0VDaRLHU; Fri, 10 Feb 2023 04:31:14 -0800 X-Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) by mx.groups.io with SMTP id smtpd.web10.13409.1676032273803173206 for ; Fri, 10 Feb 2023 04:31:13 -0800 X-Received: by mail-pl1-f179.google.com with SMTP id k13so6361504plg.0 for ; Fri, 10 Feb 2023 04:31:13 -0800 (PST) X-Gm-Message-State: D7DmlacAhZr314IG69Pqfwwvx1787277AA= X-Google-Smtp-Source: AK7set8yUzuHyg3eq5MqPg9LUWWYi88MhepPx573gPJc7xo8EgVhvioLWwxgBXkjgP2fKbslCwfEUg== X-Received: by 2002:a17:902:d4c6:b0:198:db5c:d296 with SMTP id o6-20020a170902d4c600b00198db5cd296mr17661963plg.64.1676032273042; Fri, 10 Feb 2023 04:31:13 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:12 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Abner Chang , Andrei Warkentin , Michael D Kinney Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 09/19] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file Date: Fri, 10 Feb 2023 18:00:31 +0530 Message-Id: <20230210123041.1489506-10-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032274; bh=RU2ZuRLXnvQvpbcU3oLv3BAKexEdrOaAmG9TSr4rAVA=; h=Cc:Date:From:Reply-To:Subject:To; b=dA5RijZradYCo/8JqUQ/cKrsFdJ1U9Ykj864KHnNFKlXCJOmGnzlRQBW2aRamb+Wxvd MAVtXjmxjO2fd41Y+TfV3ulozqu17/cdRgOhg1NQF6UfNUoubVU/dONW6Z5BetjOC9Dhc rukkNNqn66QyCTIlvqFN6AzoqHzfibC3Q24= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032275044100020 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Reviewed-by: Michael D Kinney Acked-by: Ray Ni Acked-by: Ard Biesheuvel --- UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index a377366798b0..c2280aedf5ce 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -27,6 +27,7 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ + "Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLi= b.h" ] }, "CompilerPlugin": { --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99990): https://edk2.groups.io/g/devel/message/99990 Mute This Topic: https://groups.io/mt/96874990/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99991+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99991+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032277; cv=none; d=zohomail.com; s=zohoarc; b=Pspo1nWc3EI6AtSORyy3tQC05/Ra3LN3PYoWFns/nMSoha7qc4hncfESWFkicSZFaqz/sAdm6B9t1vsyYQuCpjguvG2nkzgR3ZTMfrVHHWPhDBfLc9ELHbbwkjAZh3bF/fsg3yjMZWIMvIKDIiDV59GwTr56tNPVkRG78roCdWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032277; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Ymrkw2ikE2wJ8YZ4HCMd5gkv5jxqPJ6/EOPRF+Ll22M=; b=b/I5ZZG8TiZMv5IWUd5svBiUimi+lk7NsG4q2IOzsibVdhAwSgtSejD4yCLYgNHpVm21BuSBW+7HgK8Yh1BKkuE4pI3qIRmO3K/FkuJYZK2sL0WfYpWHD8e29e2K5SqH1FU/Zcrn5bOyv31hdk2t6HE1+aiuD5MozfoMRf095hQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99991+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032277862868.6398146742787; Fri, 10 Feb 2023 04:31:17 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id p1NuYY1788612x7632AjduI4; Fri, 10 Feb 2023 04:31:16 -0800 X-Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) by mx.groups.io with SMTP id smtpd.web10.13409.1676032273803173206 for ; Fri, 10 Feb 2023 04:31:16 -0800 X-Received: by mail-pl1-f179.google.com with SMTP id k13so6361590plg.0 for ; Fri, 10 Feb 2023 04:31:16 -0800 (PST) X-Gm-Message-State: J8cDxPMwKjX1xsSPr1wo2ycAx1787277AA= X-Google-Smtp-Source: AK7set+Aee7CWniU7og7fFGExj05lCTat4JDX+EHH+UPhQSM3KN3eZkF05+9FGCGy3QpMmjlnETtyg== X-Received: by 2002:a17:902:e547:b0:195:f3e3:b923 with SMTP id n7-20020a170902e54700b00195f3e3b923mr16209486plf.8.1676032275479; Fri, 10 Feb 2023 04:31:15 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:15 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Ard Biesheuvel , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 10/19] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Date: Fri, 10 Feb 2023 18:00:32 +0530 Message-Id: <20230210123041.1489506-11-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032276; bh=k1R+AORLVN5Hc0TmeZ9ZAf0LXQ+6XFn/80xqEIIJMwY=; h=Cc:Date:From:Reply-To:Subject:To; b=kXrVaHLPiaIDZkd0MHcb1oPsgq2n9ZWOsQaXpLvif/nL+zShJUtDIEo3GUbYmzIYpJW G32/3D3kh+zBrs6jQL2i8QrAmK9uZpSrVgPuzHHy+1wDDRpSvvqNfuecSESPGmkvD5/hh FHt3cw60+x6HYi1pyeVmdcEH3frDZKb5x4Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032279055100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This module is required by other architectures like RISC-V. Hence, move this to OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Ard Biesheuvel Reviewed-by: Andrei Warkentin --- ArmVirtPkg/ArmVirtPkg.dec | 9 = --------- OvmfPkg/OvmfPkg.dec | 7 = +++++++ {ArmVirtPkg =3D> OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf | = 3 +-- {ArmVirtPkg =3D> OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c | 0 4 files changed, 8 insertions(+), 11 deletions(-) diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec index 89d21ec3a364..4645c91a8375 100644 --- a/ArmVirtPkg/ArmVirtPkg.dec +++ b/ArmVirtPkg/ArmVirtPkg.dec @@ -34,8 +34,6 @@ [Guids.common] gEarly16550UartBaseAddressGuid =3D { 0xea67ca3e, 0x1f54, 0x436b, { 0x9= 7, 0x88, 0xd4, 0xeb, 0x29, 0xc3, 0x42, 0x67 } } gArmVirtSystemMemorySizeGuid =3D { 0x504eccb9, 0x1bf0, 0x4420, { 0x8= 6, 0x5d, 0xdc, 0x66, 0x06, 0xd4, 0x13, 0xbf } } =20 - gArmVirtVariableGuid =3D { 0x50bea1e5, 0xa2c5, 0x46e9, { 0x9b, 0x3a, 0= x59, 0x59, 0x65, 0x16, 0xb0, 0x0a } } - [PcdsFeatureFlag] # # Feature Flag PCD that defines whether TPM2 support is enabled @@ -69,10 +67,3 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # Cloud Hypervisor has no other way to pass Rsdp address to the guest ex= cept use a PCD. # gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x000000= 05 - -[PcdsDynamic] - # - # Whether to force disable ACPI, regardless of the fw_cfg settings - # exposed by QEMU - # - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x00000003 diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index be30547474ae..749fbd3b6bf4 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -161,6 +161,7 @@ [Guids] gVMMBootOrderGuid =3D {0x668f4529, 0x63d0, 0x4bb5, {= 0xb6, 0x5d, 0x6f, 0xbb, 0x9d, 0x36, 0xa4, 0x4a}} gUefiOvmfPkgTdxAcpiHobGuid =3D {0x6a0c5870, 0xd4ed, 0x44f4, {= 0xa1, 0x35, 0xdd, 0x23, 0x8b, 0x6f, 0x0c, 0x8d}} gEfiNonCcFvGuid =3D {0xae047c6d, 0xbce9, 0x426c, {= 0xae, 0x03, 0xa6, 0x8e, 0x3b, 0x8a, 0x04, 0x88}} + gOvmfVariableGuid =3D {0x50bea1e5, 0xa2c5, 0x46e9, {= 0x9b, 0x3a, 0x59, 0x59, 0x65, 0x16, 0xb0, 0x0a}} =20 [Ppis] # PPI whose presence in the PPI database signals that the TPM base addre= ss @@ -467,6 +468,12 @@ [PcdsDynamic, PcdsDynamicEx] # 2 - set by GOP Driver. gUefiOvmfPkgTokenSpaceGuid.PcdVideoResolutionSource|0|UINT8|0x64 =20 + # + # Whether to force disable ACPI, regardless of the fw_cfg settings + # exposed by QEMU + # + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69 + [PcdsFeatureFlag] gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf b/Ovm= fPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf similarity index 89% rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf index e900aa992661..85873f73b2eb 100644 --- a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf +++ b/OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf @@ -19,7 +19,6 @@ [Sources] PlatformHasAcpiDtDxe.c =20 [Packages] - ArmVirtPkg/ArmVirtPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -38,7 +37,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] gEfiVariableArchProtocolGuid diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c b/OvmfP= kg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c similarity index 100% rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99991): https://edk2.groups.io/g/devel/message/99991 Mute This Topic: https://groups.io/mt/96874991/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99992+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99992+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032279; cv=none; d=zohomail.com; s=zohoarc; b=l6IySsgNoKf8E/KDZUScEVZBFFIlM5AlDYuXsy9/luCZCCM2RifS+xNjvStdITI1CwhmFQAHSnGW0DBkGVxC78ydDcvkgLB/bX8qz1QSFugHwJiUScAm/aadpVnDjla4ujltQSdlPAZL/mFOYOXiKK7nvwVY22m76nWK750aBUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032279; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xr6GkKoMpygyRprA+mZRU/vYPoogR52yFcswG6gT8ZU=; b=jzzlAOEeY+yFlHpyUdLLMzubqnkkW7ZMAbdG423MZGUDfjn0qcNCHtcsjqZhf3Y0qiOpiLPaTdIqiKAHhi8/c2q4qG4feLZIOvVaUmejI78iQ8bTJDkVCd1bhNTCsmbDedf4oMlP4XGZMiueurNDAHD9ZZvLNuCKL1wfFM5gPDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99992+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16760322797681016.4360222827605; Fri, 10 Feb 2023 04:31:19 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id nSBwYY1788612x5NVcJPf0U0; Fri, 10 Feb 2023 04:31:19 -0800 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web10.13410.1676032278509182614 for ; Fri, 10 Feb 2023 04:31:18 -0800 X-Received: by mail-pl1-f170.google.com with SMTP id w5so6275799plg.8 for ; Fri, 10 Feb 2023 04:31:18 -0800 (PST) X-Gm-Message-State: MDw8dRcdPHHilJSbHKxI6e0Vx1787277AA= X-Google-Smtp-Source: AK7set9eIfTwNEp98bRzjbtIoFrvgAD3YZOAbRzFJqF/xPPVVaO67LGOnQtYLJHGm6s+tNDPQf4A9w== X-Received: by 2002:a17:903:41cd:b0:199:4be8:be48 with SMTP id u13-20020a17090341cd00b001994be8be48mr6593764ple.19.1676032277823; Fri, 10 Feb 2023 04:31:17 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:17 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 11/19] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe Date: Fri, 10 Feb 2023 18:00:33 +0530 Message-Id: <20230210123041.1489506-12-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032279; bh=GRBmlUdxYZzcc7C2bo77ID6FEvQPcmyMK8BcZzp1kZU=; h=Cc:Date:From:Reply-To:Subject:To; b=pRmUDcnX1wCR9YF4c/i7g9GBLT/YysDxzMvfJEmo6HUHiCqhQ4geseL0HRdcR9zA08D PXO/0+2IyvbnqsE7011LHIcyYTkWjXgrLawb9r8DAacMYHJsCnwCeTN0zKFbU9YF826Jw iQmgAOn0MK4HaDhFj/bFpCBWPQdZjyjIWzw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032281077100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 PlatformHasAcpiDtDxe is required by other architectures also. Hence, it is moved to OvmfPkg. So, update the consumers of this module with the new location. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 4 ++-- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf | 2 +- ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 4 ++-- ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc index 7ca7a391d9cf..c975e139a216 100644 --- a/ArmVirtPkg/ArmVirtCloudHv.dsc +++ b/ArmVirtPkg/ArmVirtCloudHv.dsc @@ -198,7 +198,7 @@ [PcdsDynamicDefault.common] gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 =20 [PcdsDynamicHii] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGui= d|0x0|FALSE|NV,BS + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS =20 ##########################################################################= ###### # diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 0f1c6395488a..72a0cacab4a8 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -305,7 +305,7 @@ [PcdsPatchableInModule] !endif =20 [PcdsDynamicHii] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGui= d|0x0|FALSE|NV,BS + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS =20 !if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS @@ -578,7 +578,7 @@ [Components.common] # # ACPI Support # - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf [Components.AARCH64] MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index 807c85d48285..3cb9120e4e10 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -461,7 +461,7 @@ [Components.common] # # ACPI Support # - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf [Components.AARCH64] MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { diff --git a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf= b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf index 4af06b2a6746..7cad40e11f33 100644 --- a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf +++ b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf @@ -36,7 +36,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] gEfiVariableArchProtocolGuid diff --git a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf b/ArmVirt= Pkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf index 1cf25780f830..c5bf798c3b2b 100644 --- a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf +++ b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf @@ -21,7 +21,7 @@ [Sources] KvmtoolPlatformDxe.c =20 [Packages] - ArmVirtPkg/ArmVirtPkg.dec + OvmfPkg/OvmfPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -37,7 +37,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] TRUE diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuF= vMain.fdf.inc index e06ca7424476..8a063bac04ac 100644 --- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc +++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc @@ -141,7 +141,7 @@ [FV.FvMain] # # ACPI Support # - INF ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf !if $(ARCH) =3D=3D AARCH64 INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99992): https://edk2.groups.io/g/devel/message/99992 Mute This Topic: https://groups.io/mt/96874992/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99993+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99993+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032282; cv=none; d=zohomail.com; s=zohoarc; b=J/qBoXbu/VPybkg0vTFtLQiW1FZmZ8z97FDdaS0dGgY1T2C7bz01YZxlXRASbr+HLAsMiHb76x0mTcDbXOgQErI52C/8N1hTKtA1VuvqUgTC6LxPtbo7J4uxAltTMj7d5ss26wzksgNTavoaIygmjZoiGn113dyp5zvSaZ60734= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032282; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=I0gO3LBAekhI3ZxSJG9gTf81eJ+Yp0A09T3uwur/0mE=; b=T7LI7nnYqhefCD+JR8XCPevTYi0XjiYo4BLxLsr9NOKkkCQ+Cgz9uD1DOdqquZCSQma+FN0W5rSpKP+zcK3By2f8XuKQ9/w2Xeg//jrvvb4zOFB37ynK6OwjnojqlUhpnKRnBeWVz7tWqATRCU+GroEYR2MgvCccbGx2DPM1/+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99993+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032282310372.07895800908227; Fri, 10 Feb 2023 04:31:22 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id SQk4YY1788612xHOyMc98K4Z; Fri, 10 Feb 2023 04:31:21 -0800 X-Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web10.13411.1676032281238839545 for ; Fri, 10 Feb 2023 04:31:21 -0800 X-Received: by mail-pl1-f173.google.com with SMTP id m2so6305568plg.4 for ; Fri, 10 Feb 2023 04:31:21 -0800 (PST) X-Gm-Message-State: tZ40AaDThaGDDU9efMIv1CpXx1787277AA= X-Google-Smtp-Source: AK7set9OJm9qonxPx63qzxVt90Ik5SeFG89jHk5g61XtYSfCe9jrT1bfwf6ZKvE2JmR0nr/InR0syQ== X-Received: by 2002:a17:902:e807:b0:196:8d48:8760 with SMTP id u7-20020a170902e80700b001968d488760mr17546079plg.31.1676032280472; Fri, 10 Feb 2023 04:31:20 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:20 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 12/19] OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library Date: Fri, 10 Feb 2023 18:00:34 +0530 Message-Id: <20230210123041.1489506-13-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032281; bh=h08Cb5E4sJlr+d/KsvD0uBWkSo+TZOoG7tX+DIxPGg4=; h=Cc:Date:From:Reply-To:Subject:To; b=F2J7dsCDxvhNll+h84jQPWqcSeAeeVKCdbNIWFTdinyCfZPqJNyWl2ys01M4zZm+xJ8 HE1VHph1iLmVc/fmLNSvFnqPaPTDdbyoV3N1IUQc21BQPDOblQU/Qkw6386rBjXfmw9hy +C001NfTukVsvdSUbolLNtzY1ZuRDlKCHDg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032283139100009 Content-Type: text/plain; charset="utf-8" RISC-V Qemu Virt platfform needs the PlatformBootManagerLib similar to the one in ArmVirtPlatform. Add the library in OvmfPkg/RiscVVirt leveraging the one from Arm. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.in= f | 75 ++ OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h = | 45 + OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c = | 1078 ++++++++++++++++++++ OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c = | 77 ++ 4 files changed, 1275 insertions(+) diff --git a/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootM= anagerLib.inf b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBo= otManagerLib.inf new file mode 100644 index 000000000000..9d66c8110c53 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerL= ib.inf @@ -0,0 +1,75 @@ +## @file +# Implementation for PlatformBootManagerLib library class interfaces for = RISC-V. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D DxeRiscV64PlatformBootManagerLib + FILE_GUID =3D 4FC87DC9-2666-49BB-9023-B5FAA1E9E732 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformBootManagerLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PlatformBm.c + PlatformBm.h + QemuKernel.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + SecurityPkg/SecurityPkg.dec + ShellPkg/ShellPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BootLogoLib + DebugLib + DevicePathLib + MemoryAllocationLib + PcdLib + PlatformBmPrintScLib + QemuBootOrderLib + QemuLoadImageLib + ReportStatusCodeLib + TpmPlatformHierarchyLib + UefiBootManagerLib + UefiBootServicesTableLib + UefiLib + UefiRuntimeServicesTableLib + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[Guids] + gEfiEndOfDxeEventGroupGuid + gEfiGlobalVariableGuid + gRootBridgesConnectedEventGroupGuid + gUefiShellFileGuid + gEfiTtyTermGuid + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid + gEfiGraphicsOutputProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gVirtioDeviceProtocolGuid diff --git a/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h = b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h new file mode 100644 index 000000000000..70c52d9832ca --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.h @@ -0,0 +1,45 @@ +/** @file + Head file for BDS Platform specific code + + Copyright (C) 2015-2016, Red Hat, Inc. + Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BM_H_ +#define _PLATFORM_BM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Download the kernel, the initial ramdisk, and the kernel command line fr= om + QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two + image files, and load and start the kernel from it. + + The kernel will be instructed via its command line to load the initrd fr= om + the same Simple FileSystem. + + @retval EFI_NOT_FOUND Kernel image was not found. + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. + @retval EFI_PROTOCOL_ERROR Unterminated kernel command line. + + @return Error codes from any of the underlying + functions. On success, the function doesn't + return. +**/ +EFI_STATUS +EFIAPI +TryRunningQemuKernel ( + VOID + ); + +#endif // _PLATFORM_BM_H_ diff --git a/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c = b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c new file mode 100644 index 000000000000..2559889638ad --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBm.c @@ -0,0 +1,1078 @@ +/** @file + Implementation for PlatformBootManagerLib library class interfaces. + + Copyright (C) 2015-2016, Red Hat, Inc. + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformBm.h" + +#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >= > 8) } + +#define VERSION_STRING_PREFIX L"RISC-V EDK2 firmware version " + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH SerialDxe; + UART_DEVICE_PATH Uart; + VENDOR_DEFINED_DEVICE_PATH TermType; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_SERIAL_CONSOLE; +#pragma pack () + +STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole =3D { + // + // VENDOR_DEVICE_PATH SerialDxe + // + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH= ) }, + EDKII_SERIAL_PORT_LIB_VENDOR_GUID + }, + + // + // UART_DEVICE_PATH Uart + // + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) = }, + 0, // Reserved + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits + FixedPcdGet8 (PcdUartDefaultParity), // Parity + FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits + }, + + // + // VENDOR_DEFINED_DEVICE_PATH TermType + // + { + { + MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, + DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) + } + // + // Guid to be filled in dynamically + // + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + +#pragma pack (1) +typedef struct { + USB_CLASS_DEVICE_PATH Keyboard; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_USB_KEYBOARD; +#pragma pack () + +STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard =3D { + // + // USB_CLASS_DEVICE_PATH Keyboard + // + { + { + MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, + DP_NODE_LEN (USB_CLASS_DEVICE_PATH) + }, + 0xFFFF, // VendorId: any + 0xFFFF, // ProductId: any + 3, // DeviceClass: HID + 1, // DeviceSubClass: boot + 1 // DeviceProtocol: keyboard + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + +/** + Check if the handle satisfies a particular condition. + + @param[in] Handle The handle to check. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. + + @retval TRUE The condition is satisfied. + @retval FALSE Otherwise. This includes the case when the condition coul= d not + be fully evaluated due to an error. +**/ +typedef +BOOLEAN +(EFIAPI *FILTER_FUNCTION)( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Process a handle. + + @param[in] Handle The handle to process. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. +**/ +typedef +VOID +(EFIAPI *CALLBACK_FUNCTION)( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Locate all handles that carry the specified protocol, filter them with a + callback function, and pass each handle that passes the filter to another + callback. + + @param[in] ProtocolGuid The protocol to look for. + + @param[in] Filter The filter function to pass each handle to. If = this + parameter is NULL, then all handles are process= ed. + + @param[in] Process The callback function to pass each handle to th= at + clears the filter. +**/ +STATIC +VOID +FilterAndProcess ( + IN EFI_GUID *ProtocolGuid, + IN FILTER_FUNCTION Filter OPTIONAL, + IN CALLBACK_FUNCTION Process + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN NoHandles; + UINTN Idx; + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + ProtocolGuid, + NULL /* SearchKey */, + &NoHandles, + &Handles + ); + if (EFI_ERROR (Status)) { + // + // This is not an error, just an informative condition. + // + DEBUG (( + DEBUG_VERBOSE, + "%a: %g: %r\n", + __FUNCTION__, + ProtocolGuid, + Status + )); + return; + } + + ASSERT (NoHandles > 0); + for (Idx =3D 0; Idx < NoHandles; ++Idx) { + CHAR16 *DevicePathText; + STATIC CHAR16 Fallback[] =3D L""; + + // + // The ConvertDevicePathToText() function handles NULL input transpare= ntly. + // + DevicePathText =3D ConvertDevicePathToText ( + DevicePathFromHandle (Handles[Idx]), + FALSE, // DisplayOnly + FALSE // AllowShortcuts + ); + if (DevicePathText =3D=3D NULL) { + DevicePathText =3D Fallback; + } + + if ((Filter =3D=3D NULL) || Filter (Handles[Idx], DevicePathText)) { + Process (Handles[Idx], DevicePathText); + } + + if (DevicePathText !=3D Fallback) { + FreePool (DevicePathText); + } + } + + gBS->FreePool (Handles); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a PCI display dev= ice. +**/ +STATIC +BOOLEAN +EFIAPI +IsPciDisplay ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + + Status =3D gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + // + // This is not an error worth reporting. + // + return FALSE; + } + + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0 /* Offset */, + sizeof Pci / sizeof (UINT32), + &Pci + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status)= ); + return FALSE; + } + + return IS_PCI_DISPLAY (&Pci); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a Virtio RNG devi= ce at + the VIRTIO_DEVICE_PROTOCOL level. +**/ +STATIC +BOOLEAN +EFIAPI +IsVirtioRng ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + VIRTIO_DEVICE_PROTOCOL *VirtIo; + + Status =3D gBS->HandleProtocol ( + Handle, + &gVirtioDeviceProtocolGuid, + (VOID **)&VirtIo + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return (BOOLEAN)(VirtIo->SubSystemDeviceId =3D=3D + VIRTIO_SUBSYSTEM_ENTROPY_SOURCE); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a Virtio RNG devi= ce at + the EFI_PCI_IO_PROTOCOL level. +**/ +STATIC +BOOLEAN +EFIAPI +IsVirtioPciRng ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT16 VendorId; + UINT16 DeviceId; + UINT8 RevisionId; + BOOLEAN Virtio10; + UINT16 SubsystemId; + + Status =3D gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + // + // Read and check VendorId. + // + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_VENDOR_ID_OFFSET, + 1, + &VendorId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + if (VendorId !=3D VIRTIO_VENDOR_ID) { + return FALSE; + } + + // + // Read DeviceId and RevisionId. + // + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_DEVICE_ID_OFFSET, + 1, + &DeviceId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + PCI_REVISION_ID_OFFSET, + 1, + &RevisionId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + // + // From DeviceId and RevisionId, determine whether the device is a + // modern-only Virtio 1.0 device. In case of Virtio 1.0, DeviceId can + // immediately be restricted to VIRTIO_SUBSYSTEM_ENTROPY_SOURCE, and + // SubsystemId will only play a sanity-check role. Otherwise, DeviceId c= an + // only be sanity-checked, and SubsystemId will decide. + // + if ((DeviceId =3D=3D 0x1040 + VIRTIO_SUBSYSTEM_ENTROPY_SOURCE) && + (RevisionId >=3D 0x01)) + { + Virtio10 =3D TRUE; + } else if ((DeviceId >=3D 0x1000) && (DeviceId <=3D 0x103F) && (Revision= Id =3D=3D 0x00)) { + Virtio10 =3D FALSE; + } else { + return FALSE; + } + + // + // Read and check SubsystemId as dictated by Virtio10. + // + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_SUBSYSTEM_ID_OFFSET, + 1, + &SubsystemId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + if (Virtio10 && (SubsystemId >=3D 0x40)) { + return TRUE; + } + + if (!Virtio10 && (SubsystemId =3D=3D VIRTIO_SUBSYSTEM_ENTROPY_SOURCE)) { + return TRUE; + } + + return FALSE; + +PciError: + DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status)); + return FALSE; +} + +/** + This CALLBACK_FUNCTION attempts to connect a handle non-recursively, ask= ing + the matching driver to produce all first-level child handles. +**/ +STATIC +VOID +EFIAPI +Connect ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + + Status =3D gBS->ConnectController ( + Handle, // ControllerHandle + NULL, // DriverImageHandle + NULL, // RemainingDevicePath -- produce all children + FALSE // Recursive + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, + "%a: %s: %r\n", + __FUNCTION__, + ReportText, + Status + )); +} + +/** + This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the + handle, and adds it to ConOut and ErrOut. +**/ +STATIC +VOID +EFIAPI +AddOutput ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + DevicePath =3D DevicePathFromHandle (Handle); + if (DevicePath =3D=3D NULL) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: handle %p: device path not found\n", + __FUNCTION__, + ReportText, + Handle + )); + return; + } + + Status =3D EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL= ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: adding to ConOut: %r\n", + __FUNCTION__, + ReportText, + Status + )); + return; + } + + Status =3D EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL= ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: adding to ErrOut: %r\n", + __FUNCTION__, + ReportText, + Status + )); + return; + } + + DEBUG (( + DEBUG_VERBOSE, + "%a: %s: added to ConOut and ErrOut\n", + __FUNCTION__, + ReportText + )); +} + +STATIC +VOID +PlatformRegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINT32 Attributes + ) +{ + EFI_STATUS Status; + INTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status =3D gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **)&LoadedImage + ); + ASSERT_EFI_ERROR (Status); + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + DevicePath =3D DevicePathFromHandle (LoadedImage->DeviceHandle); + ASSERT (DevicePath !=3D NULL); + DevicePath =3D AppendDevicePathNode ( + DevicePath, + (EFI_DEVICE_PATH_PROTOCOL *)&FileNode + ); + ASSERT (DevicePath !=3D NULL); + + Status =3D EfiBootManagerInitializeLoadOption ( + &NewOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + NULL, + 0 + ); + ASSERT_EFI_ERROR (Status); + FreePool (DevicePath); + + BootOptions =3D EfiBootManagerGetLoadOptions ( + &BootOptionCount, + LoadOptionTypeBoot + ); + + OptionIndex =3D EfiBootManagerFindLoadOption ( + &NewOption, + BootOptions, + BootOptionCount + ); + + if (OptionIndex =3D=3D -1) { + Status =3D EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN); + ASSERT_EFI_ERROR (Status); + } + + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + +/** + Remove all MemoryMapped(...)/FvFile(...) and Fv(...)/FvFile(...) boot op= tions + whose device paths do not resolve exactly to an FvFile in the system. + + This removes any boot options that point to binaries built into the firm= ware + and have become stale due to any of the following: + - FvMain's base address or size changed (historical), + - FvMain's FvNameGuid changed, + - the FILE_GUID of the pointed-to binary changed, + - the referenced binary is no longer built into the firmware. + + EfiBootManagerFindLoadOption() used in PlatformRegisterFvBootOption() on= ly + avoids exact duplicates. +**/ +STATIC +VOID +RemoveStaleFvFileOptions ( + VOID + ) +{ + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + UINTN Index; + + BootOptions =3D EfiBootManagerGetLoadOptions ( + &BootOptionCount, + LoadOptionTypeBoot + ); + + for (Index =3D 0; Index < BootOptionCount; ++Index) { + EFI_DEVICE_PATH_PROTOCOL *Node1, *Node2, *SearchNode; + EFI_STATUS Status; + EFI_HANDLE FvHandle; + + // + // If the device path starts with neither MemoryMapped(...) nor Fv(...= ), + // then keep the boot option. + // + Node1 =3D BootOptions[Index].FilePath; + if (!((DevicePathType (Node1) =3D=3D HARDWARE_DEVICE_PATH) && + (DevicePathSubType (Node1) =3D=3D HW_MEMMAP_DP)) && + !((DevicePathType (Node1) =3D=3D MEDIA_DEVICE_PATH) && + (DevicePathSubType (Node1) =3D=3D MEDIA_PIWG_FW_VOL_DP))) + { + continue; + } + + // + // If the second device path node is not FvFile(...), then keep the bo= ot + // option. + // + Node2 =3D NextDevicePathNode (Node1); + if ((DevicePathType (Node2) !=3D MEDIA_DEVICE_PATH) || + (DevicePathSubType (Node2) !=3D MEDIA_PIWG_FW_FILE_DP)) + { + continue; + } + + // + // Locate the Firmware Volume2 protocol instance that is denoted by the + // boot option. If this lookup fails (i.e., the boot option references= a + // firmware volume that doesn't exist), then we'll proceed to delete t= he + // boot option. + // + SearchNode =3D Node1; + Status =3D gBS->LocateDevicePath ( + &gEfiFirmwareVolume2ProtocolGuid, + &SearchNode, + &FvHandle + ); + + if (!EFI_ERROR (Status)) { + // + // The firmware volume was found; now let's see if it contains the F= vFile + // identified by GUID. + // + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileNode; + UINTN BufferSize; + EFI_FV_FILETYPE FoundType; + EFI_FV_FILE_ATTRIBUTES FileAttributes; + UINT32 AuthenticationStatus; + + Status =3D gBS->HandleProtocol ( + FvHandle, + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvProtocol + ); + ASSERT_EFI_ERROR (Status); + + FvFileNode =3D (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)Node2; + // + // Buffer=3D=3DNULL means we request metadata only: BufferSize, Foun= dType, + // FileAttributes. + // + Status =3D FvProtocol->ReadFile ( + FvProtocol, + &FvFileNode->FvFileName, // NameGuid + NULL, // Buffer + &BufferSize, + &FoundType, + &FileAttributes, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + // + // The FvFile was found. Keep the boot option. + // + continue; + } + } + + // + // Delete the boot option. + // + Status =3D EfiBootManagerDeleteLoadOptionVariable ( + BootOptions[Index].OptionNumber, + LoadOptionTypeBoot + ); + DEBUG_CODE_BEGIN (); + CHAR16 *DevicePathString; + + DevicePathString =3D ConvertDevicePathToText ( + BootOptions[Index].FilePath, + FALSE, + FALSE + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_WARN : DEBUG_VERBOSE, + "%a: removing stale Boot#%04x %s: %r\n", + __FUNCTION__, + (UINT32)BootOptions[Index].OptionNumber, + DevicePathString =3D=3D NULL ? L"" : DevicePathString, + Status + )); + if (DevicePathString !=3D NULL) { + FreePool (DevicePathString); + } + + DEBUG_CODE_END (); + } + + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + +STATIC +VOID +PlatformRegisterOptionsAndKeys ( + VOID + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Enter; + EFI_INPUT_KEY F2; + EFI_INPUT_KEY Esc; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + + // + // Register ENTER as CONTINUE key + // + Enter.ScanCode =3D SCAN_NULL; + Enter.UnicodeChar =3D CHAR_CARRIAGE_RETURN; + Status =3D EfiBootManagerRegisterContinueKeyOption (0, &Enter= , NULL); + ASSERT_EFI_ERROR (Status); + + // + // Map F2 and ESC to Boot Manager Menu + // + F2.ScanCode =3D SCAN_F2; + F2.UnicodeChar =3D CHAR_NULL; + Esc.ScanCode =3D SCAN_ESC; + Esc.UnicodeChar =3D CHAR_NULL; + Status =3D EfiBootManagerGetBootManagerMenu (&BootOption); + ASSERT_EFI_ERROR (Status); + Status =3D EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)BootOption.OptionNumber, + 0, + &F2, + NULL + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED); + Status =3D EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)BootOption.OptionNumber, + 0, + &Esc, + NULL + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED); +} + +// +// BDS Platform Functions +// + +/** + Do the platform init, can be customized by OEM/IBV + Possible things that can be done in PlatformBootManagerBeforeConsole: + > Update console variable: 1. include hot-plug devices; + > 2. Clear ConIn and add SOL for AMT + > Register new Driver#### or Boot#### + > Register new Key####: e.g.: F12 + > Signal ReadyToLock event + > Authentication action: 1. connect Auth devices; + > 2. Identify auto logon user. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + UINT16 FrontPageTimeout; + RETURN_STATUS PcdStatus; + EFI_STATUS Status; + + // + // Signal EndOfDxe PI Event + // + EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid); + + // + // Disable the TPM 2 platform hierarchy + // + ConfigureTpmPlatformHierarchy (); + + // + // Dispatch deferred images after EndOfDxe event. + // + EfiBootManagerDispatchDeferredImages (); + + // + // Locate the PCI root bridges and make the PCI bus driver connect each, + // non-recursively. This will produce a number of child handles with Pci= Io on + // them. + // + FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect); + + // + // Signal the ACPI platform driver that it can download QEMU ACPI tables. + // + EfiEventGroupSignal (&gRootBridgesConnectedEventGroupGuid); + + // + // Find all display class PCI devices (using the handles from the previo= us + // step), and connect them non-recursively. This should produce a number= of + // child handles with GOPs on them. + // + FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect); + + // + // Now add the device path of all handles with GOP on them to ConOut and + // ErrOut. + // + FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput); + + // + // Add the hardcoded short-form USB keyboard device path to ConIn. + // + EfiBootManagerUpdateConsoleVariable ( + ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, + NULL + ); + + // + // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. + // + CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid); + + EfiBootManagerUpdateConsoleVariable ( + ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + EfiBootManagerUpdateConsoleVariable ( + ConOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + EfiBootManagerUpdateConsoleVariable ( + ErrOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + + // + // Set the front page timeout from the QEMU configuration. + // + FrontPageTimeout =3D GetFrontPageTimeoutFromQemu (); + PcdStatus =3D PcdSet16S (PcdPlatformBootTimeOut, FrontPageTimeout= ); + ASSERT_RETURN_ERROR (PcdStatus); + // + // Reflect the PCD in the standard Timeout variable. + // + Status =3D gRT->SetVariable ( + EFI_TIME_OUT_VARIABLE_NAME, + &gEfiGlobalVariableGuid, + (EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS), + sizeof FrontPageTimeout, + &FrontPageTimeout + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, + "%a: SetVariable(%s, %u): %r\n", + __FUNCTION__, + EFI_TIME_OUT_VARIABLE_NAME, + FrontPageTimeout, + Status + )); + + // + // Register platform-specific boot options and keyboard shortcuts. + // + PlatformRegisterOptionsAndKeys (); + + // + // At this point, VIRTIO_DEVICE_PROTOCOL instances exist only for Virtio= MMIO + // transports. Install EFI_RNG_PROTOCOL instances on Virtio MMIO RNG dev= ices. + // + FilterAndProcess (&gVirtioDeviceProtocolGuid, IsVirtioRng, Connect); + + // + // Install both VIRTIO_DEVICE_PROTOCOL and (dependent) EFI_RNG_PROTOCOL + // instances on Virtio PCI RNG devices. + // + FilterAndProcess (&gEfiPciIoProtocolGuid, IsVirtioPciRng, Connect); +} + +/** + Do the platform specific action after the console is ready + Possible things that can be done in PlatformBootManagerAfterConsole: + > Console post action: + > Dynamically switch output mode from 100x31 to 80x25 for certain scen= ario + > Signal console ready platform customized event + > Run diagnostics like memory testing + > Connect certain devices + > Dispatch additional option roms + > Special boot: e.g.: USB boot, enter UI +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + RETURN_STATUS Status; + UINTN FirmwareVerLength; + + FirmwareVerLength =3D StrLen (PcdGetPtr (PcdFirmwareVersionString)); + // + // Show the splash screen. + // + BootLogoEnableLogo (); + + if (FirmwareVerLength > 0) { + Print ( + VERSION_STRING_PREFIX L"%s\n", + PcdGetPtr (PcdFirmwareVersionString) + ); + } + + Print (L"Press ESCAPE within 10 seconds for boot options "); + // + // Process QEMU's -kernel command line option. The kernel booted this way + // will receive ACPI tables: in PlatformBootManagerBeforeConsole(), we + // connected any and all PCI root bridges, and then signaled the ACPI + // platform driver. + // + TryRunningQemuKernel (); + + // + // Connect the purported boot devices. + // + Status =3D ConnectDevicesFromQemu (); + if (RETURN_ERROR (Status)) { + // + // Connect the rest of the devices. + // + EfiBootManagerConnectAll (); + } + + // + // Enumerate all possible boot options, then filter and reorder them bas= ed on + // the QEMU configuration. + // + EfiBootManagerRefreshAllBootOption (); + + // + // Register UEFI Shell + // + PlatformRegisterFvBootOption ( + &gUefiShellFileGuid, + L"EFI Internal Shell", + LOAD_OPTION_ACTIVE + ); + + RemoveStaleFvFileOptions (); + SetBootOrderFromQemu (); + + PlatformBmPrintScRegisterHandler (); +} + +/** + This function is called each second during the boot manager waits the + timeout. + + @param TimeoutRemain The remaining timeout. +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White; + UINT16 TimeoutInitial; + + TimeoutInitial =3D PcdGet16 (PcdPlatformBootTimeOut); + + // + // If PcdPlatformBootTimeOut is set to zero, then we consider + // that no progress update should be enacted. + // + if (TimeoutInitial =3D=3D 0) { + return; + } + + Black.Raw =3D 0x00000000; + White.Raw =3D 0x00FFFFFF; + + BootLogoUpdateProgress ( + White.Pixel, + Black.Pixel, + L"Start boot option", + White.Pixel, + (TimeoutInitial - TimeoutRemain) * 100 / TimeoutInitial, + 0 + ); +} + +/** + The function is called when no boot option could be launched, + including platform recovery options and options pointing to applications + built into firmware volumes. + + If this function returns, BDS attempts to enter an infinite loop. +**/ +VOID +EFIAPI +PlatformBootManagerUnableToBoot ( + VOID + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Key; + EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu; + UINTN Index; + + // + // BootManagerMenu doesn't contain the correct information when return s= tatus + // is EFI_NOT_FOUND. + // + Status =3D EfiBootManagerGetBootManagerMenu (&BootManagerMenu); + if (EFI_ERROR (Status)) { + return; + } + + // + // Normally BdsDxe does not print anything to the system console, but th= is is + // a last resort -- the end-user will likely not see any DEBUG messages + // logged in this situation. + // + // AsciiPrint() will NULL-check gST->ConOut internally. We check gST->Co= nIn + // here to see if it makes sense to request and wait for a keypress. + // + if (gST->ConIn !=3D NULL) { + AsciiPrint ( + "%a: No bootable option or device was found.\n" + "%a: Press any key to enter the Boot Manager Menu.\n", + gEfiCallerBaseName, + gEfiCallerBaseName + ); + Status =3D gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &Index); + ASSERT_EFI_ERROR (Status); + ASSERT (Index =3D=3D 0); + + // + // Drain any queued keys. + // + while (!EFI_ERROR (gST->ConIn->ReadKeyStroke (gST->ConIn, &Key))) { + // + // just throw away Key + // + } + } + + for ( ; ;) { + EfiBootManagerBoot (&BootManagerMenu); + } +} diff --git a/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c = b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c new file mode 100644 index 000000000000..736628174f4e --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/QemuKernel.c @@ -0,0 +1,77 @@ +/** @file + Try to load an EFI-stubbed RISC-V Linux kernel from QEMU's fw_cfg. + + This implementation differs from OvmfPkg/Library/LoadLinuxLib. An EFI + stub in the subject kernel is a hard requirement here. + + Copyright (C) 2014-2016, Red Hat, Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include "PlatformBm.h" + +// +// The entry point of the feature. +// + +/** + Download the kernel, the initial ramdisk, and the kernel command line fr= om + QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two + image files, and load and start the kernel from it. + + The kernel will be instructed via its command line to load the initrd fr= om + the same Simple FileSystem. + + @retval EFI_NOT_FOUND Kernel image was not found. + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. + @retval EFI_PROTOCOL_ERROR Unterminated kernel command line. + + @return Error codes from any of the underlying + functions. On success, the function doesn't + return. +**/ +EFI_STATUS +EFIAPI +TryRunningQemuKernel ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE KernelImageHandle; + + Status =3D QemuLoadKernelImage (&KernelImageHandle); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Signal the EFI_EVENT_GROUP_READY_TO_BOOT event. + // + EfiSignalEventReadyToBoot (); + + REPORT_STATUS_CODE ( + EFI_PROGRESS_CODE, + (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT) + ); + + // + // Start the image. + // + Status =3D QemuStartKernelImage (&KernelImageHandle); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: QemuStartKernelImage(): %r\n", + __FUNCTION__, + Status + )); + } + + QemuUnloadKernelImage (KernelImageHandle); + + return Status; +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99993): https://edk2.groups.io/g/devel/message/99993 Mute This Topic: https://groups.io/mt/96874995/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99994+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99994+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032284; cv=none; d=zohomail.com; s=zohoarc; b=NBuxSamfVCw9et+Y3c+y6A6TPYSVtUbFlllIpTH70LpNoEslShH0N1U7Sdn/NBlD3tf7hjvy1Ee2rTPvmGspgU2w/5EGX6U5L2MCAgtUjNh8YFAJSFqVB9L5KUNoUKetKwx/Z/qu2ctmiDhB0a2GpEfd7uwiM6SOEscqs4lC+7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032284; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9X5XH8vDO9boX7N1E6cUFuTsIkEVXoVLnQNnb37An7M=; b=g6DjUIqaW1URNzraVSPKMb8dFJbjJClITigupoyWmDjL0KtHYJBLNmj4E+GoGCcXbJRJBTQt4TPjVWvWuerIdIxp/ixaQnvxWLteyMkb0Nc2LLI1KAv/FsLMzGS4AaZdEeGHbcTjG+vpTEXojR4dxgs/wuZsuHXVrg0ohX2pfvg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99994+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032284395119.6668829215962; Fri, 10 Feb 2023 04:31:24 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6N0eYY1788612xyn6rYtzOIS; Fri, 10 Feb 2023 04:31:24 -0800 X-Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) by mx.groups.io with SMTP id smtpd.web10.13409.1676032273803173206 for ; Fri, 10 Feb 2023 04:31:23 -0800 X-Received: by mail-pl1-f179.google.com with SMTP id k13so6361893plg.0 for ; Fri, 10 Feb 2023 04:31:23 -0800 (PST) X-Gm-Message-State: U4Nm0PqvgCLaKjnZriOLcyNQx1787277AA= X-Google-Smtp-Source: AK7set+Kb5G7EYiVClmlZErDkvew5AwhqRqE0ulg4Qp0tI3y5tGwZUsNKCkf9AgWS5f7SgRPVR3rmQ== X-Received: by 2002:a17:902:d18b:b0:199:151d:d1b0 with SMTP id m11-20020a170902d18b00b00199151dd1b0mr10920250plb.49.1676032283141; Fri, 10 Feb 2023 04:31:23 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:22 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 13/19] OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library Date: Fri, 10 Feb 2023 18:00:35 +0530 Message-Id: <20230210123041.1489506-14-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032284; bh=1stH9sZx3tyTF+KTLTOGmwf8FAwAluaZeIV8KCefGig=; h=Cc:Date:From:Reply-To:Subject:To; b=PVA3WZDLiYCNhuTWv341JAt3+qnIXPKn+R/7RsBiSQBAxqp9qqwmOBaFTXEZ7CA7Yqt rakKGSZU1wehptQTv6mf34cSrFVqnB6YiB48nn1qMQQgk0nhXxC2hbzMFvrE7+9aZ+vNw lh4wNoqOf1t40dIRP6BtH6wjY/ayyyJUA88= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032285119100013 Content-Type: text/plain; charset="utf-8" Add the PrePiHobListPointerLib required for RISC-V Qemu Virt machine since it follows PEIless design. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.in= f | 23 +++++++ OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c = | 65 ++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListP= ointerLib.inf b/OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobLi= stPointerLib.inf new file mode 100644 index 000000000000..c539682e8d0b --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerL= ib.inf @@ -0,0 +1,23 @@ +#/** @file +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PrePiHobListPointerLib + FILE_GUID =3D E3FAFC60-758C-471B-A333-FE704A4C11B4 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PrePiHobListPointerLib + +[Sources.RISCV64] + PrePiHobListPointer.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + UefiCpuPkg/UefiCpuPkg.dec diff --git a/OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListP= ointer.c b/OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPoi= nter.c new file mode 100644 index 000000000000..a58b7aae6bee --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointer.c @@ -0,0 +1,65 @@ +/** @file +* +* Copyright (c) 2021, Intel Corporation. All rights reserved.
+* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +/** + Returns the pointer to the HOB list. + + This function returns the pointer to first HOB in the list. + + @return The pointer to the HOB list. + +**/ +VOID * +EFIAPI +PrePeiGetHobList ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return NULL; + } + + return (VOID *)FirmwareContext->PrePiHobList; +} + +/** + Updates the pointer to the HOB list. + + @param HobList Hob list pointer to store + +**/ +EFI_STATUS +EFIAPI +PrePeiSetHobList ( + IN VOID *HobList + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_NOT_READY; + } + + FirmwareContext->PrePiHobList =3D HobList; + return EFI_SUCCESS; +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99994): https://edk2.groups.io/g/devel/message/99994 Mute This Topic: https://groups.io/mt/96874996/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99995+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99995+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032287; cv=none; d=zohomail.com; s=zohoarc; b=VMtFnO9bUaWy+IyiDhi5y9QJhbl/16VAd8Jq3Kttotvs98pjLzg9O0Lu0iwztvJX9ENgIDvk8RuBHHpiykiuNkInr23Z2vA82lczXZapb4ToUgp+7st3dVi54NEkyxJUGGDlM5jD5KwkIr4B3DjO6Ua+KNsjWKizoMNTS6ScnHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032287; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=VE63msbbSTxKMWiQR2GesHy51zz7ZLi276PiS/qI5GU=; b=LxHuf8TSEh+NEWQC8wo60VdUPmcY4KCY/12ZLNSb6Nk+bLs2/MK9Il5wmhleVTvBe1JNP3RGEvzFkYhXJQmimPjC5eKTXSE0Lr3448xDHosv3obtBRWsLSv32F+lgA394vxFvjAzaKFk2lN1WZ+mT1Xx1u7M8wkyfuNO0q1WNyo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99995+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032287118322.6996613005033; Fri, 10 Feb 2023 04:31:27 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id LF91YY1788612xCH4oB3g0Gv; Fri, 10 Feb 2023 04:31:26 -0800 X-Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web10.13398.1676032256853730884 for ; Fri, 10 Feb 2023 04:31:26 -0800 X-Received: by mail-pj1-f43.google.com with SMTP id gj9-20020a17090b108900b0023114156d36so9190974pjb.4 for ; Fri, 10 Feb 2023 04:31:26 -0800 (PST) X-Gm-Message-State: WiFvIob9DilggdcdaQw3mzHcx1787277AA= X-Google-Smtp-Source: AK7set8sTsxz1zLMjwbbVUTL+vbhpFi7K6YpgMaN+EB5ldwti0ZtYSLvXjC/vMrUxDUQ0Cz6cPVIaQ== X-Received: by 2002:a17:902:e885:b0:198:dd3f:2847 with SMTP id w5-20020a170902e88500b00198dd3f2847mr17914629plg.21.1676032285579; Fri, 10 Feb 2023 04:31:25 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:25 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 14/19] OvmfPkg/RiscVVirt: Add ResetSystemLib library Date: Fri, 10 Feb 2023 18:00:36 +0530 Message-Id: <20230210123041.1489506-15-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032286; bh=/7Am4V/dtbn8ozs0eOra7wWPAWsd93C/UwFLMKu1INQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ws/gb4zXaVnzLxs1OqgKmerPLt+XeYOTZ79w++ek42lzNwpMbrlWu/+gtlkPLsk5W11 CsvQmBl2mUOLTYMaakce0fWa5wKZG+JV41fuSb27kycK/esdjW+V85hCfsxY8DHOYpgdK aBmkBicbOddKG6RSgq47sYVnxJFDPCxiiSs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032289147100002 Content-Type: text/plain; charset="utf-8" RISC-V Qemu virt uses SBI calls to implement the reset. Add the base class library. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf | 38 ++++= ++ OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c | 128 ++++= ++++++++++++++++ 2 files changed, 166 insertions(+) diff --git a/OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.in= f b/OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf new file mode 100644 index 000000000000..c3fa6bd99b52 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf @@ -0,0 +1,38 @@ +## @file +# Base library instance for ResetSystem library class for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseResetSystemLib + FILE_GUID =3D AB45A200-769D-4C10-B0D6-5E1FF5EEBF31 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ResetSystemLib + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + ResetSystemLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + TimerLib + RiscVSbiLib diff --git a/OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c b/Ov= mfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 000000000000..14f7653aa8de --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,128 @@ +/** @file + Reset System Library functions for RISC-V + + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + // Shut down via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE= ); +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform. The platform m= ay + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + // + // Can map to OpenSBI vendor or platform specific reset type. + // + return; +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,= or EfiResetShutdown + the data buffer starts with a Null-terminated = string, optionally + followed by additional binary data. The string= is a description + that the caller may use to further indicate th= e reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99995): https://edk2.groups.io/g/devel/message/99995 Mute This Topic: https://groups.io/mt/96874997/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99996+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99996+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032295; cv=none; d=zohomail.com; s=zohoarc; b=Y0C/eMJ5HFKlGkCtQotwQUrx/pJ2Aep0duLlVeWIIbuzXPtQRJvQhdnSwYH0lhGnYcPgMJj8Wmy7qNLX4mD+V9R1mVJXB01BHID0+oAAiJYPNdxT288jsfWjTLGzMGxTIPyKAxnUGPj5syL1gEWMagIVWnPtdofw8y2mgY4LR3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032295; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wa0YmHla1eKg8DiHdNkCP3v/UKR2RORKW6r1RZKdQmE=; b=YHEA+zem+EA2IUlfMy7SlPofTRQTqJgHtnaOo2EiIxA6HbqtfQ9loLN0MyL6HUs7Gzvyk1NgoKsqt1PRER9MSjB4uG1PHUEgFZOnQYrBlxNOVLpY20sbuQpt8KrfHbfcmcNH848inzQjAMIctszKqb7zbwU6KBI33cdjbqfCDE8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99996+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032295577620.2873160803797; Fri, 10 Feb 2023 04:31:35 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id VjpTYY1788612xnKIvgRsS5X; Fri, 10 Feb 2023 04:31:34 -0800 X-Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) by mx.groups.io with SMTP id smtpd.web10.13414.1676032288677369579 for ; Fri, 10 Feb 2023 04:31:28 -0800 X-Received: by mail-pj1-f49.google.com with SMTP id f16-20020a17090a9b1000b0023058bbd7b2so5412645pjp.0 for ; Fri, 10 Feb 2023 04:31:28 -0800 (PST) X-Gm-Message-State: f2i16zgcGqwqTB6xhswfEZGEx1787277AA= X-Google-Smtp-Source: AK7set/Yd2iyfz7yeq3rYqnglp+epTgC7u3i3wTqlgTWkbTSYIOxjO5/coIElbP3IT8r8yoIgpvquw== X-Received: by 2002:a17:902:e807:b0:199:642:1c27 with SMTP id u7-20020a170902e80700b0019906421c27mr17364580plg.12.1676032288012; Fri, 10 Feb 2023 04:31:28 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:27 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 15/19] OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library Date: Fri, 10 Feb 2023 18:00:37 +0530 Message-Id: <20230210123041.1489506-16-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032294; bh=oQht+REJIoSPJEnkYlk04cr6N5sdhEv7gdiBDaoYU3s=; h=Cc:Date:From:Reply-To:Subject:To; b=vnJ/W7ejS5O8sY0xqLzr081A4jHlbbf/Sc888AcjNMjvzyqkr92ZVpFxUqDAwc4O6Fa Hg8cg+QY0oK8Sk2R6ecwx4uQ9iij6OXCNiZYiuUk/yD1XXhUCbKpy5lkRblhpN4cLz8NA QQqA3DG9uoYCcjIOUdaCb9FmasTawX1Sy0A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032297174100007 Content-Type: text/plain; charset="utf-8" Qemu NOR flash driver needs this library. Add this library for RISC-V leveraged from SbsaQemu. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.in= f | 30 +++++++++++++++ OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c = | 40 ++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlash= StaticLib.inf b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFl= ashStaticLib.inf new file mode 100644 index 000000000000..4e87bd437380 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticL= ib.inf @@ -0,0 +1,30 @@ +#/** @file +# +# Component description file for VirtNorFlashStaticLib module +# +# Copyright (c) 2014, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VirtNorFlashStaticLib + FILE_GUID =3D 064742F1-E531-4D7D-A154-22315889CC23 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VirtNorFlashPlatformLib + +[Sources.common] + VirtNorFlashStaticLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase diff --git a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlash= StaticLib.c b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlas= hStaticLib.c new file mode 100644 index 000000000000..fdc2ccb6294e --- /dev/null +++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticL= ib.c @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Linaro Ltd. All rights reserved + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include + +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB + +EFI_STATUS +VirtNorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =3D +{ + FixedPcdGet32 (PcdOvmfFdBaseAddress), + FixedPcdGet64 (PcdFlashNvStorageVariableBase), + FixedPcdGet32 (PcdOvmfFirmwareFdSize), + QEMU_NOR_BLOCK_SIZE +}; + +EFI_STATUS +VirtNorFlashPlatformGetDevices ( + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + *NorFlashDescriptions =3D &mNorFlashDevice; + *Count =3D 1; + return EFI_SUCCESS; +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99996): https://edk2.groups.io/g/devel/message/99996 Mute This Topic: https://groups.io/mt/96874998/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99997+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99997+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032292; cv=none; d=zohomail.com; s=zohoarc; b=m2FdN/ZyysuzCrE4VWMUfJ1xUsWTqtKvUwc+8g7IDJGYVxKCAfxrME+vjC4MCLK5TxTOuDC11bYFXGQ7/nDSk9Z3wu+8hr5UOooGgZB3BlhbRkZ6qMPIqPna+qnoLb6NFllKc6cXj7QHKHHcUHy5rFD3hW9BFEweEmHq3e7asZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032292; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tcu8WLtLZs6sZcfwhbx7kPDVcbYi6NMmBLoxHqbGqHk=; b=RaqoOaRc3cEcKkigETctIFvmdOaSONd2/O5p83n0BFcbPQlpWMzccugAfSewdbPDMW6IO8t67EWqQa3IHmNF/HLKUSv+GQiwub4GSUjLwy99fB3Oh/gdeQ8F44Mfvc+JaQ+mUgm8cAfmL1U4Rqx+LcTXf98/3UIH/znIpo43fKY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99997+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032292625651.6840743048027; Fri, 10 Feb 2023 04:31:32 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7OhpYY1788612xXvluYFZxun; Fri, 10 Feb 2023 04:31:32 -0800 X-Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) by mx.groups.io with SMTP id smtpd.web11.13161.1676032291270296880 for ; Fri, 10 Feb 2023 04:31:31 -0800 X-Received: by mail-pj1-f51.google.com with SMTP id e10-20020a17090a630a00b0022bedd66e6dso9644166pjj.1 for ; Fri, 10 Feb 2023 04:31:31 -0800 (PST) X-Gm-Message-State: qUYzglIkgc8pQ0oPtbK1fTgPx1787277AA= X-Google-Smtp-Source: AK7set+rSU9n51KaLLQ2SrZAlm8lP4dhdx2mQo3tpX9dM1gZV2atTQDj4aVpLkhUul6W7eYBR580tA== X-Received: by 2002:a17:902:ea0e:b0:199:4362:93df with SMTP id s14-20020a170902ea0e00b00199436293dfmr12411122plg.12.1676032290483; Fri, 10 Feb 2023 04:31:30 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:30 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 16/19] OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module Date: Fri, 10 Feb 2023 18:00:38 +0530 Message-Id: <20230210123041.1489506-17-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032292; bh=cVl+qG99nVwjJ9WNuibkVgqWgFI113jV0M1NAxyIhMI=; h=Cc:Date:From:Reply-To:Subject:To; b=PwF9V2gz8mbI6LWcU8X4MyjUE5FvRE2Hqx07OK7FmizzYG2DzjZOAtZ0DK5Hp7rG8rU 6tY3eXni0gKLQGVSJ8pV7y2lIxv92NI3k3S7U1BVWWCBaSiJqZPLGjpprePYVr1yntO4i JKGYRttiqjIKMzHxHzxVS1f6DNUsLPM2ot4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032293193100002 Content-Type: text/plain; charset="utf-8" Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL to add the translation for IO access. This is copied from ArmPciCpuIo2Dxe driver. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++ OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ++++++++++++++++++++ 2 files changed, 605 insertions(+) diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/OvmfPkg/Risc= VVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf new file mode 100644 index 000000000000..4f78cfa4067b --- /dev/null +++ b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf @@ -0,0 +1,48 @@ +## @file +# Produces the CPU I/O 2 Protocol by using the services of the I/O Librar= y. +# +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PciCpuIo2Dxe + FILE_GUID =3D 9BD3C765-2579-4CF0-9349-D77205565030 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciCpuIo2Initialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PciCpuIo2Dxe.c + +[Packages] + OvmfPkg/OvmfPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation + +[Protocols] + gEfiCpuIo2ProtocolGuid ## PRODUCES + +[Depex] + TRUE diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/OvmfPkg/RiscVV= irt/PciCpuIo2Dxe/PciCpuIo2Dxe.c new file mode 100644 index 000000000000..f3bf07e63141 --- /dev/null +++ b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c @@ -0,0 +1,557 @@ +/** @file + Produces the CPU I/O 2 Protocol. + +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include +#include + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Handle for the CPU I/O 2 Protocol +// +STATIC EFI_HANDLE mHandle =3D NULL; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mInStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 0, // EfiCpuIoWidthFifoUint8 + 0, // EfiCpuIoWidthFifoUint16 + 0, // EfiCpuIoWidthFifoUint32 + 0, // EfiCpuIoWidthFifoUint64 + 1, // EfiCpuIoWidthFillUint8 + 2, // EfiCpuIoWidthFillUint16 + 4, // EfiCpuIoWidthFillUint32 + 8 // EfiCpuIoWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mOutStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 1, // EfiCpuIoWidthFifoUint8 + 2, // EfiCpuIoWidthFifoUint16 + 4, // EfiCpuIoWidthFifoUint32 + 8, // EfiCpuIoWidthFifoUint64 + 0, // EfiCpuIoWidthFillUint8 + 0, // EfiCpuIoWidthFillUint16 + 0, // EfiCpuIoWidthFillUint32 + 0 // EfiCpuIoWidthFillUint64 +}; + +/** + Check parameters to a CPU I/O 2 Protocol service request. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port= operation. + @param[in] Width Signifies the width of the I/O or Memory opera= tion. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The n= umber of + bytes moved is Width size * Count, starting at= Address. + @param[in] Buffer For read operations, the destination buffer to= store the results. + For write operations, the source buffer from w= hich to write data. + + @retval EFI_SUCCESS The parameters for this request pass the = checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >=3D EfiCpuIoWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if ((Width >=3D EfiCpuIoWidthFifoUint8) && (Width <=3D EfiCpuIoWidthFifo= Uint64)) { + Count =3D 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + return EFI_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the= maximum + // allowed address. The maximum address implied by the parameters passe= d in is + // Address + Size * Count. If the following condition is met, then the = transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_POR= T_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the C= PU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all overflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count =3D=3D 0) { + if (Address > Limit) { + return EFI_UNSUPPORTED; + } + } else { + MaxCount =3D RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return EFI_UNSUPPORTED; + } + + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return EFI_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != =3D 0) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Reads memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); + } + } + + return EFI_SUCCESS; +} + +/** + Writes memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + } + } + + return EFI_SUCCESS; +} + +/** + Reads I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address +=3D PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } + } + + return EFI_SUCCESS; +} + +/** + Write I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + // + // Make sure the parameters are valid + // + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address +=3D PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + + for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride, = Uint8Buffer +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } + } + + return EFI_SUCCESS; +} + +// +// CPU I/O 2 Protocol instance +// +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D { + { + CpuMemoryServiceRead, + CpuMemoryServiceWrite + }, + { + CpuIoServiceRead, + CpuIoServiceWrite + } +}; + +/** + The user Entry Point for module CpuIo2Dxe. The user code starts with thi= s function. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +PciCpuIo2Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mHandle, + &gEfiCpuIo2ProtocolGuid, + &mCpuIo2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99997): https://edk2.groups.io/g/devel/message/99997 Mute This Topic: https://groups.io/mt/96874999/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99998+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99998+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032295; cv=none; d=zohomail.com; s=zohoarc; b=QW2yIkjyHIIHnYQU6jbtPijledgrd/+H8zaLKuW3x/C3FSxLswi3UBGSDdu1t4Gkam99FIc2NmHNBX5DRnzcUrBxPdvynxzfOILsyfscZfsBE5JEGaBvrAsYLdDJXIjl/VY2aErRoKKnSwm4IstoGd79wcHxuPtVw71WVm6JX54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032295; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KiCC3cxZ3oWxerISt9b+eYpYagT4O9Nk9KHC73PsSPI=; b=Go3Wuf2w+12fMWuHdo+FnjNpqf68pqBm/++xPrFm8axcZ6mJaISwd24rK37eZrUzmSLlMDIg24RmB4DpTf8T3W8/b5AT1JL1nu3ncwyHK7op4l4LfdXn7s/CHpOsgjtN6YNehYSE3pAmZVL4F47E+V4RAfMeZE1Iun//kOXhHLE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99998+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032295823857.6527239519417; Fri, 10 Feb 2023 04:31:35 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id VcJtYY1788612xa6aa9MCZB4; Fri, 10 Feb 2023 04:31:35 -0800 X-Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) by mx.groups.io with SMTP id smtpd.web10.13415.1676032294004612313 for ; Fri, 10 Feb 2023 04:31:34 -0800 X-Received: by mail-pj1-f47.google.com with SMTP id nn4-20020a17090b38c400b00233a6f118d0so2622738pjb.2 for ; Fri, 10 Feb 2023 04:31:33 -0800 (PST) X-Gm-Message-State: OV2j9hWTivXq9BHkbpxr2HXtx1787277AA= X-Google-Smtp-Source: AK7set+Nvldjx3C61TjNL4a1PFZuGslZF8B4OHQyXB9mHZG9UFle7n4Uiou56uTnCehOrFc29y+0/w== X-Received: by 2002:a17:903:120f:b0:196:27be:4f53 with SMTP id l15-20020a170903120f00b0019627be4f53mr16443919plh.13.1676032293205; Fri, 10 Feb 2023 04:31:33 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:32 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 17/19] OvmfPkg/RiscVVirt: Add SEC module Date: Fri, 10 Feb 2023 18:00:39 +0530 Message-Id: <20230210123041.1489506-18-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032295; bh=W0CJ29Gg/bPcn8EFTNaR+4kSIzQyuJnyTCRN1YAmzY0=; h=Cc:Date:From:Reply-To:Subject:To; b=vUaXfixraxRiOfciWheK5d4xN9QD7jW2cU3McoPmQCBKRZwbKfYA1WSwxhdq/zQeq3t NEpbAIz7lASSk3EM1RcWBajvFcZ8T5RoIvyxLnolnYy0ZlC4NxWPIb4PnMIYjwUkTWDdO cnMo8/CllxA1Ts5nBxCTQ2PBjUx1s2EybAM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032297207100009 Content-Type: text/plain; charset="utf-8" Add the SEC module for RISC-V Qemu virt machine support. It uses the PEI less design. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/Sec/SecMain.inf | 66 +++++ OvmfPkg/RiscVVirt/Sec/SecMain.h | 102 ++++++++ OvmfPkg/RiscVVirt/Sec/Cpu.c | 33 +++ OvmfPkg/RiscVVirt/Sec/Memory.c | 263 ++++++++++++++++++++ OvmfPkg/RiscVVirt/Sec/Platform.c | 84 +++++++ OvmfPkg/RiscVVirt/Sec/SecMain.c | 104 ++++++++ OvmfPkg/RiscVVirt/Sec/SecEntry.S | 21 ++ 7 files changed, 673 insertions(+) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecM= ain.inf new file mode 100644 index 000000000000..aed35d3af596 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -0,0 +1,66 @@ +## @file +# SEC Driver for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D SecMainRiscV64 + FILE_GUID =3D 16740C0A-AA84-4F62-A06D-AE328057AE07 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + SecEntry.S + SecMain.c + SecMain.h + Cpu.c + Memory.c + Platform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + IoLib + PeCoffLib + LzmaDecompressLib + RiscVSbiLib + PrePiLib + FdtLib + MemoryAllocationLib + HobLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid ## PRODUCES + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress + +[Guids] + gFdtHobGuid diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMai= n.h new file mode 100644 index 000000000000..83a8058efe40 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -0,0 +1,102 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +/** + Perform Platform PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ); + +/** + Perform Memory PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +MemoryPeimInitialization ( + VOID + ); + +/** + Perform CPU PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +CpuPeimInitialization ( + VOID + ); + +#endif diff --git a/OvmfPkg/RiscVVirt/Sec/Cpu.c b/OvmfPkg/RiscVVirt/Sec/Cpu.c new file mode 100644 index 000000000000..2c16df697e37 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/Cpu.c @@ -0,0 +1,33 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include + +/** + Cpu Peim initialization. + +**/ +EFI_STATUS +CpuPeimInitialization ( + VOID + ) +{ + // + // for MMU type >=3D sv39 + // + BuildCpuHob (56, 32); + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c new file mode 100644 index 000000000000..70935b07b56b --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/Memory.c @@ -0,0 +1,263 @@ +/** @file + Memory Detection for Virtual Machines. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +/** + Build reserved memory range resource HOB. + + @param MemoryBase Reserved memory range base address. + @param MemorySize Reserved memory range size. + +**/ +STATIC +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +STATIC +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +STATIC +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Configure MMU +**/ +STATIC +VOID +InitMmu ( + ) +{ + // + // Set supervisor translation mode to Bare mode + // + RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 6= 0); + DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.= \n", __FUNCTION__)); +} + +/** + Publish system RAM and reserve memory regions. + +**/ +STATIC +VOID +InitializeRamRegions ( + EFI_PHYSICAL_ADDRESS SystemMemoryBase, + UINT64 SystemMemorySize, + EFI_PHYSICAL_ADDRESS MmodeResvBase, + UINT64 MmodeResvSize + ) +{ + /* + * M-mode FW can be loaded anywhere in memory but should not overlap + * with the EDK2. This can happen if some other boot code loads the + * M-mode firmware. + * + * The M-mode firmware memory should be marked as reserved memory + * so that OS doesn't use it. + */ + DEBUG (( + DEBUG_INFO, + "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, + MmodeResvBase, + MmodeResvBase + MmodeResvSize + )); + AddReservedMemoryBaseSizeHob (MmodeResvBase, MmodeResvSize); + + if (MmodeResvBase > SystemMemoryBase) { + AddMemoryRangeHob (SystemMemoryBase, MmodeResvBase); + } + + AddMemoryRangeHob ( + MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize + ); +} + +/** + Initialize memory hob based on the DTB information. + + @return EFI_SUCCESS The memory hob added successfully. + +**/ +EFI_STATUS +MemoryPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + UINT64 CurBase, CurSize; + INT32 Node, Prev; + INT32 Len; + VOID *FdtPointer; + EFI_PHYSICAL_ADDRESS MmodeResvBase; + UINT64 MmodeResvSize; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + /* try to locate the reserved memory opensbi node */ + Node =3D fdt_path_offset (FdtPointer, "/reserved-memory/mmode_resv0"); + if (Node >=3D 0) { + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + MmodeResvBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + MmodeResvSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + } + } + + // Look for the lowest memory node + for (Prev =3D 0; ; Prev =3D Node) { + Node =3D fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + + // Check for memory node + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG (( + DEBUG_INFO, + "%a: System RAM @ 0x%lx - 0x%lx\n", + __FUNCTION__, + CurBase, + CurBase + CurSize - 1 + )); + + if ((MmodeResvBase >=3D CurBase) && ((MmodeResvBase + MmodeResvSiz= e) <=3D (CurBase + CurSize))) { + InitializeRamRegions ( + CurBase, + CurSize, + MmodeResvBase, + MmodeResvSize + ); + } else { + AddMemoryBaseSizeHob (CurBase, CurSize); + } + } else { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to parse FDT memory node\n", + __FUNCTION__ + )); + } + } + } + + InitMmu (); + + BuildMemoryTypeInformationHob (); + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platf= orm.c new file mode 100644 index 000000000000..e8fd126cf800 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/Platform.c @@ -0,0 +1,84 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUN= CTION__, FdtPointer)); + Base =3D FdtPointer; + if (fdt_check_header (Base) !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + if (NewBase =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n", __FUNC= TION__)); + return EFI_UNSUPPORTED; + } + + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + if (FdtHobData =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + *FdtHobData =3D (UINTN)NewBase; + + BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSiz= e)); + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMai= n.c new file mode 100644 index 000000000000..054e49ef0c1e --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -0,0 +1,104 @@ +/** @file + RISC-V SEC phase module for Qemu Virt. + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +STATIC +EFI_STATUS +EFIAPI +SecInitializePlatform ( + VOID + ) +{ + EFI_STATUS Status; + + MemoryPeimInitialization (); + + CpuPeimInitialization (); + + // Set the Boot Mode + SetBootMode (BOOT_WITH_FULL_CONFIGURATION); + + Status =3D PlatformPeimInitialization (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_STATUS Status; + UINT64 UefiMemoryBase; + UINT64 StackBase; + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __FUNCTION__, + BootHartId, + DeviceTreeAddress + )); + + FirmwareContext.BootHartId =3D BootHartId; + FirmwareContext.FlattenedDeviceTree =3D (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + StackBase =3D (UINT64)FixedPcdGet32 (PcdOvmfSecPeiTempRamBase); + UefiMemoryBase =3D StackBase + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)= - SIZE_32MB; + + // Declare the PI/UEFI memory region + HobList =3D HobConstructor ( + (VOID *)UefiMemoryBase, + SIZE_32MB, + (VOID *)UefiMemoryBase, + (VOID *)StackBase // The top of the UEFI Memory is reserved = for the stacks + ); + PrePeiSetHobList (HobList); + + SecInitializePlatform (); + + // + // Process all libraries constructor function linked to SecMain. + // + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compre= ssed FV. + Status =3D DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status =3D LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/OvmfPkg/RiscVVirt/Sec/SecEntry.S b/OvmfPkg/RiscVVirt/Sec/SecEn= try.S new file mode 100644 index 000000000000..e919a3cb0e80 --- /dev/null +++ b/OvmfPkg/RiscVVirt/Sec/SecEntry.S @@ -0,0 +1,21 @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +.text +.align 3 + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + li a5, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99998): https://edk2.groups.io/g/devel/message/99998 Mute This Topic: https://groups.io/mt/96875001/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99999+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99999+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032298; cv=none; d=zohomail.com; s=zohoarc; b=ItGOVGdlJl7f3NpUe03aY5AyxARU+TmMdhaIXVxFAUC87/qydC48mENxtLOXnU7Qv/QoAGHE4ehUu5egypcqaQt5F6hmE0+t3WZGG9Cv+9047zVwQta1hiJ76hFNK6w4eCdpfO9NZShzkodqKZ0GWPs8nQbn8vdtL0RSGVYKcLg= ARC-Message-Signature: i=1; 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Fri, 10 Feb 2023 04:31:37 -0800 X-Received: by mail-pl1-f177.google.com with SMTP id r8so6326996pls.2 for ; Fri, 10 Feb 2023 04:31:36 -0800 (PST) X-Gm-Message-State: DR2rXebAg88ed4WLRLdMXtbqx1787277AA= X-Google-Smtp-Source: AK7set+x3N0stiOwf0y623Lll/0shFwH+ouTNhy9luBmUac3L3M1wrVZm/s02ant3dJcMyR+eAvDxA== X-Received: by 2002:a17:902:ea0d:b0:199:4362:93ea with SMTP id s13-20020a170902ea0d00b00199436293eamr12350642plg.1.1676032295868; Fri, 10 Feb 2023 04:31:35 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:35 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang , Andrei Warkentin Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 18/19] OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform Date: Fri, 10 Feb 2023 18:00:40 +0530 Message-Id: <20230210123041.1489506-19-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032297; bh=AMzx0an2mk0BJAFzxfMF3nISMtHPnjmfjOG8YzAdG3I=; h=Cc:Date:From:Reply-To:Subject:To; b=NoUlOd4MsiaXQLqBJrCoRUdmjgetvCHfyTerBlQINgbRYKGedqy/33SPCXwSoO81kDU 7TruKTTdFy85/XDkT6WSkDDU48vWPY8/Oq3mbdlvduKL62UpI2s5PzbtB1xcs4UiA+HRI xSXrFzqMioI0UlglyYfOef2wEXxNO4PrJl4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032299269100013 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW - Leveraged from ArmVirtQemu Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin Acked-by: Ard Biesheuvel --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 336 +++++++++++++ OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 504 ++++++++++++++++++++ OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 306 ++++++++++++ OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 41 ++ OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 +++ 5 files changed, 1266 insertions(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc new file mode 100644 index 000000000000..731f54f73f81 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -0,0 +1,336 @@ +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved. +# Copyright (c) 2011 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. +# Copyright (c) Microsoft Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEFINE DEBUG_PRINT_ERROR_LEVEL =3D 0x80000047 + +[LibraryClasses.common] +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + + # + # Ramdisk Requirements + # + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # Allow dynamic PCDs + # + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # Networking Requirements +!include NetworkPkg/NetworkLibs.dsc.inc +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif + + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + # RISC-V Architectural Libraries + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/= PlatformBootManagerLib.inf + ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemL= ib.inf + + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # PCI Libraries + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf + DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + + # USB Libraries + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # + # CryptoPkg libraries needed by multiple firmware features + # + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf +!else + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf +!endif + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBo= otVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariablePro= visionLib/SecureBootVariableProvisionLib.inf + PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPo= licy/PlatformPKProtectionLibVarPolicy.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/= PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + +[LibraryClasses.common.DXE_CORE] + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + +[LibraryClasses.common.DXE_DRIVER] + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + +[PcdsFeatureFlag] + # + # Activate AcpiSdtProtocol + # + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(DEBUG_ON_SERIAL_PORT) !=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEV= EL) +!endif + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|6000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >=3D 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM an= d OS + # reserved ones, with the exception of LoaderData regions, of which OS l= oaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC0000000= 00007FD5 + +[Components.common] + # + # Ramdisk support + # + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.in= f { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf +!if $(ACPIVIEW_ENABLE) =3D=3D TRUE + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf +!endif + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf +!endif + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVV= irtQemu.dsc new file mode 100644 index 000000000000..054d511138c3 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -0,0 +1,504 @@ +## @file +# RISC-V EFI on RiscVVirtQem platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D RiscVVirtQemu + PLATFORM_GUID =3D 39DADB39-1B21-4867-838E-830B6149B9E0 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE TTY_TERMINAL =3D FALSE + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE TPM2_ENABLE =3D FALSE + DEFINE TPM2_CONFIG_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!if $(NETWORK_SNP_ENABLE) =3D=3D TRUE + !error "NETWORK_SNP_ENABLE is IA32/X64/EBC only" +!endif + + +!include MdePkg/MdeLibs.dsc.inc + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC: *_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include NetworkPkg/NetworkDefines.dsc.inc + +!include OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses.common] + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf + QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf + QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFw= CfgSimpleParserLib.inf + QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf + + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLi= b/VirtNorFlashStaticLib.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/= PlatformBootManagerLib.inf + PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciHostBridgeLib|OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf + PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostB= ridgeUtilityLib.inf + PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT= cg2PhysicalPresenceLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= b/PeiDxeTpmPlatformHierarchyLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER] + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + +#!include NetworkPkg/NetworkBuildOptions.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag.common] + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + # + # The cumulative and individual VOLATILE variable size limits should be = set + # high enough for accommodating several and/or large CA certificates. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x80000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVolatileVariableSize|0x40000 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"2.7" + + # Serial Port + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|9600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + + # + # Network Pcds + # +!include NetworkPkg/NetworkPcds.dsc.inc + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + + # + # Enable the non-executable DXE stack. (This gets set up by DxeIpl) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + gEfiShellPkgTokenSpaceGuid.PcdShellFileOperationSize|0x20000 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x02 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + +[PcdsDynamicDefault.common] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI + # enumeration to complete before installing ACPI tables. + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE + + # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this + # PCD and PcdPciDisableBusEnumeration above have not been assigned yet + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF + + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 + + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 + + # + # SMBIOS entry point version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + + # + # IPv4 and IPv6 PXE Boot support. + # + gEfiNetworkPkgTokenSpaceGuid.PcdIPv4PXESupport|0x01 + gEfiNetworkPkgTokenSpaceGuid.PcdIPv6PXESupport|0x01 + + # + # TPM2 support + # +!if $(TPM2_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0 +!else +[PcdsPatchableInModule] + # make this PCD patchable instead of dynamic when TPM support is not ena= bled + # this permits setting the PCD in unreachable code without pulling in dy= namic PCD support + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 +!endif + +[PcdsDynamicHii] + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS + +!if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2C= onfigFormSetGuid|0x8|3|NV,BS +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] +!if $(TPM2_ENABLE) =3D=3D TRUE + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf +!else + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +!endif + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + OvmfPkg/RiscVVirt/Sec/SecMain.inf { + + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectio= nLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaC= ustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointer= Lib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/Pre= PiMemoryAllocationLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + # + # Architectural Protocols + # + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!if $(TPM2_ENABLE) =3D=3D TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf +!endif + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf + OvmfPkg/EnrollDefaultKeys/EnrollDefaultKeys.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # Status Code Routing + # + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + # + # Platform Driver + # + OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf + EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + OvmfPkg/VirtioScsiDxe/VirtioScsi.inf + OvmfPkg/VirtioNetDxe/VirtioNet.inf + OvmfPkg/VirtioRngDxe/VirtioRng.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + OvmfPkg/VirtioFsDxe/VirtioFsDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf { + + NULL|OvmfPkg/Library/BlobVerifierLibNull/BlobVerifierLibNull.inf + } + + # + # Networking stack + # +!include NetworkPkg/NetworkComponents.dsc.inc + + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf { + + NULL|OvmfPkg/Library/PxeBcPcdProducerLib/PxeBcPcdProducerLib.inf + } + +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf { + + NULL|OvmfPkg/Library/TlsAuthConfigLib/TlsAuthConfigLib.inf + } +!endif + + # + # SCSI Bus and Disk Driver + # + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # NVME Driver + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf { + + NULL|OvmfPkg/Library/SmbiosVersionLib/DetectSmbiosVersionLib.inf + } + OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # + # PCI support + # + OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf + OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf + OvmfPkg/Virtio10Dxe/Virtio10.inf + + # + # Video support + # + OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf + OvmfPkg/VirtioGpuDxe/VirtioGpu.inf + OvmfPkg/PlatformDxe/Platform.inf + + # + # USB Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # TPM2 support + # +!if $(TPM2_ENABLE) =3D=3D TRUE + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { + + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt= oRouterDxe.inf + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf + NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384= .inf + NULL|SecurityPkg/Library/HashInstanceLibSha512/HashInstanceLibSha512= .inf + NULL|SecurityPkg/Library/HashInstanceLibSm3/HashInstanceLibSm3.inf + } +!if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf +!endif +!endif + + # + # ACPI Support + # + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVV= irtQemu.fdf new file mode 100644 index 000000000000..6072c37af03d --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -0,0 +1,306 @@ +# @file +# Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Platform definitions +# + +!include RiscVVirt.fdf.inc + +##########################################################################= ###### +[FD.RISCV_VIRT] +BaseAddress =3D $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdB= aseAddress +Size =3D $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdS= ize +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +0x00000000|$(CODE_SIZE) +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfDxeMemFvSize +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf +INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf +INF OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf + +# +# PI DXE Drivers producing Architectural Protocols (EFI Services) +# +INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf +INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + +# +# Multiple Console IO support +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + +# RISC-V Core Drivers +INF UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf +INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# +# FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs +# +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf +INF OvmfPkg/VirtioFsDxe/VirtioFsDxe.inf + +# +# Status Code Routing +# +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf + +# +# Platform Driver +# +INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf +INF OvmfPkg/VirtioNetDxe/VirtioNet.inf +INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf +INF OvmfPkg/VirtioRngDxe/VirtioRng.inf + +INF ShellPkg/Application/Shell/Shell.inf +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf +INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand= .inf + +# +# Bds +# +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.= inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf +INF OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf + +# +# Networking stack +# +!include NetworkPkg/Network.fdf.inc + +# +# SCSI Bus and Disk Driver +# +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + +# +# NVME Driver +# +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + +# +# SMBIOS Support +# +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf +INF OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + +# +# ACPI Support +# +INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphics= ResourceTableDxe.inf +INF OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf + +# +# PCI support +# +INF OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf +INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf +INF OvmfPkg/Virtio10Dxe/Virtio10.inf + +# +# Video support +# +INF OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf +INF OvmfPkg/VirtioGpuDxe/VirtioGpu.inf +INF OvmfPkg/PlatformDxe/Platform.inf + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +# +# TianoCore logo (splash screen) +# +INF MdeModulePkg/Logo/LogoDxe.inf + +# +# Ramdisk support +# +INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + +#INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDx= e.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +INF OvmfPkg/RiscVVirt/Sec/SecMain.inf + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.fdf.inc new file mode 100644 index 000000000000..b0a1c3293f33 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -0,0 +1,41 @@ +## @file +# Definitions of Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE PFLASH1_BASE =3D 0x22000000 + +DEFINE FW_BASE_ADDRESS =3D $(PFLASH1_BASE) +DEFINE FW_SIZE =3D 0x00800000 +DEFINE FW_BLOCKS =3D 0x800 + +DEFINE CODE_BASE_ADDRESS =3D $(FW_BASE_ADDRESS) +DEFINE CODE_SIZE =3D 0x00740000 +DEFINE CODE_BLOCKS =3D 0x740 + +DEFINE VARS_SIZE =3D 0x000C0000 +DEFINE VARS_BLOCK_SIZE =3D 0x40000 +DEFINE VARS_BLOCKS =3D 0x3 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET =3D $(CODE_SIZE) +DEFINE VARS_LIVE_SIZE =3D 0x00040000 +DEFINE VARS_FTW_WORKING_OFFSET =3D $(VARS_OFFSET) + $(VARS_LIVE_SIZE) +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00040000 +DEFINE VARS_FTW_SPARE_OFFSET =3D $(VARS_FTW_WORKING_OFFSET) + $(VA= RS_FTW_WORKING_SIZE) +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00040000 + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency =3D 10000000 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase =3D 0x83FF0000 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize =3D 0x00010000 diff --git a/OvmfPkg/RiscVVirt/VarStore.fdf.inc b/OvmfPkg/RiscVVirt/VarStor= e.fdf.inc new file mode 100644 index 000000000000..30b170d77997 --- /dev/null +++ b/OvmfPkg/RiscVVirt/VarStore.fdf.inc @@ -0,0 +1,79 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_LIVE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3FFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99999): https://edk2.groups.io/g/devel/message/99999 Mute This Topic: https://groups.io/mt/96875002/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 13:20:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+100000+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100000+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1676032299; cv=none; d=zohomail.com; s=zohoarc; b=Cg7Zd56XU8DEn3CiPDIsryPcoszPtpCHDj4S1xKFy1LpIjRxuhPqocXJXPwkDtwcg9onmvSRnTWuJjEiDne3WccqcZ96ONFCsUXLCFVmXHuo4OvMy6NbeWktXmLJzuvgBuKzSUl5rn8eUAtrhpU3Yt8MUly2XzGhwOmRWe5zJ7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676032299; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=dB7AdKe36wZolsZiGJaW5JA/H0JQNd0eeag4wbY65kQ=; b=QVpLH+Z8rZabOdgH4OyslpFSb1LZI7bGzl1bBV7WLSjNBilir/nrS4tkq/pN8joZmdsCJiwxASauz1ZBu0/lz6wqmTmez3r6RP58tOPPm2R46Ti38cKnaej+vFz6kdQzuOs1F33ldiRops02huwUz/2jMHSOzTcF1es6sJu3WxA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+100000+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1676032299689472.31829452034503; Fri, 10 Feb 2023 04:31:39 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id nSOuYY1788612xTvco2BpSwW; Fri, 10 Feb 2023 04:31:39 -0800 X-Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web10.13398.1676032256853730884 for ; Fri, 10 Feb 2023 04:31:38 -0800 X-Received: by mail-pj1-f43.google.com with SMTP id gj9-20020a17090b108900b0023114156d36so9191673pjb.4 for ; Fri, 10 Feb 2023 04:31:38 -0800 (PST) X-Gm-Message-State: Ty8d5PL0qB6XwsxP1oKcpzwLx1787277AA= X-Google-Smtp-Source: AK7set9acE5Qt6veUJM+xc9YJbNyH5p2yR534Gkle72CsVIdIf/PZwikfzlas0ymg82QS9lr9YwzuQ== X-Received: by 2002:a17:903:4091:b0:19a:6943:369e with SMTP id z17-20020a170903409100b0019a6943369emr3387575plc.30.1676032298291; Fri, 10 Feb 2023 04:31:38 -0800 (PST) X-Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id b17-20020a170902ed1100b0019a73faf773sm1172961pld.71.2023.02.10.04.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 04:31:37 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Andrew Fish , Leif Lindholm , Michael D Kinney , Andrei Warkentin , Jiewen Yao Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 19/19] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt Date: Fri, 10 Feb 2023 18:00:41 +0530 Message-Id: <20230210123041.1489506-20-sunilvl@ventanamicro.com> In-Reply-To: <20230210123041.1489506-1-sunilvl@ventanamicro.com> References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676032299; bh=obTs2RvnYgY5bKSaigE1ah77b+NEwCVlVLdcwF9mg2c=; h=Cc:Date:From:Reply-To:Subject:To; b=AqjHsiM904FvvLIQtQ1O1B1FCoCnmmKzAa2b/RWVAIAGXE/sS3WzD1PXuOkdbtM83i0 XrvoYcgJ7H9uFP327JdY0Lv4G3NfWh81ix+2YpPe1l8/+mH+9urBuKYl11OrqfAUCAmLz HA1cl1UePNJOgF2S6LTefBLJujvNclBk9Nw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676032301186100017 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RiscVVirt is created to support EDK2 for RISC-V qemu virt machine platform. Add maintainer entries. Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin Reviewed-by: Jiewen Yao Reviewed-by: Michael D Kinney Acked-by: Ard Biesheuvel --- Maintainers.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 68f603b48398..af723cfaadc8 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -539,6 +539,11 @@ F: OvmfPkg/XenResetVector/ R: Anthony Perard [tperard] R: Julien Grall [jgrall] =20 +OvmfPkg: RISC-V Qemu Virt Platform +F: OvmfPkg/RiscVVirt +R: Sunil V L [vlsunil] +R: Andrei Warkentin [andreiw] + PcAtChipsetPkg F: PcAtChipsetPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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