From nobody Fri May 17 04:49:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99919+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99919+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675963110; cv=none; d=zohomail.com; s=zohoarc; b=V1KBc4y3TOeObloLMdOIOgbKh79qiswZce9KKDyf3CSa7wpzcOObOBMcJAYqJ25dZ/93IiQxiD5Rp762M2cEcIelUioCLD9jIE8hQXfTXh30yncOGp62IZKB264Eirj4mHmohQg9SvbuPDYobzuG8AYxOfM0ShvsZI+zeU9Q+Ho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675963110; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=moBMhR2/sNMtpjqb6aMtUKMaRA8Z+zeHm5coSoeQ8vA=; b=iL0De9B8zdtF46sELBQYhQ/e2+eD1Tft6RghLfsNzVGyPislGscD8Dw4+68Q8ZNGJkP/LbpKnOXYZ3Y8Z4yCox+uoQrRWFVKXWZsHNpWIuXidOGCNGpo3uZarsGV3rJni49QGziBKm8YCcJkicU2jeVsc7OE5o3ReIrTPlmKFew= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99919+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1675963110990608.2508652807121; Thu, 9 Feb 2023 09:18:30 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id r7UXYY1788612xhnQisQggCk; Thu, 09 Feb 2023 09:18:29 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.22385.1675963108676885965 for ; Thu, 09 Feb 2023 09:18:28 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10616"; a="327863223" X-IronPort-AV: E=Sophos;i="5.97,284,1669104000"; d="scan'208";a="327863223" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2023 09:15:49 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10616"; a="841724231" X-IronPort-AV: E=Sophos;i="5.97,284,1669104000"; d="scan'208";a="841724231" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.212.151.147]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2023 09:15:49 -0800 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Ashraf Ali S , Isaac Oram , Rangasai V Chaganty , Ray Ni , Michael Kubacki Subject: [edk2-devel] [edk2-platforms: PATCH v2] IntelSiliconPkg/SpiFvbServiceSmm: Support Additional NVS region. Date: Thu, 9 Feb 2023 09:15:39 -0800 Message-Id: <20230209171539.1461-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: gsDfC1KQTydJ70mLcjTkrNxDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675963109; bh=KUJJFEhoGMDd6iQ62Tv3AQ+J913dBvaOzGsVIJpz5Rk=; h=Cc:Date:From:Reply-To:Subject:To; b=vhXlzawdPi+Nl8WFbX9bCKXOSXeS0phIJGc+MB3JSDxUTMXaNIzGruLX/smpr8QDxVQ qYHPZdjJNpkvQsCSmhCRvf/+AbIhgFsykLPJ2CDr12yWSgFybNAlSnEDeKoNwT5+zXlE/ b3yYeU9iLWbI//rtyOLgLi0v3loNJKVTNfU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675963111426100002 Content-Type: text/plain; charset="utf-8" Platform may implement an additional NVS region following Regular variable region and in this case SpiFvbService should include both region size when calculating the total NVS region size. One usage model is EventLog NVS region and there could be others. Example NVS flash map for such usage model: -------------- |UEI Variable| -------------- |EventLog | <=3D this is Additional variable region -------------- |FTW Working | -------------- |FTW Spare | -------------- Cc: Ashraf Ali S Cc: Isaac Oram Cc: Rangasai V Chaganty Cc: Ray Ni Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCom= mon.c | 17 +++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm= .inf | 7 ++++--- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = | 8 ++++++++ 3 files changed, 29 insertions(+), 3 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiF= vbServiceCommon.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbServi= ce/SpiFvbServiceCommon.c index 942abf95a6..7be8d9319c 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceCommon.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceCommon.c @@ -568,6 +568,23 @@ GetVariableFvInfo ( return; } =20 + // + // GetVariableFlashNvStorageInfo () only reports regular variable region= information, + // if platform implemented an additional NVS region following the regula= r variable region, + // the both region size should be included as overall NVS region size. + // Example NVS flash map for such usage model: + // -------------- + // |UEI Variable| + // -------------- + // |EventLog | <=3D this is Additional variable region + // -------------- + // |FTW Working | + // -------------- + // |FTW Spare | + // -------------- + // + NvStoreLength +=3D PcdGet32 (PcdFlashNvStorageAdditionalSize); + Status =3D GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64); if (!EFI_ERROR (Status)) { // Stay within the current UINT32 size assumptions in the variable sta= ck. diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiF= vbServiceSmm.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbServic= e/SpiFvbServiceSmm.inf index 73049eceb2..f4009d8d8c 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceSmm.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServi= ceSmm.inf @@ -43,9 +43,10 @@ IntelSiliconPkg/IntelSiliconPkg.dec =20 [Pcd] - gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUM= ES - gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUM= ES - gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ## SOMETI= MES_CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ## SOM= ETIMES_CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize ## CON= SUMES =20 [Sources] FvbInfo.c diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 63dae756ad..b10529b69d 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -194,3 +194,11 @@ # Other value: reserved for future use.
# @Prompt Flash Variable Store type. gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType|0x00|UINT8|0x00= 00000E + + ## Declares Additional NVS Variable Region Size.

+ # Platform may implement a Regular variable region and an additional va= riable region, which will require this PCD + # to tell SpiFvbService to include both regions.
+ # 0: No additional variable region.
+ # non-zero: The size of an additional variable region following the Reg= ular variable region.
+ # @Prompt Additional NVS Variable Region Size. + gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize|0x0000000= 0|UINT32|0x0000000F --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99919): https://edk2.groups.io/g/devel/message/99919 Mute This Topic: https://groups.io/mt/96857918/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-