From nobody Sat Feb 7 04:47:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99371+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99371+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1675204567; cv=none; d=zohomail.com; s=zohoarc; b=C0BfizkcO3HWtA9Ct28WDyJ6MxPJkAZqqWirzAi2RJAZ1DfN3+vkfVZy1cRFVqoFV+z8/2MweuJHLATuZzRn9yBoCmmpZMLwIfj/YZPFn8nVJ0UlJKKMRlSqjTVcisx7YfVpfpKZo9a3Kjd/bWTXMrAa9titg0lVjp6oZgGUj2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675204567; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=fyyWnHHK3dlvHF3Hs4bce90GxJo1RtdMObzpUZKY7vs=; b=ButjpRVn9GW90qZJtJRf1HN2NXGM0o2DO/6ruAUqxLkcR05yzd66jfV9iZf+WKP2VDgx4XjUkBtx/uui4Z36OsTnRyiiwFHFuwA9CLEVJrQIIwDWIy8OgR3xN7QunD+q20r5/l8vYlX138RsR1PtbxMcmKaWnNumx5hU6Si6MMA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99371+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167520456746951.716587729860066; Tue, 31 Jan 2023 14:36:07 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id C2YGYY1788612xRmdcf2qiX2; Tue, 31 Jan 2023 14:36:07 -0800 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.8740.1675204566528414674 for ; Tue, 31 Jan 2023 14:36:06 -0800 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 156026173D; Tue, 31 Jan 2023 22:36:06 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE699C433A0; Tue, 31 Jan 2023 22:36:03 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [PATCH 3/4] ArmPkg/CpuDxe: Unify PageAttributeToGcdAttribute helper Date: Tue, 31 Jan 2023 23:35:49 +0100 Message-Id: <20230131223550.1775834-4-ardb@kernel.org> In-Reply-To: <20230131223550.1775834-1-ardb@kernel.org> References: <20230131223550.1775834-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: hAFiZtvYfF9FKRIeTWmOJYUwx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675204567; bh=DX8os11QQ1ffswBDQM+rqFsAvk3QCEp5OoJJ8/PKSn0=; h=Cc:Date:From:Reply-To:Subject:To; b=OdLucm9D6k2bb/F/Ovn6I6Lswx9K3gcvjZHtxjL+AsluRClAeyAIwjWR3is06lUAMrZ cx2oNxvGWU/hsbRlIl+TrdM1YokCWOcrJA7e3BMn784dqYQMvNydTakureI7XiBOZyNMb gENOGvaKEk2NTPZditicLDC3QphSkgIVRF8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675204569321100014 Content-Type: text/plain; charset="utf-8" In preparation for introducing an implementation of the EFI memory attributes protocol that is shared between ARM and AArch64, unify the existing code that converts a page table descriptor into a EFI_MEMORY_xxx bitfield, so it can be called from the generic code. Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 5 +-- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 46 +++++++++++--------- ArmPkg/Drivers/CpuDxe/CpuDxe.h | 5 +++ 3 files changed, 32 insertions(+), 24 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AA= rch64/Mmu.c index 8bb33046e707..4ec9fc0a582c 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -30,13 +30,12 @@ GetRootTranslationTableInfo ( *RootTableEntryCount =3D TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_= LEVEL; } =20 -STATIC UINT64 PageAttributeToGcdAttribute ( - IN UINT64 PageAttributes + IN UINTN PageAttributes ) { - UINT64 GcdAttributes; + UINTN GcdAttributes; =20 switch (PageAttributes & TT_ATTR_INDX_MASK) { case TT_ATTR_INDX_DEVICE_MEMORY: diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 2daf47ba6fe5..9545a1c1d2d3 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -77,39 +77,46 @@ SectionToGcdAttributes ( return EFI_SUCCESS; } =20 -EFI_STATUS -PageToGcdAttributes ( - IN UINT32 PageAttributes, - OUT UINT64 *GcdAttributes +UINT64 +PageAttributeToGcdAttribute ( + IN UINTN PageAttributes ) { - *GcdAttributes =3D 0; + UINT64 GcdAttributes; =20 // determine cacheability attributes switch (PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) { case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED: - *GcdAttributes |=3D EFI_MEMORY_UC; + GcdAttributes =3D EFI_MEMORY_UC; break; case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE: - *GcdAttributes |=3D EFI_MEMORY_UC; + GcdAttributes =3D EFI_MEMORY_UC; break; case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC: - *GcdAttributes |=3D EFI_MEMORY_WT; + GcdAttributes =3D EFI_MEMORY_WT; break; case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC: - *GcdAttributes |=3D EFI_MEMORY_WB; + GcdAttributes =3D EFI_MEMORY_WB; break; case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE: - *GcdAttributes |=3D EFI_MEMORY_WC; + GcdAttributes =3D EFI_MEMORY_WC; break; case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC: - *GcdAttributes |=3D EFI_MEMORY_WB; + GcdAttributes =3D EFI_MEMORY_WB; break; case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE: - *GcdAttributes |=3D EFI_MEMORY_UC; + GcdAttributes =3D EFI_MEMORY_UC; break; default: - return EFI_UNSUPPORTED; + DEBUG (( + DEBUG_ERROR, + "PageAttributeToGcdAttribute: PageAttributes:0x%X not supported.\n= ", + PageAttributes + )); + ASSERT (0); + // The Global Coherency Domain (GCD) value is defined as a bit set. + // Returning 0 means no attribute has been set. + GcdAttributes =3D 0; } =20 // determine protection attributes @@ -126,7 +133,7 @@ PageToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_PAGE_AP_RO_NO: case TT_DESCRIPTOR_PAGE_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_RO; + GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -135,10 +142,10 @@ PageToGcdAttributes ( =20 // now process eXectue Never attribute if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) !=3D 0 ) { - *GcdAttributes |=3D EFI_MEMORY_XP; + GcdAttributes |=3D EFI_MEMORY_XP; } =20 - return EFI_SUCCESS; + return GcdAttributes; } =20 EFI_STATUS @@ -152,7 +159,6 @@ SyncCacheConfigPage ( IN OUT UINT32 *NextSectionAttributes ) { - EFI_STATUS Status; UINT32 i; volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable; UINT32 NextPageAttributes; @@ -183,8 +189,7 @@ SyncCacheConfigPage ( NextPageAttributes =3D PageAttributes; } else if (PageAttributes !=3D NextPageAttributes) { // Convert Section Attributes into GCD Attributes - Status =3D PageToGcdAttributes (NextPageAttributes, &GcdAttributes= ); - ASSERT_EFI_ERROR (Status); + GcdAttributes =3D PageAttributeToGcdAttribute (NextPageAttributes); =20 // update GCD with these changes (this will recurse into our own C= puSetMemoryAttributes below which is OK) SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, = *NextRegionBase, *NextRegionLength, GcdAttributes); @@ -196,8 +201,7 @@ SyncCacheConfigPage ( } } else if (NextPageAttributes !=3D 0) { // Convert Page Attributes into GCD Attributes - Status =3D PageToGcdAttributes (NextPageAttributes, &GcdAttributes); - ASSERT_EFI_ERROR (Status); + GcdAttributes =3D PageAttributeToGcdAttribute (NextPageAttributes); =20 // update GCD with these changes (this will recurse into our own Cpu= SetMemoryAttributes below which is OK) SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *N= extRegionBase, *NextRegionLength, GcdAttributes); diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index ff672390ce51..8933fa90c4ed 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -126,4 +126,9 @@ SetGcdMemorySpaceAttributes ( IN UINT64 Attributes ); =20 +UINT64 +PageAttributeToGcdAttribute ( + IN UINTN PageAttributes + ); + #endif // CPU_DXE_H_ --=20 2.39.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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