From nobody Mon Feb 9 20:34:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99134+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99134+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1674811438; cv=none; d=zohomail.com; s=zohoarc; b=Gcbtmr+isdy+rCKhS5V47uvK00v5NNMLqwpLfI2GACK2mwqltWBiXT87DZ00fH+Vww4DOu3vxonRIuMByZVWRczNVGo9Q2QU33mXzA63175ZMyqeGPFDNUjIdidn/5RsPeXl80JRV/swYaWcOJ+XYInsca7GYc/2qb6JzCtcOJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674811438; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OkThZhasB2NgFB3/JB3X2fwPzsDbLLEoMrNZn7DRLtw=; b=F1TOxrkSAjHvFsaHLO8CcqO7l0CdSEyHWgiUAViQcK7VIowSkWV3ytyg8XIKYsfZzoMT/619Qxj1gqoB3Mq4OcymYv+WXyb1iALXmxhfB08GcXmiYymDAtcyXXqiaaYQGOMm7j2Vvy0JkKqpiDj9pIubE/wmcuzNzrThGfEGCBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99134+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674811438903580.9189206630429; Fri, 27 Jan 2023 01:23:58 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id y4NQYY1788612xFspvEtPWY5; Fri, 27 Jan 2023 01:23:58 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.98412.1674811437430564321 for ; Fri, 27 Jan 2023 01:23:57 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 05B2B2B; Fri, 27 Jan 2023 01:24:39 -0800 (PST) X-Received: from usa.arm.com (a077843.arm.com [10.162.43.190]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A0D313F64C; Fri, 27 Jan 2023 01:23:54 -0800 (PST) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com Subject: [edk2-devel] [edk2-platforms][PATCH V2 4/5] Platform/Sgi: Initialize additional UART controllers Date: Fri, 27 Jan 2023 14:53:37 +0530 Message-Id: <20230127092338.72056-5-vivek.gautam@arm.com> In-Reply-To: <20230127092338.72056-1-vivek.gautam@arm.com> References: <20230127092338.72056-1-vivek.gautam@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.gautam@arm.com X-Gm-Message-State: FXbqLGT3FbKhNhjP7mBOxwHXx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674811438; bh=+9HlfEiPkJ0/79+DLMvbIT5xef21o3cbPLyaxg0hE+s=; h=Cc:Date:From:Reply-To:Subject:To; b=ri6njOh7ZkB29NixDeQB/IyFDLvyP+0XYVoaeivxZPMo8gCLLeeNc/w42rIPrV+5s6l wWsdjXz9jOQ3PnpmoQ5RPhe8kpJ97wclSEPgm770ZJwVtWLuOPXRmVqrBAYmmanmUbScm 2WKGu8CG2jtm0nrTQoJIZzIYFlm7RXcG0bo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674811440762100002 Content-Type: text/plain; charset="utf-8" From: Shriram K The IO virtualization block on reference design platforms allow connecting SoC expansion devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by: Shriram K Signed-off-by: Vivek Gautam --- Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 10 ++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 7 ++- Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 64 ++++++++++++= +++++++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 43 ++++++++++++- Platform/ARM/SgiPkg/SgiPlatform.dec | 1 + 5 files changed, 118 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Plat= form/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf index 9d89314a594e..42feadaf5f6f 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -17,6 +17,7 @@ VirtioDevices.c =20 [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec @@ -37,10 +38,17 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetSupported =20 [FixedPcd] + gArmSgiTokenSpaceGuid.PcdChipCount + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkPeriOffset + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioBlkSize gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioNetSize =20 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + [Depex] TRUE diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Plat= form/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index 1ca7679b4191..4459b20ecb06 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,10 +41,13 @@ gArmPlatformTokenSpaceGuid.PcdCoreCount gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase =20 - gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdDramBlock2Base gArmSgiTokenSpaceGuid.PcdDramBlock2Size gArmSgiTokenSpaceGuid.PcdGicSize + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkPeriOffset + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip =20 gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platfo= rm/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c index 2f72e7152ff3..b3a998bc1585 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -9,6 +9,9 @@ #include #include #include +#include + +#include #include =20 VOID @@ -16,6 +19,64 @@ InitVirtioDevices ( VOID ); =20 +/** + Initialize UART controllers connected to IO Virtualization block. + + Use PL011UartLib Library to initialize UART controllers that are present= in + the SoC expansion block. This SoC expansion block is connected to the IO + virtualization block on Arm infrastructure reference design (RD) platfor= ms. + + @retval None +**/ +STATIC +VOID +InitIoVirtSocExpBlkUartControllers (VOID) +{ + EFI_STATUS Status; + EFI_PARITY_TYPE Parity; + EFI_STOP_BITS_TYPE StopBits; + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + UINT8 DataBits; + UINT8 UartIdx; + UINT32 ChipIdx; + UINT64 UartAddr; + + if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 0) + return; + + ReceiveFifoDepth =3D 0; + Parity =3D 1; + DataBits =3D 8; + StopBits =3D 1; + BaudRate =3D 115200; + + for (ChipIdx =3D 0; ChipIdx < FixedPcdGet32 (PcdChipCount); ChipIdx++) { + for (UartIdx =3D 0; UartIdx < 2; UartIdx++) { + UartAddr =3D SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartId= x); + + Status =3D PL011UartInitializePort ( + (UINTN)UartAddr, + FixedPcdGet32 (PcdSerialDbgUartClkInHz), + &BaudRate, + &ReceiveFifoDepth, + &Parity, + &DataBits, + &StopBits + ); + + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Failed to init PL011_UART%u on IO Virt Block port, status: %r\n= ", + UartIdx, + Status + )); + } + } + } +} + EFI_STATUS EFIAPI ArmSgiPkgEntryPoint ( @@ -32,6 +93,7 @@ ArmSgiPkgEntryPoint ( } =20 InitVirtioDevices (); + InitIoVirtSocExpBlkUartControllers (); =20 return Status; } diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Pla= tform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index 8139b75d8ee4..08aa9bf64940 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -13,11 +13,23 @@ #include #include =20 +#include #include =20 // Total number of descriptors, including the final "end-of-table" descrip= tor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \ - (14 + (FixedPcdGet32 (PcdChipCount) * 2)) +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS = \ + ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + = \ + (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * = \ + FixedPcdGet32 (PcdChipCount) * 2)) + +// Memory Map descriptor for IO Virtualization SoC Expansion Block UART +#define IO_VIRT_SOC_EXP_BLK_UART_MMAP(UartIdx, ChipIdx) = \ + VirtualMemoryTable[++Index].PhysicalBase =3D = \ + SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartIdx); = \ + VirtualMemoryTable[Index].VirtualBase =3D = \ + SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartIdx); = \ + VirtualMemoryTable[Index].Length =3D SIZE_64KB; = \ + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; =20 /** Returns the Virtual Memory Map of the platform. @@ -171,6 +183,31 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D SIZE_64KB; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 +#if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 1) + // Chip-0 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 0) + // Chip-0 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 0) +#if (FixedPcdGet32 (PcdChipCount) > 1) + // Chip-1 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 1) + // Chip-1 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 1) +#if (FixedPcdGet32 (PcdChipCount) > 2) + // Chip-2 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 2) + // Chip-2 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 2) +#if (FixedPcdGet32 (PcdChipCount) > 3) + // Chip-3 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 3) + // Chip-3 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 3) +#endif +#endif +#endif +#endif + // DDR - (2GB - 16MB) VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiP= latform.dec index 407f03c1c3e8..43d350ec48bb 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -102,6 +102,7 @@ gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0|UINT64|0x0000002B gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkPeriOffset|0|UINT32|0x0000002C gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkResourceSize|0|UINT32|0x0000002D + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable|0|UINT32|0x0000002E =20 [Ppis] gNtFwConfigDtInfoPpiGuid =3D { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0= x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } } --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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