From nobody Mon Feb 9 21:12:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99023+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99023+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1674654997; cv=none; d=zohomail.com; s=zohoarc; b=eI6Pajz2uHPGC4CiFlclwZtl68yNU3E635ktElLeq7cxHt0Wsd0sidFdeEBRDwaaOjpOU4kkgEY18kon6MSLHT8d/EJFx48ZuXq29IEFOJaINUJx+Bu4pfQjScdo3/tQ50CJFeBsbHSULfSIVrC3DrIboRYrgVTS+SJycXelwm0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674654997; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Y434yhgE95ZyP2YaO0kDEkAWf2+jtWjcGp2ylqu5V74=; b=RJpPD6k/BNW48kwp9GsUGFAC2laftvb4l1cVCPubTIHfwJEnZxCPku4Ae+IIpBqNSmqjVFkNp2FjtTeVRtbcJ9LWSz0f1pPERzsh3jEn/dl7ME4TfnIiimx9KmnFvHHxJ7TsI6LyLnRELfOCev+j1XmJ11bN8BcAwOxhbjpIhnQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99023+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674654997613284.1136566730837; Wed, 25 Jan 2023 05:56:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id RwaLYY1788612xMfMVloalMd; Wed, 25 Jan 2023 05:56:37 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.45349.1674654996319482684 for ; Wed, 25 Jan 2023 05:56:36 -0800 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-481-84fz1qm1MpaHJthsRq5gfw-1; Wed, 25 Jan 2023 08:56:32 -0500 X-MC-Unique: 84fz1qm1MpaHJthsRq5gfw-1 X-Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C50CE1991C42; Wed, 25 Jan 2023 13:56:31 +0000 (UTC) X-Received: from sirius.home.kraxel.org (unknown [10.39.192.186]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 67DC01121333; Wed, 25 Jan 2023 13:56:31 +0000 (UTC) X-Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 4594818009D9; Wed, 25 Jan 2023 14:56:28 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Min Xu , Erdem Aktas , Ard Biesheuvel , Pawel Polawski , Julien Grall , Oliver Steffen , Tom Lendacky , Gerd Hoffmann , Jordan Justen , Jiewen Yao , Anthony Perard , Michael Roth , James Bottomley Subject: [edk2-devel] [PATCH 3/3] OvmfPkg/PlatformInitLib: simplify mtrr setup Date: Wed, 25 Jan 2023 14:56:28 +0100 Message-Id: <20230125135628.1896096-4-kraxel@redhat.com> In-Reply-To: <20230125135628.1896096-1-kraxel@redhat.com> References: <20230125135628.1896096-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com X-Gm-Message-State: FiAWjGn9oHXYsPHsBk8XRk7nx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674654997; bh=0+N/vKPsVFhysQU6zZZkzZbeL8uOV4k4nW8OTmOyl9w=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ECJNNuoiBX4Fu0mUDAynIIg4QIzSEER+CYWoZylAkbpqQxgiQW+uTKCxO3QPIXrqMTP k68kolMBPuojU6calTzirr0xDc9t0BmV0ir8UyJr7s4p95+ZLeF9femiG2O5cbns3EyRu Ay3GW2f3XMRnz2msUNUnyEDWdmOWwc/WO/w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674654999860100001 Content-Type: text/plain; charset="utf-8"; x-default="true" With the new mmconfig location at 0xe0000000 above the 32-bit PCI MMIO window we don't have to special-case the mmconfig xbar any more. We'll just add a mtrr uncachable entry starting at MMIO window base and ending at 4GB. Update comments to match reality. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 36 +++++++++------------ 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/= PlatformInitLib/MemDetect.c index 5aeeeff89f57..fd5ae42243ba 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -61,33 +61,20 @@ PlatformQemuUc32BaseInitialization ( return; } =20 + ASSERT ( + PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID || + PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID + ); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); =20 if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >=3D PlatformInfoHob->LowM= emory); - - if (PlatformInfoHob->LowMemory <=3D BASE_2GB) { - // Newer qemu with gigabyte aligned memory, - // 32-bit pci mmio window is 2G -> 4G then. - PlatformInfoHob->Uc32Base =3D BASE_2GB; - } else { - // - // On q35, the 32-bit area that we'll mark as UC, through variable M= TRRs, - // starts at PcdPciExpressBaseAddress. The platform DSC is responsib= le for - // setting PcdPciExpressBaseAddress such that describing the - // [PcdPciExpressBaseAddress, 4GB) range require a very small number= of - // variable MTRRs (preferably 1 or 2). - // - PlatformInfoHob->Uc32Base =3D (UINT32)PcdGet64 (PcdPciExpressBaseAdd= ress); - } - - return; } =20 - ASSERT (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); // - // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one + // Start with the [LowerMemorySize, 4GB) range. Make sure one // variable MTRR suffices by truncating the size to a whole power of two, // while keeping the end affixed to 4GB. This will round the base up. // @@ -1027,6 +1014,13 @@ PlatformQemuInitializeRam ( // practically any alignment, and we may not have enough variable MTRRs = to // cover it exactly. // + // Because of that PlatformQemuUc32BaseInitialization() will round + // up PlatformInfoHob->LowMemory to make sure a single mtrr register + // is enough. The the result will be stored in + // PlatformInfoHob->Uc32Base. On a typical qemu configuration with + // gigabyte-alignment being used LowMemory will be 2 or 3 GB and no + // rounding is needed, so LowMemory and Uc32Base will be identical. + // if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId !=3D CLOUDHV= _DEVICE_ID)) { MtrrGetAllMtrrs (&MtrrSettings); =20 @@ -1056,8 +1050,8 @@ PlatformQemuInitializeRam ( ASSERT_EFI_ERROR (Status); =20 // - // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI - // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. + // Set the memory range from the start of the 32-bit PCI MMIO + // aperture to 4GB as uncacheable. // Status =3D MtrrSetMemoryAttribute ( PlatformInfoHob->Uc32Base, --=20 2.39.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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