From nobody Mon Feb 9 18:19:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99021+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99021+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1674654996; cv=none; d=zohomail.com; s=zohoarc; b=dsylQAc9Gcn1y0DXSwRybR0wTbOkQlrfKpGLr95+OfyUwMVDCIB9vdklqreW/mtbPcWeVkPQ96pnDXsOZNVXSzH02xivA1Ijv09D3s1+3aVe8HhoQ4aADKKz/Ns8ghjoi327A/N9Bw2zSzOQRJ2F/aeseV+eibWACKZRNQ7yZYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674654996; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=BKMNmqAijpQi15iUrGGVVNsjQeAG4kfCIAvbRGgAQW8=; b=jmzUaN+bUsLyUKZ0C/oTAV8ILetNIF5fZVN8qm8d7WjnNzYJKDgXf6Wcd+8b/X/mpXx0hJ0cWuXZCuYk9bsLLOMGOFuQOloQ9xOlC/C/ovilHZayO5Hc7ti7xnUp5FhlE2g4cy0tJFgrc0nHYvdNK0hYQdvp+rqzhT4DcPC7tro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99021+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674654996323986.253691181088; Wed, 25 Jan 2023 05:56:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ofP9YY1788612x4x2q8WRPcw; Wed, 25 Jan 2023 05:56:36 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web11.45459.1674654995059731095 for ; Wed, 25 Jan 2023 05:56:35 -0800 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-367-zohxGCClPfu8GHDRhPrf5w-1; Wed, 25 Jan 2023 08:56:31 -0500 X-MC-Unique: zohxGCClPfu8GHDRhPrf5w-1 X-Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 26504101A52E; Wed, 25 Jan 2023 13:56:30 +0000 (UTC) X-Received: from sirius.home.kraxel.org (unknown [10.39.192.186]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BC2DB40C200C; Wed, 25 Jan 2023 13:56:29 +0000 (UTC) X-Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 3BC3718009C0; Wed, 25 Jan 2023 14:56:28 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Min Xu , Erdem Aktas , Ard Biesheuvel , Pawel Polawski , Julien Grall , Oliver Steffen , Tom Lendacky , Gerd Hoffmann , Jordan Justen , Jiewen Yao , Anthony Perard , Michael Roth , James Bottomley Subject: [edk2-devel] [PATCH 1/3] OvmfPkg/PlatformInitLib: update address space layout comment Date: Wed, 25 Jan 2023 14:56:26 +0100 Message-Id: <20230125135628.1896096-2-kraxel@redhat.com> In-Reply-To: <20230125135628.1896096-1-kraxel@redhat.com> References: <20230125135628.1896096-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com X-Gm-Message-State: HrQsX3hy2HdAyMQYMo59VTwex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674654996; bh=c+ZAMIfyc4UJCtRoyYT/kK4h9BgRwNhbDPdL5Cz7lSo=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=VkXdU16cHk0iMENJnY2SIyJajX2syFQq7Fs850UGPMxwnL3psH+x/eH/nWOL/iaZY8C vRemejQYI3asG7sycqmQ9gVmRYutccWhFDRktdE6ZeooO/Zds+/x7/OUIexNWpF6vdcRV hasASI4S0d4AiSindkKiq7+B9D1HoPkPpvc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674654997634100002 Content-Type: text/plain; charset="utf-8"; x-default="true" Move the commment up so it is placed just before the address space calculations start. Also add q35 memory layout. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/Platform.c | 36 ++++++++++++---------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Platform.c index 9fee6e481038..678e8e329023 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -152,26 +152,12 @@ PlatformMemMapInitialization ( return; } =20 - PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); - PciExBarBase =3D 0; - if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // The MMCONFIG area is expected to fall between the top of low RAM and - // the base of the 32-bit PCI host aperture. - // - PciExBarBase =3D PcdGet64 (PcdPciExpressBaseAddress); - ASSERT (PlatformInfoHob->LowMemory <=3D PciExBarBase); - ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); - } else { - ASSERT (PlatformInfoHob->LowMemory <=3D PlatformInfoHob->Uc32Base); - PciBase =3D PlatformInfoHob->Uc32Base; - } - // // address purpose size // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) + // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) (pc) + // 0xB0000000 MMCONFIG 256 MB (q35) + // 0xC0000000 PCI MMIO 960 MB (q35) // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB @@ -181,6 +167,22 @@ PlatformMemMapInitialization ( // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PciExBarBase =3D 0; + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // The MMCONFIG area is expected to fall between the top of low RAM and + // the base of the 32-bit PCI host aperture. + // + PciExBarBase =3D PcdGet64 (PcdPciExpressBaseAddress); + ASSERT (PlatformInfoHob->LowMemory <=3D PciExBarBase); + ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); + PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + } else { + ASSERT (PlatformInfoHob->LowMemory <=3D PlatformInfoHob->Uc32Base); + PciBase =3D PlatformInfoHob->Uc32Base; + } + PciSize =3D 0xFC000000 - PciBase; PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); =20 --=20 2.39.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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