From nobody Mon Feb 9 01:22:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98485+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98485+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673623851; cv=none; d=zohomail.com; s=zohoarc; b=KL8s6cKV1TwkTBaKDEKSU/zBkM1VtlBZseTxglDyoJE4/3yLwoozsCwhhh+iSijWgQIa8C/emCxmqyGe40SmXranLjcaLWoJzihpMKg2Gs44RVCyUfVVQIMqf6ucVmu+NI53um1615RrfxgnPHSptLCESczUWJt6s+77wvXmwbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673623851; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=cPickhteal7Q75gXNCSLbaqRn1nB4qXupia37wJ5eAk=; b=b4ZB3QU+E02uQFAq0PpY5fpPWVBGUYKZZhr9pfuzcRAjLZDbu+PC7BMvH+Vw5bjYyK28HLI6kAAdKCOJrEVEGVyAFnkA7UnGMlZzxpWQRjTbNvL+XvE+5j8zqJswlnQe4SKVjf+MNWM9K6LY0RL2pGUE23AkB9dIUy7VELiLO5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98485+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673623851619368.91496500245296; Fri, 13 Jan 2023 07:30:51 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6SxjYY1788612x5iGiXwx13s; Fri, 13 Jan 2023 07:30:51 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.90164.1673623849597548955 for ; Fri, 13 Jan 2023 07:30:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="410251792" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="410251792" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 07:30:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="782182322" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="782182322" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga004.jf.intel.com with ESMTP; 13 Jan 2023 07:30:48 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 1/4] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Fri, 13 Jan 2023 23:30:42 +0800 Message-Id: <20230113153045.13060-2-jiaxin.wu@intel.com> In-Reply-To: <20230113153045.13060-1-jiaxin.wu@intel.com> References: <20230113153045.13060-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: ifynfQM6noTdOuEBmyNgVwZBx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673623851; bh=j38rNUOU/YbXZSCHhBYSDlG9028nqQ9fJyTiU3vbVhE=; h=Cc:Date:From:Reply-To:Subject:To; b=nrkPlF3My7VIE24KfQlVejAH3ZC182N9PRfa7tFTtht9RPa6iIpQzsrotPzsQImeuXR hGIneZyCvwD94DqBiEyXCkAD+XqiAf4wzEuICfhhcAT6XVGEGyDeRSC+Umdy+npY8FdeT SbwZ0B3D7id4Zm9DXqH6Yy55QbbSwin9moA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673623852489100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from CPU perspective is to program the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocated happens in one PEI module ahead of the PiSmmCpuDxeSmm, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver which runs at a later phase about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver shall install the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall program the new SMBASE itself. This patch adds the SMM Base HOB, which can be produced by any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for reach Processors. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 49 ++++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 2 files changed, 52 insertions(+) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid= /SmmBaseHob.h new file mode 100644 index 0000000000..6ed32481dc --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,49 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase in array for each Processors. + + The default SMBASE for the x86 processor is 0x30000. When SMI happens, + CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state + area is within SMBASE+0x10000. + + One of the SMM initialization from CPU perspective is to program the + new SMBASE (in TSEG range) for each CPU thread. When the SMBASE update + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB + in HOB database which tells the PiSmmCpuDxeSmm driver which runs at a + later phase about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm + driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 + for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver + shall program the new SMBASE itself. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#include +#include + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d,= 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// Describes the Number of all max supported processors. + /// + UINT64 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..2afd08cdd2 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} =20 + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid =3D { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c= , 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94= , 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid =3D { 0xaa00d50b, 0x4911, 0x428f, { 0= xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98485): https://edk2.groups.io/g/devel/message/98485 Mute This Topic: https://groups.io/mt/96247961/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Feb 9 01:22:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98486+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98486+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673623854; cv=none; d=zohomail.com; s=zohoarc; b=ApPO0h6k5Q4oycStyV00ERhPGAHLDziJ7i0sWYyrjF2SWEs0DUOg4Covw6jtumMs0S6UFz5dPUiTl8Hd0rqcTLwvXxZjM2KmMlqPRNlI7Ne4wVeRgZ58EXhZWHjNfQ+HSaGG+Mn1rtTH9qM+Xwf+5xZGblCazGJfb2Lmnb8rKkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673623854; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ghv70541RmQosQHvrH2ARgRJGZ4CrcYR4o1OqKFsjMo=; b=OzJ54/uXj45/ga4QjvlaLIEIExMOmL0Ryzraw1rZlEIruY1WS9j+JHlisPetevV5d++eh2o/Tu22fT8n2P1Tu2VMEJ3dGJTTgM4CWNy5IwXvbJ7MMVhruOgKIXnd+Mn2ABWq0KMoeBvgz0N5Bhi1FaDfBgQ3oQT2QddryJml6LM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98486+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673623854359112.502240635818; Fri, 13 Jan 2023 07:30:54 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id cF03YY1788612xdiNniYK9CQ; Fri, 13 Jan 2023 07:30:54 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.90164.1673623849597548955 for ; Fri, 13 Jan 2023 07:30:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="410251808" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="410251808" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 07:30:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="782182343" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="782182343" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga004.jf.intel.com with ESMTP; 13 Jan 2023 07:30:50 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 2/4] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info Date: Fri, 13 Jan 2023 23:30:43 +0800 Message-Id: <20230113153045.13060-3-jiaxin.wu@intel.com> In-Reply-To: <20230113153045.13060-1-jiaxin.wu@intel.com> References: <20230113153045.13060-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: ZrPhvEKu1GSBRMUgKD8u3G1Px1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673623854; bh=pFmSAlfQaghdBQFcPqtnUbvls2yYeUPr8EBJah8KZ0I=; h=Cc:Date:From:Reply-To:Subject:To; b=F5/aJBytHJRFLgCgIIcPsy7zX34xXGsqQgqI2hfiN0mKG5O7qrzvdYygI868fTiUFPF V/tIO6EWl5KkaLgWct3lJ9GknIVqVN0VLr/cow2pRweitwk4muMCpzrNpu9EVYxtn3QJq Uuloz2l3gB2Dh+Gc2hsIQhW/cgDNouBt9nw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673623856493100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PiSmmCpuDxeSmm will retrieve the SMBASE addresses from SMM Base Hob and installs the SMI handler at [SMBASE+8000h] for each processor instead of relocating SMM Base addresses from SMRAM again. With SMM Base Hob, PiSmmCpuDxeSmm does not need the RSM instruction to reload the SMBASE register with the new allocated SMBASE each time when it exits SMM. SMBASE Register for each processors have already been programmed and all SMBASE address have recorded in SMM Base Hob. So the same default SMBASE Address (0x30000) will not be used, thus the CPUs over-writing each other's SMM Save State Area will not happen. This way makes the first SMI init can be executed in parallel and save boot time on multi-core system. Mainly changes as below: *Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. *Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init before normal SMI sources happen. *Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 21 ++- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 29 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 185 +++++++++++++++++++++--= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 31 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 5 files changed, 217 insertions(+), 50 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index fb4a44eab6..66b05e74ed 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -822,13 +822,30 @@ SmmRestoreCpu ( // InitializeCpuBeforeRebase (); } =20 // - // Restore SMBASE for BSP and all APs + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. // - SmmRelocateBases (); + mSmmRelocated =3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) !=3D NULL= ); + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! + // + if (!mSmmRelocated) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execut= e first SMI init. + // + ExecuteFirstSmiInit (); + } =20 // // Skip initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index a0967eb69c..b64efd327c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1721,17 +1721,40 @@ SmiRendezvous ( UINTN Index; UINTN Cr2; =20 ASSERT (CpuIndex < mMaxNumberOfCpus); =20 + if (mSmmRelocated) { + ASSERT (mSmmInitialized !=3D NULL); + } + // // Save Cr2 because Page Fault exception in SMM may override its value, // when using on-demand paging for above 4G memory. // Cr2 =3D 0; SaveCr2 (&Cr2); =20 + if (mSmmRelocated && !mSmmInitialized[CpuIndex]) { + // + // Perform SmmInitHandler for CpuIndex + // + SmmInitHandler (); + + // + // Restore Cr2 + // + RestoreCr2 (Cr2); + + // + // Mark the first SMI init for CpuIndex has been done so as to avoid t= he reentry. + // + mSmmInitialized[CpuIndex] =3D TRUE; + + return; + } + // // Call the user register Startup function first. // if (mSmmMpSyncData->StartupProcedure !=3D NULL) { mSmmMpSyncData->StartupProcedure (mSmmMpSyncData->StartupProcArgs); @@ -1882,13 +1905,13 @@ Exit: // RestoreCr2 (Cr2); } =20 /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIn= dex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackag= eFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which means not + specified yet. =20 **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..2ec423355f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -57,11 +57,10 @@ SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate =3D &mSmmCpuPriva= teData; =20 // // SMM Relocation variables // volatile BOOLEAN *mRebased; -volatile BOOLEAN mIsBsp; =20 /// /// Handle for the SMM CPU Protocol /// EFI_HANDLE mSmmCpuHandle =3D NULL; @@ -83,10 +82,14 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribut= e =3D { EdkiiSmmClearMemoryAttributes }; =20 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; =20 +BOOLEAN mSmmRelocated =3D FALSE; +BOOLEAN *mSmmInitialized =3D NULL; +UINT32 mBspApicId =3D 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -341,60 +344,109 @@ VOID EFIAPI SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; + BOOLEAN IsBsp; =20 // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId =3D GetApicId (); =20 + IsBsp =3D (BOOLEAN)(mBspApicId =3D=3D ApicId); + ASSERT (mNumberOfCpus <=3D mMaxNumberOfCpus); =20 for (Index =3D 0; Index < mNumberOfCpus; Index++) { if (ApicId =3D=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Process= orId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsBsp, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); =20 if (!mSmmS3Flag) { // // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); - } - - if (mIsBsp) { + } else if (IsBsp) { // // BSP rebase is already done above. // Initialize private data during S3 resume // InitializeMpSyncData (); } =20 - // - // Hook return after RSM to set SMM re-based flag - // - SemaphoreHook (Index, &mRebased[Index]); + if (!mSmmRelocated) { + // + // Hook return after RSM to set SMM re-based flag + // + SemaphoreHook (Index, &mRebased[Index]); + } =20 return; } } =20 ASSERT (FALSE); } =20 +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute firs= t SMI init. + +**/ +VOID +EFIAPI +ExecuteFirstSmiInit ( + VOID + ) +{ + UINTN Index; + + // + // Reset the mSmmInitialized to false. + // + if (mSmmInitialized =3D=3D NULL) { + mSmmInitialized =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * mMaxNu= mberOfCpus); + } + + ASSERT (mSmmInitialized !=3D NULL); + if (mSmmInitialized =3D=3D NULL) { + return; + } + + ZeroMem (mSmmInitialized, sizeof (BOOLEAN) * mMaxNumberOfCpus); + + // + // Get the BSP ApicId. + // + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] =3D=3D FALSE) { + } + } +} + /** Relocate SmmBases for each processor. =20 Execute on first boot and all S3 resumes =20 @@ -407,11 +459,10 @@ SmmRelocateBases ( { UINT8 BakBuf[BACK_BUF_SIZE]; SMRAM_SAVE_STATE_MAP BakBuf2; SMRAM_SAVE_STATE_MAP *CpuStatePtr; UINT8 *U8Ptr; - UINT32 ApicId; UINTN Index; UINTN BspIndex; =20 // // Make sure the reserved size is large enough for procedure SmmInitTemp= late. @@ -448,21 +499,20 @@ SmmRelocateBases ( CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize); =20 // // Retrieve the local APIC ID of current processor // - ApicId =3D GetApicId (); + mBspApicId =3D GetApicId (); =20 // // Relocate SM bases for all APs // This is APs' 1st SMI - rebase will be done here, and APs' default SMI= handler will be overridden by gcSmmInitTemplate // - mIsBsp =3D FALSE; BspIndex =3D (UINTN)-1; for (Index =3D 0; Index < mNumberOfCpus; Index++) { mRebased[Index] =3D FALSE; - if (ApicId !=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Processor= Id) { + if (mBspApicId !=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Proce= ssorId) { SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId= ); // // Wait for this AP to finish its 1st SMI // while (!mRebased[Index]) { @@ -477,12 +527,11 @@ SmmRelocateBases ( =20 // // Relocate BSP's SMM base // ASSERT (BspIndex !=3D (UINTN)-1); - mIsBsp =3D TRUE; - SendSmiIpi (ApicId); + SendSmiIpi (mBspApicId); // // Wait for the BSP to finish its 1st SMI // while (!mRebased[BspIndex]) { } @@ -561,10 +610,15 @@ PiCpuSmmEntry ( UINT32 RegEcx; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; UINT32 Cr3; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + + GuidHob =3D NULL; + SmmBaseHobData =3D NULL; =20 // // Initialize address fixup // PiSmmCpuSmmInitFixupAddress (); @@ -789,30 +843,55 @@ PiCpuSmmEntry ( // context must be reduced. // ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // - // Allocate buffer for all of the tiles. + // Check whether the Required TileSize is enough. // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.11 SMBASE Relocation - // For Pentium and Intel486 processors, the SMBASE values must be - // aligned on a 32-KByte boundary or the processor will enter shutdown - // state during the execution of a RSM instruction. + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Re= quired TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE_8= KB)); + CpuDeadLoop (); + return RETURN_BUFFER_TOO_SMALL; + } + // - // Intel486 processors: FamilyId is 4 - // Pentium processors : FamilyId is 5 + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. // - BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfC= pus - 1)); - if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + GuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); + if (GuidHob !=3D NULL) { + SmmBaseHobData =3D GET_GUID_HOB_DATA (GuidHob); + + ASSERT (SmmBaseHobData->NumberOfProcessors =3D=3D mMaxNumberOfCpus); + mSmmRelocated =3D TRUE; } else { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); - } + // + // When the HOB doesn't exist, allocate new SMBASE itself. + // + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + // + // Allocate buffer for all of the tiles. + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.11 SMBASE Relocation + // For Pentium and Intel486 processors, the SMBASE values must be + // aligned on a 32-KByte boundary or the processor will enter shutdo= wn + // state during the execution of a RSM instruction. + // + // Intel486 processors: FamilyId is 4 + // Pentium processors : FamilyId is 5 + // + BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberO= fCpus - 1)); + if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + } else { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); + } =20 - ASSERT (Buffer !=3D NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer,= EFI_PAGES_TO_SIZE (BufferPages))); + ASSERT (Buffer !=3D NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%= 08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } =20 // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // gSmmCpuPrivate->ProcessorInfo =3D (EFI_PROCESSOR_INFORMATION *)AllocateP= ool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); @@ -843,11 +922,12 @@ PiCpuSmmEntry ( // Retrieve APIC ID of each enabled processor from the MP Services proto= col. // Also compute the SMBASE address, CPU Save State address, and CPU Save= state // size for each CPU in the platform // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Ti= leSize - SMM_HANDLER_OFFSET; + mCpuHotPlugData.SmBase[Index] =3D mSmmRelocated ? (UINTN)SmmBaseHobDat= a->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof (SMRAM_SAVE_STATE_M= AP); gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { @@ -956,21 +1036,27 @@ PiCpuSmmEntry ( // Initialize IDT // InitializeSmmIdt (); =20 // - // Relocate SMM Base addresses to the ones allocated from SMRAM + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberO= fCpus); - ASSERT (mRebased !=3D NULL); - SmmRelocateBases (); + if (!mSmmRelocated) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumbe= rOfCpus); + ASSERT (mRebased !=3D NULL); + SmmRelocateBases (); =20 - // - // Call hook for BSP to perform extra actions in normal mode after all - // SMM base addresses have been relocated on all CPUs - // - SmmCpuFeaturesSmmRelocationComplete (); + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } =20 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); =20 // // SMM Time initialization @@ -997,10 +1083,25 @@ PiCpuSmmEntry ( ); } } } =20 + // + // For relocated SMBASE, some MSRs & CSRs are still required to be confi= gured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM I= PI) to execute first SMI init. + // + if (mSmmRelocated) { + ExecuteFirstSmiInit (); + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + // // Fill in SMM Reserved Regions // gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart =3D 0; gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize =3D 0; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 5f0a38e400..bddd0b5798 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -23,10 +23,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =20 #include #include #include +#include =20 #include #include #include #include @@ -346,10 +347,30 @@ SmmWriteSaveState ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer ); =20 +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID + ); + +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute firs= t SMI init. + +**/ +VOID +EFIAPI +ExecuteFirstSmiInit ( + VOID + ); + /** Read a CPU Save State register on the target processor. =20 This function abstracts the differences that whether the CPU Save State re= gister is in the IA32 CPU Save State Map or X64 CPU Save State Map. @@ -400,10 +421,14 @@ WriteSaveStateRegister ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ); =20 +extern BOOLEAN mSmmRelocated; +extern BOOLEAN *mSmmInitialized; +extern UINT32 mBspApicId; + extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; extern UINT32 mSmmCr0; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; @@ -1486,13 +1511,13 @@ RegisterStartupProcedure ( IN EFI_AP_PROCEDURE Procedure, IN OUT VOID *ProcedureArguments OPTIONAL ); =20 /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIn= dex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackag= eFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which means not + specified yet. =20 **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index b4b327f60c..6dbed17b96 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -112,10 +112,11 @@ =20 [Guids] gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # = it is used for S3 boot. gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONS= UMES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98486): https://edk2.groups.io/g/devel/message/98486 Mute This Topic: https://groups.io/mt/96247964/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Feb 9 01:22:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98487+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98487+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673623856; cv=none; d=zohomail.com; s=zohoarc; b=F7DUSsTlQRVAiNUr2MbS3t+b6yXTm0HQpdEhrOkw9/vz90gEiiG+WFXr7Sevgnl5sY6pOJ7nx/EXglsBEjqKwJQ7kaPlavN5TGwTWze9QDoS1jw3HCeEotCurmMHHgdcwTZz4Jgw8mrGMjVwxdVvINZ8oBjfMhBwNIPlDaENGYw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673623856; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=CbP5gWfa9LviEroBKZzOR4tsoKEmDhXoTKCUOIiXGGU=; b=Ofmy7sD7Rt5il/uv4q4t3mt/gnmKIDHVET9DhY1Evo20mZYNQl00lchnQWsHH9KMZ1Mq1LbmzAruIdVC0Cf2ahFUZfFZzWLc1vQzYacoxUMcXaZMPeKx0h//rs/wikiRjwj1GzmawQcTl8G8MDNWDFeRSEB5HMI+i5NFBz7G3G8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98487+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673623856573797.7719325178692; Fri, 13 Jan 2023 07:30:56 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id wguOYY1788612x2nzohVmePt; Fri, 13 Jan 2023 07:30:55 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.90164.1673623849597548955 for ; Fri, 13 Jan 2023 07:30:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="410251841" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="410251841" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 07:30:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="782182349" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="782182349" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga004.jf.intel.com with ESMTP; 13 Jan 2023 07:30:53 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/SmmCpuFeaturesLib: Skip to configure SMBASE Date: Fri, 13 Jan 2023 23:30:44 +0800 Message-Id: <20230113153045.13060-4-jiaxin.wu@intel.com> In-Reply-To: <20230113153045.13060-1-jiaxin.wu@intel.com> References: <20230113153045.13060-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: M87f1mwv7nnk3vuY23kuuk1hx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673623855; bh=KGEbnMYmFjzJIhxZrItBHjhu8rz09Cgkg8LGtvucON4=; h=Cc:Date:From:Reply-To:Subject:To; b=VoaTwoDfLuLPp+uY8rCJXZ7fGhVJmoK3bSeGydhMv4HdiNNjfaP/Xdhkl9VEAZmEisx qI2SGWB9/80AYB6E+tjGtbut/sk+3Al7MTVctZjTcN9+z0p7lQmUOWGd0ccTMwzgBbcH6 EYxD4BdPFnTbS5qW6KnvRrFHdZXwxEVyfVE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673623858496100006 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h | 2 ++ .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c | 23 ++++++++++++++++++= +--- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 ++++ .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 1 + UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1 - .../StandaloneMmCpuFeaturesLib.inf | 4 ++++ 6 files changed, 31 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h index fd3e902547..c2e4fbe96b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h @@ -7,15 +7,17 @@ **/ =20 #ifndef CPU_FEATURES_LIB_H_ #define CPU_FEATURES_LIB_H_ =20 +#include #include #include #include #include #include +#include =20 /** Performs library initialization. =20 This initialization function contains common functionality shared betwen= all diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index d5eaaa7a99..7c3836286b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -36,10 +36,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmmCpuFeaturesSmmRelocated; + // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs =3D TRUE; =20 @@ -142,10 +148,16 @@ CpuFeaturesLibInitialization ( // // Allocate array for state of SMRR enable on all CPUs // mSmrrEnabled =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLo= gicalProcessorNumber ()); ASSERT (mSmrrEnabled !=3D NULL); + + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + mSmmCpuFeaturesSmmRelocated =3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobG= uid) !=3D NULL); } =20 /** Called during the very first SMI into System Management Mode to initiali= ze CPU features, including SMBASE, for the currently executing CPU. Since = this @@ -185,14 +197,19 @@ SmmCpuFeaturesInitializeProcessor ( UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmCpuFeaturesSmmRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_S= MBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily // diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9ac7dde78f..280a4b8b39 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -31,10 +31,14 @@ [LibraryClasses] BaseLib PcdLib MemoryAllocationLib DebugLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 86d367e0a0..4bb045244b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -62,10 +62,11 @@ =20 [Guids] gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## System= Table gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## System= Table + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOME= TIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 3cf162ada0..455fe83991 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -6,11 +6,10 @@ =20 **/ =20 #include #include -#include #include #include #include #include #include diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLi= b.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index b1f60a5505..63259e44e7 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -32,10 +32,14 @@ [LibraryClasses] BaseLib DebugLib MemoryAllocationLib PcdLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98487): https://edk2.groups.io/g/devel/message/98487 Mute This Topic: https://groups.io/mt/96247965/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Feb 9 01:22:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98488+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98488+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673623858; cv=none; d=zohomail.com; s=zohoarc; b=TdP9yDi24C8//NZX+yJDsiYPrEJIpJ9XFleQ3jZ4d5xaJru3X+bf3A3Nbd+71pkx5Ef1YuErh+Wz34tlK6GEQWxuFK89ksNyyAKm0qizbNS4aKURFKdWkuzHkfZqHgefooSftTDnvNX6GrqnDJ1LxkAbb9OiDuENgskOi6Wvzb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673623858; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=eTosJ6EuK19kU6KNG0BQ0MewqEE5xXFIgI/YfneHEQ4=; b=PHPwkKQ2DY1/0wXk7b7bAhgCvr0Bxp0t8WlbSJ9/OhziAY+qRSVyu58VYYb6rblkKF5pAH/U0qWb4It7rJRom3gQVuWEtS0s0yK8tiHDVQ9+CuPnpLeA79OUs21X22IxxExRs64gR49p/wtSj8sHdbZlzyS7K75i4t7vwLTGBxM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98488+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673623858578749.0782888431719; Fri, 13 Jan 2023 07:30:58 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id O6EwYY1788612xQxWxUHZ7vB; Fri, 13 Jan 2023 07:30:58 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.90164.1673623849597548955 for ; Fri, 13 Jan 2023 07:30:57 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="410251866" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="410251866" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 07:30:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="782182356" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="782182356" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga004.jf.intel.com with ESMTP; 13 Jan 2023 07:30:55 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 4/4] OvmfPkg/SmmCpuFeaturesLib: Skip to configure SMBASE Date: Fri, 13 Jan 2023 23:30:45 +0800 Message-Id: <20230113153045.13060-5-jiaxin.wu@intel.com> In-Reply-To: <20230113153045.13060-1-jiaxin.wu@intel.com> References: <20230113153045.13060-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: f0W58EJpxnDzbp2ZCRwxg7VLx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673623858; bh=pKhGeTAByLuPrcmse4fHYe7IETimE4iBhPVpLMe1rtg=; h=Cc:Date:From:Reply-To:Subject:To; b=Yt82Z4hym7PPNU05DTbQmCQ0M94AHk7e8AYmnW1G7jO6RQUyJw/GqDFipF+Y8SFDQ09 HJ+UeYOhme5CGBhkrTUhQlZb+VPfSo/a4Za89QSPrOcMf9a/MoN4vMo5Suhau8HaN7slF 9HL75wYOelXZ3krwNer+wz1gK6Jhg41dXtI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673623860472100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 37 ++++++++++++++++--= ---- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 +++ 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 6693666d04..d2841af6a4 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -15,20 +15,28 @@ #include #include #include #include #include +#include #include #include #include #include +#include =20 // // EFER register LMA bit // #define LMA BIT10 =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmmCpuFeaturesSmmRelocated; + /** The constructor function =20 @param[in] ImageHandle The firmware allocated handle for the EFI image. @param[in] SystemTable A pointer to the EFI System Table. @@ -41,10 +49,16 @@ EFIAPI SmmCpuFeaturesLibConstructor ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + mSmmCpuFeaturesSmmRelocated =3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobG= uid) !=3D NULL); + // // No need to program SMRRs on our virtual platform. // return EFI_SUCCESS; } @@ -83,20 +97,25 @@ SmmCpuFeaturesInitializeProcessor ( ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuState; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( - SMM_DEFAULT_SMBASE + - SMRAM_SAVE_STATE_MAP_OFF= SET - ); - if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; - } else { - CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmCpuFeaturesSmmRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( + SMM_DEFAULT_SMBASE + + SMRAM_SAVE_STATE_MAP_O= FFSET + ); + if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } else { + CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } } =20 // // No need to program SMRRs on our virtual platform. // diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 8a426a4c10..6a281518f5 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -33,10 +33,14 @@ MemoryAllocationLib PcdLib SafeIntLib SmmServicesTableLib UefiBootServicesTableLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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