From nobody Mon Feb 9 20:32:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98240+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98240+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1673338892; cv=none; d=zohomail.com; s=zohoarc; b=jyVSbPhBQTb4sK+T2Suu6dGJyoBNwHXxKgwaZijAXTvOMD06Vezochngt++46kkviaA0Lj5ZWTp7FdDY4wTVC7wXSZhn+CtvL6Q0kLhwR1arhbZ+3llkAEDgc1th+J9lB4buu2arNcqlju2cmciuAfF7V9pCGEFx1d7iiB8MMBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673338892; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8z/OJf2qPQAbyUvL6+QB5Dmcd4qb4khqQPI6bM/Ah78=; b=JagYRT1ZrkP/Qsk6p8ezr8wdbEXe4Dh0ZB9UHiEUjlVPDxZEFpVjipBD2Xd9w5IC3z5LWvzOM0ggDudldqgtevMYvklPd4ZhQwwqY+H17LSiXtt9JwCe0PpneLylYH2pNlUPiM9rjBxEGQJKvXjr8nS3nOGNvciS/7NdhuIW1VI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98240+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167333889220759.48599381309873; Tue, 10 Jan 2023 00:21:32 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id tOglYY1788612x2khaemLijV; Tue, 10 Jan 2023 00:21:31 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.98860.1673338891370149389 for ; Tue, 10 Jan 2023 00:21:31 -0800 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-635-CvCWsQY_PyGo0cLD32j23w-1; Tue, 10 Jan 2023 03:21:27 -0500 X-MC-Unique: CvCWsQY_PyGo0cLD32j23w-1 X-Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2837985CCE2; Tue, 10 Jan 2023 08:21:27 +0000 (UTC) X-Received: from sirius.home.kraxel.org (unknown [10.39.192.238]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AEBE9492C14; Tue, 10 Jan 2023 08:21:26 +0000 (UTC) X-Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id E45181800619; Tue, 10 Jan 2023 09:21:23 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Pawel Polawski , Jiewen Yao , Oliver Steffen , Jordan Justen , =?UTF-8?q?L=C3=A1szl=C3=B3=20=C3=89rsek?= , Ard Biesheuvel , Gerd Hoffmann Subject: [edk2-devel] [PATCH v2 2/4] OvmfPkg/PlatformInitLib: Add PlatformGetLowMemoryCB Date: Tue, 10 Jan 2023 09:21:21 +0100 Message-Id: <20230110082123.159521-3-kraxel@redhat.com> In-Reply-To: <20230110082123.159521-1-kraxel@redhat.com> References: <20230110082123.159521-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com X-Gm-Message-State: ooOJpXr3dotwjsbWK5bO5j6tx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673338891; bh=ICMiaOeQYLfaDJCHWm9h7BtVK8qrHf57OW1B0+NjqPE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=s1JBVM73vjzzMIzagtzckYClLvfKps/Q72O+UckMUgy5OOhwNgdb86mTW/OBYML3F2q fAIInG6MhwJgGr68BGQeaYdjihh2MUFlBpBclY0VrRAivgvlcAKIqzBpnVFxDt6L+hvq/ xPITS4/v6KeiS4WXPB/ckwaU8/oj2QE+cg4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673338894080100009 Content-Type: text/plain; charset="utf-8"; x-default="true" Add PlatformGetLowMemoryCB() callback function for use with PlatformScanE820(). It stores the low memory size in PlatformInfoHob->LowMemory. This replaces calls to PlatformScanOrAdd64BitE820Ram() with non-NULL LowMemory. Also change PlatformGetSystemMemorySizeBelow4gb() to likewise set PlatformInfoHob->LowMemory instead of returning the value. Update all Callers to the new convention. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Include/Library/PlatformInitLib.h | 3 +- OvmfPkg/Library/PeilessStartupLib/Hob.c | 3 +- .../PeilessStartupLib/PeilessStartup.c | 7 +- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 69 +++++++++++++------ OvmfPkg/Library/PlatformInitLib/Platform.c | 7 +- OvmfPkg/PlatformPei/MemDetect.c | 3 +- 6 files changed, 59 insertions(+), 33 deletions(-) diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index bf6f90a5761c..051b31191194 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -26,6 +26,7 @@ typedef struct { BOOLEAN Q35SmramAtDefaultSmbase; UINT16 Q35TsegMbytes; =20 + UINT32 LowMemory; UINT64 FirstNonAddress; UINT8 PhysMemAddressWidth; UINT32 Uc32Base; @@ -144,7 +145,7 @@ PlatformQemuUc32BaseInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 -UINT32 +VOID EFIAPI PlatformGetSystemMemorySizeBelow4gb ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob diff --git a/OvmfPkg/Library/PeilessStartupLib/Hob.c b/OvmfPkg/Library/Peil= essStartupLib/Hob.c index 630ce445ebec..784a8ba194de 100644 --- a/OvmfPkg/Library/PeilessStartupLib/Hob.c +++ b/OvmfPkg/Library/PeilessStartupLib/Hob.c @@ -41,8 +41,9 @@ ConstructSecHobList ( EFI_HOB_PLATFORM_INFO PlatformInfoHob; =20 ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob)); + PlatformGetSystemMemorySizeBelow4gb (&PlatformInfoHob); PlatformInfoHob.HostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID); - LowMemorySize =3D PlatformGetSystemMemorySizeBelow4gb = (&PlatformInfoHob); + LowMemorySize =3D PlatformInfoHob.LowMemory; ASSERT (LowMemorySize !=3D 0); LowMemoryStart =3D FixedPcdGet32 (PcdOvmfDxeMemFvBase) + FixedPcdGet32 (= PcdOvmfDxeMemFvSize); LowMemorySize -=3D LowMemoryStart; diff --git a/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c b/OvmfPkg/L= ibrary/PeilessStartupLib/PeilessStartup.c index 380e71597206..928120d183ba 100644 --- a/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c +++ b/OvmfPkg/Library/PeilessStartupLib/PeilessStartup.c @@ -41,8 +41,7 @@ InitializePlatform ( EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT32 LowerMemorySize; - VOID *VariableStore; + VOID *VariableStore; =20 DEBUG ((DEBUG_INFO, "InitializePlatform in Pei-less boot\n")); PlatformDebugDumpCmos (); @@ -70,14 +69,14 @@ InitializePlatform ( PlatformInfoHob->PcdCpuBootLogicalProcessorNumber )); =20 - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob= ); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); PlatformQemuUc32BaseInitialization (PlatformInfoHob); DEBUG (( DEBUG_INFO, "Uc32Base =3D 0x%x, Uc32Size =3D 0x%x, LowerMemorySize =3D 0x%x\n", PlatformInfoHob->Uc32Base, PlatformInfoHob->Uc32Size, - LowerMemorySize + PlatformInfoHob->LowMemory )); =20 VariableStore =3D PlatformReserveEmuVar= iableNvStore (); diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/= PlatformInitLib/MemDetect.c index a2a4dc043f2e..63329c4e796a 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -51,18 +51,16 @@ PlatformQemuUc32BaseInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT32 LowerMemorySize; - if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { return; } =20 if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoH= ob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); - ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >=3D LowerMemorySize); + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >=3D PlatformInfoHob->LowM= emory); =20 - if (LowerMemorySize <=3D BASE_2GB) { + if (PlatformInfoHob->LowMemory <=3D BASE_2GB) { // Newer qemu with gigabyte aligned memory, // 32-bit pci mmio window is 2G -> 4G then. PlatformInfoHob->Uc32Base =3D BASE_2GB; @@ -92,8 +90,8 @@ PlatformQemuUc32BaseInitialization ( // variable MTRR suffices by truncating the size to a whole power of two, // while keeping the end affixed to 4GB. This will round the base up. // - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (Platf= ormInfoHob); - PlatformInfoHob->Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - Lower= MemorySize)); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformInfoHob->Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - Platf= ormInfoHob->LowMemory)); PlatformInfoHob->Uc32Base =3D (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32S= ize); // // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. @@ -101,13 +99,13 @@ PlatformQemuUc32BaseInitialization ( // ASSERT (PlatformInfoHob->Uc32Base >=3D BASE_2GB); =20 - if (PlatformInfoHob->Uc32Base !=3D LowerMemorySize) { + if (PlatformInfoHob->Uc32Base !=3D PlatformInfoHob->LowMemory) { DEBUG (( DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for " "an UC32 size of 0x%x\n", __FUNCTION__, - LowerMemorySize, + PlatformInfoHob->LowMemory, PlatformInfoHob->Uc32Base, PlatformInfoHob->Uc32Size )); @@ -279,6 +277,33 @@ PlatformGetFirstNonAddressCB ( } } =20 +/** + Store the low (below 4G) memory size in + PlatformInfoHob->LowMemory +**/ +VOID +PlatformGetLowMemoryCB ( + IN EFI_E820_ENTRY64 *E820Entry, + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 Candidate; + + if (E820Entry->Type !=3D EfiAcpiAddressRangeMemory) { + return; + } + + Candidate =3D E820Entry->BaseAddr + E820Entry->Length; + if (Candidate >=3D BASE_4GB) { + return; + } + + if (PlatformInfoHob->LowMemory < Candidate) { + DEBUG ((DEBUG_INFO, "%a: LowMemory=3D0x%Lx\n", __FUNCTION__, Candidate= )); + PlatformInfoHob->LowMemory =3D Candidate; + } +} + /** Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map, call the passed callback for each entry. @@ -395,14 +420,13 @@ GetHighestSystemMemoryAddressFromPvhMemmap ( return HighestAddress; } =20 -UINT32 +VOID EFIAPI PlatformGetSystemMemorySizeBelow4gb ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { EFI_STATUS Status; - UINT64 LowerMemorySize =3D 0; UINT8 Cmos0x34; UINT8 Cmos0x35; =20 @@ -410,12 +434,13 @@ PlatformGetSystemMemorySizeBelow4gb ( (CcProbe () !=3D CcGuestTypeIntelTdx)) { // Get the information from PVH memmap - return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); + PlatformInfoHob->LowMemory =3D GetHighestSystemMemoryAddressFromPvhMem= map (TRUE); + return; } =20 - Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); - if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { - return (UINT32)LowerMemorySize; + Status =3D PlatformScanE820 (PlatformGetLowMemoryCB, PlatformInfoHob); + if ((Status =3D=3D EFI_SUCCESS) && (PlatformInfoHob->LowMemory > 0)) { + return; } =20 // @@ -430,7 +455,7 @@ PlatformGetSystemMemorySizeBelow4gb ( Cmos0x34 =3D (UINT8)PlatformCmosRead8 (0x34); Cmos0x35 =3D (UINT8)PlatformCmosRead8 (0x35); =20 - return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); + PlatformInfoHob->LowMemory =3D ((((UINTN)Cmos0x35 << 8) + Cmos0x34) << 1= 6) + SIZE_16MB; } =20 STATIC @@ -965,7 +990,6 @@ PlatformQemuInitializeRam ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT64 LowerMemorySize; UINT64 UpperMemorySize; MTRR_SETTINGS MtrrSettings; EFI_STATUS Status; @@ -975,7 +999,7 @@ PlatformQemuInitializeRam ( // // Determine total memory size available // - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob= ); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); =20 if (PlatformInfoHob->BootMode =3D=3D BOOT_ON_S3_RESUME) { // @@ -1009,14 +1033,14 @@ PlatformQemuInitializeRam ( UINT32 TsegSize; =20 TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; - PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddMemoryRangeHob (BASE_1MB, PlatformInfoHob->LowMemory - Ts= egSize); PlatformAddReservedMemoryBaseSizeHob ( - LowerMemorySize - TsegSize, + PlatformInfoHob->LowMemory - TsegSize, TsegSize, TRUE ); } else { - PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); + PlatformAddMemoryRangeHob (BASE_1MB, PlatformInfoHob->LowMemory); } =20 // @@ -1194,9 +1218,10 @@ PlatformQemuInitializeRamForS3 ( // Make sure the TSEG area that we reported as a reserved memory res= ource // cannot be used for reserved memory allocations. // + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( - PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, + PlatformInfoHob->LowMemory - TsegSize, TsegSize, EfiReservedMemoryType ); diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Platform.c index 3e13c5d4b34f..9ab0342fd8c0 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -128,7 +128,6 @@ PlatformMemMapInitialization ( { UINT64 PciIoBase; UINT64 PciIoSize; - UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; @@ -150,7 +149,7 @@ PlatformMemMapInitialization ( return; } =20 - TopOfLowRam =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); PciExBarBase =3D 0; if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // @@ -158,11 +157,11 @@ PlatformMemMapInitialization ( // the base of the 32-bit PCI host aperture. // PciExBarBase =3D PcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <=3D PciExBarBase); + ASSERT (PlatformInfoHob->LowMemory <=3D PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); } else { - ASSERT (TopOfLowRam <=3D PlatformInfoHob->Uc32Base); + ASSERT (PlatformInfoHob->LowMemory <=3D PlatformInfoHob->Uc32Base); PciBase =3D PlatformInfoHob->Uc32Base; } =20 diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 3d8375320dcb..41d186986ba8 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -271,7 +271,8 @@ PublishPeiMemory ( UINT32 S3AcpiReservedMemoryBase; UINT32 S3AcpiReservedMemorySize; =20 - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob= ); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + LowerMemorySize =3D PlatformInfoHob->LowMemory; if (PlatformInfoHob->SmmSmramRequire) { // // TSEG is chipped from the end of low RAM --=20 2.39.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98240): https://edk2.groups.io/g/devel/message/98240 Mute This Topic: https://groups.io/mt/96173191/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-