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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@quicinc.com X-Gm-Message-State: qDfAJXKBNY1qmS9S4t3n81OSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673001613; bh=K2DViRgjsU2Cq4e5qVr5p6ezBhpZa8oUmBYtoz7IuKc=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=opVAompMzoojm8dIn44gxNnUepdV2XefOw9zpbk1UX9ft7UzL9e4+3ZJdbPa9/Fxzpx csP3txxTqXc+hj8cfqe7DL5lWjQYnytRCl2gxwze5U/+H2M21JBXBaKgVZXlbJvsd1Fcz 5LeGE7b/t6HpKLh0gdA6sv1QQAb3YUZaSg8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673001615682100023 Content-Type: text/plain; charset="utf-8" Signed-off-by: Rebecca Cran --- ArmPkg/Include/Library/ArmLib.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 6566deebdde2..fa605f128bfd 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -108,14 +108,16 @@ typedef enum { =20 #define ARM_CORE_MASK ARM_CORE_AFF0 #define ARM_CLUSTER_MASK ARM_CORE_AFF1 -#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) -#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) -#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) -#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0) -#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8) -#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16) -#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32) +#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) +#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) +#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) +#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0) +#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8) +#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16) +#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32) +#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) +#define MPIDR_MT_BIT BIT24 =20 /** Reads the CCSIDR register for the specified cache. =20 --=20 2.30.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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