From nobody Mon Feb 9 13:39:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97622+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97622+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1671525786; cv=none; d=zohomail.com; s=zohoarc; b=FbCAXlQCnQ9flxKbDr3gNh73F/QtbT3iK9n+vY/6kmkrATAEmiBPlB6yDpqN1nEkEk+MTFYXAMY1E1FzLkqtyOfpXscqLiuzjpCedzfp9eiX6DYQSW5u+RPjR50ltfFCsjwmT+WCj4wgc6QSyihOy1eCx51MfPYnB2JhvU2zfFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671525786; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1M/kpxqRQZOZ9nSsj20zmnFEvb+f0FlPTSyJQMqOXnU=; b=TFGq4BMG/J3BP7o2UdYRooWCbujvWtbJW0Hj1ndc76kO5rd5p2vxtrMeEGoFyE3Mt+OIEWZ/BJNbbRvkKqQBDAbVe+io0j/CZw6oHpoDZFp1Y4FrJzo1cwlaE2eRs2KPydyyAN3y1ju/0UgFC9QcfMCO7mQ/qTysCQ3WaqATwqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97622+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671525786870263.7653006292958; Tue, 20 Dec 2022 00:43:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id mQ8aYY1788612xwvrA38gzTm; Tue, 20 Dec 2022 00:43:06 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.46058.1671525777169185136 for ; Tue, 20 Dec 2022 00:43:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="383908291" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="383908291" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2022 00:43:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="628644656" X-IronPort-AV: E=Sophos;i="5.96,259,1665471600"; d="scan'208";a="628644656" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.29.12]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2022 00:43:02 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min M Xu , Erdem Aktas , Gerd Hoffmann , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V2 4/6] OvmfPkg/Sec: Move TDX APs related nasm code to IntelTdxAPs.nasm Date: Tue, 20 Dec 2022 16:42:38 +0800 Message-Id: <20221220084240.1922-5-min.m.xu@intel.com> In-Reply-To: <20221220084240.1922-1-min.m.xu@intel.com> References: <20221220084240.1922-1-min.m.xu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: EJXF8lxmzLwrBxeBBRSoGgsPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671525786; bh=iMHBsX5521gZslHYo+5wK1t9fhTXCTkYm2qCquPOmPk=; h=Cc:Date:From:Reply-To:Subject:To; b=A2JNu/OF9qcitKLeOSGoM4gTiu/vdA3WVDKnHE8004urBmG2wKjtlueHUOS1rccryKw xHYVG0uWjOfjeVIQuYS0uXmQRbVGiJdjoTItPx+bt2SiWstdAu+L1XtnH2Tp94ZxTvzgP yjTaQw+8NuD+GFHgRLA8B7X05lWQJag3xKs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671525788640100001 Content-Type: text/plain; charset="utf-8" From: Min M Xu BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4172 This patch moves the TDX APs nasm code from SecEntry.nasm to IntelTdxAPs.nasm. IntelTdxX64 and OvmfPkgX64 use the same nasm so that it can be easier to be managed. In the following patch there will be AcceptMemory related changes in IntelTdxAPs.nasm. Cc: Erdem Aktas Cc: Gerd Hoffmann Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm | 58 +++++++++++++++++++++++ OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm | 58 ++--------------------- OvmfPkg/Sec/X64/SecEntry.nasm | 58 ++--------------------- 3 files changed, 68 insertions(+), 106 deletions(-) create mode 100644 OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm diff --git a/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm b/OvmfPkg/IntelTdx/S= ec/X64/IntelTdxAPs.nasm new file mode 100644 index 000000000000..034ac0ee9421 --- /dev/null +++ b/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm @@ -0,0 +1,58 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Intel TDX APs +; +; Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%include "TdxCommondefs.inc" + + ; + ; Note: BSP never gets here. APs will be unblocked by DXE + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; +ParkAp: + +do_wait_loop: + ; + ; register itself in [rsp + CpuArrivalOffset] + ; + mov rax, 1 + lock xadd dword [rsp + CpuArrivalOffset], eax + inc eax + +.check_arrival_cnt: + cmp eax, r8d + je .check_command + mov eax, dword[rsp + CpuArrivalOffset] + jmp .check_arrival_cnt + +.check_command: + mov eax, dword[rsp + CommandOffset] + cmp eax, MpProtectedModeWakeupCommandNoop + je .check_command + + cmp eax, MpProtectedModeWakeupCommandWakeup + je .do_wakeup + + ; Don't support this command, so ignore + jmp .check_command + +.do_wakeup: + ; + ; BSP sets these variables before unblocking APs + ; RAX: WakeupVectorOffset + ; RBX: Relocated mailbox address + ; RBP: vCpuId + ; + mov rax, 0 + mov eax, dword[rsp + WakeupVectorOffset] + mov rbx, [rsp + WakeupArgsRelocatedMailBox] + nop + jmp rax + jmp $ diff --git a/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm b/OvmfPkg/IntelTdx/Sec/= X64/SecEntry.nasm index 4528fec309a0..5a38c4213916 100644 --- a/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm @@ -10,7 +10,6 @@ ;-------------------------------------------------------------------------= ----- =20 #include -%include "TdxCommondefs.inc" =20 DEFAULT REL SECTION .text @@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint): cmp byte[eax], VM_GUEST_TYPE_TDX jne InitStack =20 + %define TDCALL_TDINFO 1 mov rax, TDCALL_TDINFO tdcall =20 @@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint): mov rax, r9 and rax, 0xffff test rax, rax - jne ParkAp + jz InitStack + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + jmp ParkAp =20 InitStack: =20 @@ -98,54 +100,4 @@ InitStack: sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) =20 - ; - ; Note: BSP never gets here. APs will be unblocked by DXE - ; - ; R8 [31:0] NUM_VCPUS - ; [63:32] MAX_VCPUS - ; R9 [31:0] VCPU_INDEX - ; -ParkAp: - - mov rbp, r9 - -.do_wait_loop: - mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) - - ; - ; register itself in [rsp + CpuArrivalOffset] - ; - mov rax, 1 - lock xadd dword [rsp + CpuArrivalOffset], eax - inc eax - -.check_arrival_cnt: - cmp eax, r8d - je .check_command - mov eax, dword[rsp + CpuArrivalOffset] - jmp .check_arrival_cnt - -.check_command: - mov eax, dword[rsp + CommandOffset] - cmp eax, MpProtectedModeWakeupCommandNoop - je .check_command - - cmp eax, MpProtectedModeWakeupCommandWakeup - je .do_wakeup - - ; Don't support this command, so ignore - jmp .check_command - -.do_wakeup: - ; - ; BSP sets these variables before unblocking APs - ; RAX: WakeupVectorOffset - ; RBX: Relocated mailbox address - ; RBP: vCpuId - ; - mov rax, 0 - mov eax, dword[rsp + WakeupVectorOffset] - mov rbx, [rsp + WakeupArgsRelocatedMailBox] - nop - jmp rax - jmp $ +%include "IntelTdxAPs.nasm" diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index 4528fec309a0..0f82051720da 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -10,7 +10,6 @@ ;-------------------------------------------------------------------------= ----- =20 #include -%include "TdxCommondefs.inc" =20 DEFAULT REL SECTION .text @@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint): cmp byte[eax], VM_GUEST_TYPE_TDX jne InitStack =20 + %define TDCALL_TDINFO 1 mov rax, TDCALL_TDINFO tdcall =20 @@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint): mov rax, r9 and rax, 0xffff test rax, rax - jne ParkAp + jz InitStack + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + jmp ParkAp =20 InitStack: =20 @@ -98,54 +100,4 @@ InitStack: sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) =20 - ; - ; Note: BSP never gets here. APs will be unblocked by DXE - ; - ; R8 [31:0] NUM_VCPUS - ; [63:32] MAX_VCPUS - ; R9 [31:0] VCPU_INDEX - ; -ParkAp: - - mov rbp, r9 - -.do_wait_loop: - mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) - - ; - ; register itself in [rsp + CpuArrivalOffset] - ; - mov rax, 1 - lock xadd dword [rsp + CpuArrivalOffset], eax - inc eax - -.check_arrival_cnt: - cmp eax, r8d - je .check_command - mov eax, dword[rsp + CpuArrivalOffset] - jmp .check_arrival_cnt - -.check_command: - mov eax, dword[rsp + CommandOffset] - cmp eax, MpProtectedModeWakeupCommandNoop - je .check_command - - cmp eax, MpProtectedModeWakeupCommandWakeup - je .do_wakeup - - ; Don't support this command, so ignore - jmp .check_command - -.do_wakeup: - ; - ; BSP sets these variables before unblocking APs - ; RAX: WakeupVectorOffset - ; RBX: Relocated mailbox address - ; RBP: vCpuId - ; - mov rax, 0 - mov eax, dword[rsp + WakeupVectorOffset] - mov rbx, [rsp + WakeupArgsRelocatedMailBox] - nop - jmp rax - jmp $ +%include "../../IntelTdx/Sec/X64/IntelTdxAPs.nasm" --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97622): https://edk2.groups.io/g/devel/message/97622 Mute This Topic: https://groups.io/mt/95782430/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-