From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97441+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97441+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671108999; cv=none; d=zohomail.com; s=zohoarc; b=EqlG97UnpVGPeeaty+AGs/O5t1iYQZ63rVciRZGNnY7ppT1xClLD/jah/Evk8j46t1noRyUIDzMh+hjrkOyT8twHhf4ppsFHFGC8CM2P8PHzd3r2jfqP0TORlmNH7/DGFo6aM+bcrqtvhIp2oCCQgwXgQSzwkwkywBGM5CR0ZHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671108999; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=neZq3iKQMXznvNyRfkvGid6azc5AJhtj6jDHALyNSFY=; b=N5ZcMZeh4xUo2p5w3cMg4DtjCmA66hObKG+tPO8+vr4wo3hdUMWWBS46eG4xFqlrLYCoY7B54CitOrW02z/tAh44R7JLQT/LGqozWMucQPv24XfWZ4tUCeOgqs4HvLAFgZRQWztFlnwihh0rqbiU6LN4si5QAtYPev7YeEkStIs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97441+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671108999860321.1910272063053; Thu, 15 Dec 2022 04:56:39 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id PeAAYY1788612xoCCf650hE1; Thu, 15 Dec 2022 04:56:39 -0800 X-Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web11.132914.1671108999018885374 for ; Thu, 15 Dec 2022 04:56:39 -0800 X-Received: by mail-pg1-f169.google.com with SMTP id q71so4090847pgq.8 for ; Thu, 15 Dec 2022 04:56:38 -0800 (PST) X-Gm-Message-State: 5UAan9qpzv3ULaX5XmaB5baOx1787277AA= X-Google-Smtp-Source: AA0mqf6g5RHdR6iOMB5x5h09Ekg7Ljdp5Rotk3FB5QNuS7IRxu2TRMlINlte3tjOpsoguUvHNxNo6g== X-Received: by 2002:a05:6a00:21c1:b0:572:5a7f:a02d with SMTP id t1-20020a056a0021c100b005725a7fa02dmr34559669pfj.6.1671108998210; Thu, 15 Dec 2022 04:56:38 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:37 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 01/23] MdePkg/Register: Add register definition header files for RISC-V Date: Thu, 15 Dec 2022 18:26:04 +0530 Message-Id: <20221215125626.545372-2-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671108999; bh=Za+a3LkDbur6mqxSLgzgoQqvUTZVfP6c0GQsQbji1Tw=; h=Cc:Date:From:Reply-To:Subject:To; b=LfUsrMmJrOaAPQp26pdprTJJ32CzX1bCR39Fo4aJd6x/8OO0lnkwljdzIRSvtOpL4Gj biRSEZ3gX4UZskiCyriynrovYPNEYjpA/YSSQSRLF7U2Q1DHyL0qnnzx0sfmaBdoNllHb 9ndY1CEGQqwz/6ZYB7aBbCCxJAa+xeNzb/k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109001325100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 ++++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ 2 files changed, 144 insertions(+) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..5c2989b797bf --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,119 @@ +/** @file + RISC-V CSR encodings + + Copyright (c) 2019, Western Digital Corporation or its affiliates. All r= ights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_ENCODING_H_ +#define RISCV_ENCODING_H_ + +#define MSTATUS_SIE 0x00000002UL +#define MSTATUS_MIE 0x00000008UL +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE 0x00000040UL +#define MSTATUS_MPIE 0x00000080UL +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (1UL << IRQ_S_SOFT) +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) +#define MIP_MSIP (1UL << IRQ_M_SOFT) +#define MIP_STIP (1UL << IRQ_S_TIMER) +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) +#define MIP_MTIP (1UL << IRQ_M_TIMER) +#define MIP_SEIP (1UL << IRQ_S_EXT) +#define MIP_VSEIP (1UL << IRQ_VS_EXT) +#define MIP_MEIP (1UL << IRQ_M_EXT) +#define MIP_SGEIP (1UL << IRQ_S_GEXT) +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0UL +#define PRV_S 1UL +#define PRV_M 3UL + +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL + +#define SATP_MODE_OFF 0UL +#define SATP_MODE_SV32 1UL +#define SATP_MODE_SV39 8UL +#define SATP_MODE_SV48 9UL +#define SATP_MODE_SV57 10UL +#define SATP_MODE_SV64 11UL + +#define SATP_MODE SATP64_MODE + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* Trap/Exception Causes */ +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..ee5c2ba60377 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,25 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_IMPL_H_ +#define RISCV_IMPL_H_ + +#include + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97441): https://edk2.groups.io/g/devel/message/97441 Mute This Topic: https://groups.io/mt/95687618/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97442+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97442+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109002; cv=none; d=zohomail.com; s=zohoarc; b=kLP2Hq4Iu7myYQbeH26MpZxHczpCqp6JWpyw/2YG44RIuPV7BFf5FAo5ULd7sli4XBLR0/LJJdRgBMEecSCqWwUCl1qD4gVFxS5SaOsYpQNaCRlZ6VyuVxsAn4J6R8g/mKbQtOEUrL5x2dSemSyUIlxL9OuJ5QyG2JQTpwcAD2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109002; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4MKWRb9ONJAqsit4nx04ECeGBVK1l0FoR25arkj3PAU=; b=jSLnHPSmbA4mOOMY+ZfXVlj1O4fEkffyPGPF2P/iuLhr3GtQZylIMWhYQoeshKZVE6Tg98okRaslXclz1ZwhRhbPX+K9IY4RsMlJVL8i+v+hLqglPn4exopygOar/Vg2QJbCktC+hJm0imKXxH/xoVyxoprGBt7vTo3Au+WjAiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97442+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109002571435.8881836004957; Thu, 15 Dec 2022 04:56:42 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id OjiZYY1788612x7LR4U3fOtV; Thu, 15 Dec 2022 04:56:42 -0800 X-Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mx.groups.io with SMTP id smtpd.web10.132058.1671109001549411686 for ; Thu, 15 Dec 2022 04:56:41 -0800 X-Received: by mail-pj1-f41.google.com with SMTP id fa4-20020a17090af0c400b002198d1328a0so6341747pjb.0 for ; Thu, 15 Dec 2022 04:56:41 -0800 (PST) X-Gm-Message-State: KGXkAwsd8QScSW6en6GzzW87x1787277AA= X-Google-Smtp-Source: AA0mqf674t4/pMqPIXUsaXbfVOCWyLwRdh/hJl+V7xe131W3dHmsWnrT9eXFbCmOgYP8DiomVAGxIg== X-Received: by 2002:a05:6a20:9c89:b0:9d:efbf:7876 with SMTP id mj9-20020a056a209c8900b0009defbf7876mr34122770pzb.43.1671109000750; Thu, 15 Dec 2022 04:56:40 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:40 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang , Heinrich Schuchardt Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 02/23] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Date: Thu, 15 Dec 2022 18:26:05 +0530 Message-Id: <20221215125626.545372-3-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109002; bh=eE5bZD8qHVWcPEPxCiHxvvTf+EuUolgL3PV0enPn83o=; h=Cc:Date:From:Reply-To:Subject:To; b=dLK6G7bZPW3Cgk//JuzjD9GHTmrfIRB61W9YJVmuIzB4Nw6BKbHfKzhoeSJKmieOChA WeyoMaZvQ4SCkJjwhE7Mj/j/spIG23x3638zT94YQs3egj8SY66RJ2LL0+vbS6jpIGmq9 E7LmbZ+fXOXGrgl34rV1UwLQ9rroWU3OmTA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109003369100010 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Heinrich Schuchardt Reviewed-by: Andrei Warkentin --- MdePkg/MdePkg.dec | 5 +++ MdePkg/Include/Protocol/RiscVBootProtocol.h | 34 ++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index e49b2d5b5f28..4f30de588a46 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -1926,6 +1926,11 @@ [Protocols] # ## Include/Protocol/ShellDynamicCommand.h gEfiShellDynamicCommandProtocolGuid =3D { 0x3c7200e9, 0x005f, 0x4ea4, {= 0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }} + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid =3D { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x9= 5, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }} =20 # # [Error.gEfiMdePkgTokenSpaceGuid] diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h b/MdePkg/Include/P= rotocol/RiscVBootProtocol.h new file mode 100644 index 000000000000..ed223b852d34 --- /dev/null +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,34 @@ +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + @par Revision Reference: + The protocol specification can be found at + https://github.com/riscv-non-isa/riscv-uefi + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_BOOT_PROTOCOL_H_ +#define RISCV_BOOT_PROTOCOL_H_ + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 +#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID)( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97442): https://edk2.groups.io/g/devel/message/97442 Mute This Topic: https://groups.io/mt/95687620/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97443+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97443+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109004; cv=none; d=zohomail.com; s=zohoarc; b=QZe7U2PkTdZ8pfsy+Pk+u8kSpUx2nZVO0sYkIy6LLfncnPBCFrTWfmTvUobx6gjGd57cPPn7b5l4kK5H9u39pTQkc0OKgg31yTXScRA0lf1X3/nAAr5dzrT7pHtRq9FIljD9IX3SGOCZ50prp9bysbXS31KLyJeU8szRUiMJwaw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KPNUZnIuNh/6lwS573cdE8RmECG93K+H1hlS1T/ZTJw=; b=aLk+0GIv4ROK98n8/bU/JcdnjN3o5wmxBMcy6k6+5vwmZFpfHd2M1ceYlRum448nJNkUkUV9un41XNCkhlIc5VHE63BDCnirKVFpIihk3zaqFDLvBihGlYedaqAYIR2Vid/5DbZjLlsGLxJ8EvBzaTyfgjFxYkY6bUj7Zi8+aOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97443+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109004807206.1953599751423; Thu, 15 Dec 2022 04:56:44 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bbY7YY1788612xqByboLnozy; Thu, 15 Dec 2022 04:56:44 -0800 X-Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web11.132916.1671109003913278056 for ; Thu, 15 Dec 2022 04:56:43 -0800 X-Received: by mail-pf1-f172.google.com with SMTP id 65so6625072pfx.9 for ; Thu, 15 Dec 2022 04:56:43 -0800 (PST) X-Gm-Message-State: yksPffOeqxikhHUoogMbBHiMx1787277AA= X-Google-Smtp-Source: AA0mqf4MC2gLmSVb4RRdFzlfkEOrQlq8TFv2JoPe94nUz4+LbQM8QvYBsRi7K0uqvR7an4QHYB9SQQ== X-Received: by 2002:a62:cd0c:0:b0:577:2a9:96ef with SMTP id o12-20020a62cd0c000000b0057702a996efmr31062604pfg.28.1671109003105; Thu, 15 Dec 2022 04:56:43 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:42 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 03/23] MdePkg/BaseLib: RISC-V: Add few more helper functions Date: Thu, 15 Dec 2022 18:26:06 +0530 Message-Id: <20221215125626.545372-4-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109004; bh=ZVsrpQq9zlFDeSJfUhLVDOYwft5OASdefUOnCU/Bbyc=; h=Cc:Date:From:Reply-To:Subject:To; b=aMzEPhBzQibxrh1MBJV/kuq1Wl/ExRCNlXCjAG1ZUTlO1+uSm0gy66XtdyiGnha0Cr6 QUuPblQZ0HkupPzsoGpACPn5Vcn2Kl29fFmO9yquewUuPu7ImcpMoOnGOEHVGiLBUeoql lqD82IAjlgCYU8ZXrJlbqsUwCS87yfOJRmw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109005397100014 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- MdePkg/Library/BaseLib/BaseLib.inf | 3 ++ MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++ MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++-- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 +++++++++ 6 files changed, 179 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 9ed46a584a14..3a48492b1a01 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,9 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuScratch.S | GCC + RiscV64/ReadTimer.S | GCC + RiscV64/RiscVMmu.S | GCC =20 [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index f3f59f21c2ea..b4f4e45a1486 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -151,6 +151,56 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID + RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID + RiscVSetSupervisorStvec ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +UINT64 +RiscVGetSupervisorTrapCause ( + VOID + ); + +VOID + RiscVSetSupervisorAddressTranslationRegister ( + UINT64 + ); + +UINT64 +RiscVReadTimer ( + VOID + ); + +VOID +RiscVEnableTimerInterrupt ( + VOID + ); + +VOID +RiscVDisableTimerInterrupt ( + VOID + ); + +VOID +RiscVClearPendingTimerInterrupt ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/B= aseLib/RiscV64/CpuScratch.S new file mode 100644 index 000000000000..5492a500eb5e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrw CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/Ba= seLib/RiscV64/ReadTimer.S new file mode 100644 index 000000000000..39a06efa51ef --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// Read CPU timer +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Read TIME CSR. +// @retval a0 : 64-bit timer. +// +ASM_FUNC (RiscVReadTimer) + csrr a0, CSR_TIME + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S index 87b3468fc7fd..6a1b90a7e45c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -8,13 +8,13 @@ // //------------------------------------------------------------------------= ------ =20 +#include + ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) =20 -#define SSTATUS_SIE 0x00000002 -#define CSR_SSTATUS 0x100 - #define SSTATUS_SPP_BIT_POSITION 8 +#define SSTATUS_SPP_BIT_POSITION 8 =20 // // This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap: ret =20 // +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, CSR_STVEC, a0 + ret + +// +// Get Supervisor mode trap vector. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, CSR_STVEC + ret + +// +// Get Supervisor trap cause CSR. +// +ASM_FUNC (RiscVGetSupervisorTrapCause) + csrrs a0, CSR_SCAUSE, 0 + ret +// // This routine returns supervisor mode interrupt // status. // -ASM_PFX(RiscVGetSupervisorModeInterrupts): +ASM_FUNC (RiscVGetSupervisorModeInterrupts) csrr a0, CSR_SSTATUS andi a0, a0, SSTATUS_SIE ret =20 +// +// This routine disables supervisor mode timer interrupt +// +ASM_FUNC (RiscVDisableTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIE, a0 + ret + +// +// This routine enables supervisor mode timer interrupt +// +ASM_FUNC (RiscVEnableTimerInterrupt) + li a0, SIP_STIP + csrs CSR_SIE, a0 + ret + +// +// This routine clears pending supervisor mode timer interrupt +// +ASM_FUNC (RiscVClearPendingTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIP, a0 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/Bas= eLib/RiscV64/RiscVMmu.S new file mode 100644 index 000000000000..ac8f92f38aed --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) + csrw CSR_SATP, a0 + ret --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97443): https://edk2.groups.io/g/devel/message/97443 Mute This Topic: https://groups.io/mt/95687622/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97444+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97444+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109007; cv=none; d=zohomail.com; s=zohoarc; b=CcLxQ28ICFIWTxVKTjF/Sx/g8ClWRJdKQDLSECeZea2CWoV7/iYJ4ePzDxApfUvT69oFq94JHD3uI7y0MXN1b5kX42LGoEKydS6/yew2egchwg+X9xzItBNF9V5b73m7Nt0tX21RTHMluHVwLfuD7i6uvNc3IVM1RhMdhpa27is= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HRmyRw4sIg7kvJDgseslL6VlUlHOtYMuQQs6mCUv3kM=; b=UyIZOBHIFh+lCDXlOeDtXrH4ct2VlPfQCEbKsMvHZ+3gHiKC94FEoPo0mkuFykd1K2d/jkbqXQB+Z9uxNapY/nvATErpOoCBUcHT5DHZIQ652h9MqHkFqzYHT2dWObiVltmm7/Kr1yywPJY7Hm7DKzxbgI/se7ZGBFomPk1ero4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97444+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109007685571.4413356604778; Thu, 15 Dec 2022 04:56:47 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id vBLpYY1788612x904N0vdtGo; Thu, 15 Dec 2022 04:56:46 -0800 X-Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mx.groups.io with SMTP id smtpd.web11.132918.1671109006264948563 for ; Thu, 15 Dec 2022 04:56:46 -0800 X-Received: by mail-pj1-f46.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso2699626pjt.0 for ; Thu, 15 Dec 2022 04:56:46 -0800 (PST) X-Gm-Message-State: wvaswmZfDk9WJnl5xD0mRRhUx1787277AA= X-Google-Smtp-Source: AA0mqf7O0Achrm5q2KutDTs/zlqh1YsRM3rOiMLOk29KsBv0Df5F9OI2L0CnwvW9ZaTbVKMa7QLZeg== X-Received: by 2002:a05:6a20:7b16:b0:af:757c:ce6b with SMTP id s22-20020a056a207b1600b000af757cce6bmr6227894pzh.51.1671109005427; Thu, 15 Dec 2022 04:56:45 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:45 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 04/23] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Date: Thu, 15 Dec 2022 18:26:07 +0530 Message-Id: <20221215125626.545372-5-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109006; bh=ReMDo0gCQVoDtOPNRVfhVf0P6SztvgEqR2alrv2n4fY=; h=Cc:Date:From:Reply-To:Subject:To; b=n/uiFNWX0LRWqpnQhpr7d1MQlHM1fenenqXh52IfCUjJbkDiJxpEHZpmFNkrInLiTqz q2yGxc0Rx7nNFNwJo+nxAUKWS5bYckWIHicuRUWku5zJmbOqD5Xqx4D+hcQLs2NSeDH5Y 8viHKnxjd88JzMiJLruieDL+k6vVKV6NUMo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109009397100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This library is required to make SBI ecalls from the S-mode EDK2. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- MdePkg/MdePkg.dec | 4 + MdePkg/MdePkg.dsc | 3 + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf | 25 +++ MdePkg/Include/Library/BaseRiscVSbiLib.h | 127 +++++++++++ MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 227 +++++++++++++++++= +++ 5 files changed, 386 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 4f30de588a46..69c1dfa4bf89 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -316,6 +316,10 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides function to support TDX processing. TdxLib|Include/Library/TdxLib.h =20 +[LibraryClasses.RISCV64] + ## @libraryclass Provides function to make ecalls to SBI + BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h + [Guids] # # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 32a852dc466e..0ac7618b4623 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -190,4 +190,7 @@ [Components.ARM, Components.AARCH64] MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf =20 +[Components.RISCV64] + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + [BuildOptions] diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf b/MdePkg/Li= brary/BaseRiscVSbiLib/BaseRiscVSbiLib.inf new file mode 100644 index 000000000000..d03132bf01c1 --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf @@ -0,0 +1,25 @@ +## @file +# RISC-V Library to call SBI ecalls +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D BaseRiscVSbiLib + FILE_GUID =3D D742CF3D-E600-4009-8FB5-318073008508 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSbiLib + +[Sources] + BaseRiscVSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib diff --git a/MdePkg/Include/Library/BaseRiscVSbiLib.h b/MdePkg/Include/Libr= ary/BaseRiscVSbiLib.h new file mode 100644 index 000000000000..3a3cbfb879f1 --- /dev/null +++ b/MdePkg/Include/Library/BaseRiscVSbiLib.h @@ -0,0 +1,127 @@ +/** @file + Library to call the RISC-V SBI ecalls + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Hart - Hardware Thread, similar to a CPU core + + Currently, EDK2 needs to call SBI only to set the time and to do system = reset. + +**/ + +#ifndef RISCV_SBI_LIB_H_ +#define RISCV_SBI_LIB_H_ + +#include + +/* SBI Extension IDs */ +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 + +/* SBI function IDs for TIME extension*/ +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for SRST extension */ +#define SBI_EXT_SRST_RESET 0x0 + +#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0 +#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1 +#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2 + +#define SBI_SRST_RESET_REASON_NONE 0x0 +#define SBI_SRST_RESET_REASON_SYSFAIL 0x1 + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + VOID *PrePiHobList; // Pre PI Hob List + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree +} EFI_RISCV_FIRMWARE_CONTEXT; + +// +// EDK2 OpenSBI firmware extension return status. +// +typedef struct { + UINTN Error; ///< SBI status code + UINTN Value; ///< Value returned +} SBI_RET; + +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ); + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ); + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ); + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ); + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ); + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ); + +#endif diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c b/MdePkg/Libr= ary/BaseRiscVSbiLib/BaseRiscVSbiLib.c new file mode 100644 index 000000000000..15222a528753 --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c @@ -0,0 +1,227 @@ +/** @file + Instance of the SBI ecall library. + + It allows calling an SBI function via an ecall from S-Mode. + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +// +// Maximum arguments for SBI ecall +#define SBI_CALL_MAX_ARGS 6 + +/** + Call SBI call using ecall instruction. + + Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS. + + @param[in] ExtId SBI extension ID. + @param[in] FuncId SBI function ID. + @param[in] NumArgs Number of arguments to pass to the ecall. + @param[in] ... Argument list for the ecall. + + @retval Returns SBI_RET structure with value and error code. + +**/ +STATIC +SBI_RET +EFIAPI +SbiCall ( + IN UINTN ExtId, + IN UINTN FuncId, + IN UINTN NumArgs, + ... + ) +{ + UINTN I; + SBI_RET Ret; + UINTN Args[SBI_CALL_MAX_ARGS]; + VA_LIST ArgList; + + VA_START (ArgList, NumArgs); + + if (NumArgs > SBI_CALL_MAX_ARGS) { + Ret.Error =3D SBI_ERR_INVALID_PARAM; + Ret.Value =3D -1; + return Ret; + } + + for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) { + if (I < NumArgs) { + Args[I] =3D VA_ARG (ArgList, UINTN); + } else { + // Default to 0 for all arguments that are not given + Args[I] =3D 0; + } + } + + VA_END (ArgList); + + register UINTN a0 asm ("a0") =3D Args[0]; + register UINTN a1 asm ("a1") =3D Args[1]; + register UINTN a2 asm ("a2") =3D Args[2]; + register UINTN a3 asm ("a3") =3D Args[3]; + register UINTN a4 asm ("a4") =3D Args[4]; + register UINTN a5 asm ("a5") =3D Args[5]; + register UINTN a6 asm ("a6") =3D (UINTN)(FuncId); + register UINTN a7 asm ("a7") =3D (UINTN)(ExtId); + + asm volatile ("ecall" \ + : "+r" (a0), "+r" (a1) \ + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \ + : "memory"); \ + Ret.Error =3D a0; + Ret.Value =3D a1; + return Ret; +} + +/** + Translate SBI error code to EFI status. + + @param[in] SbiError SBI error code + @retval EFI_STATUS +**/ +STATIC +EFI_STATUS +EFIAPI +TranslateError ( + IN UINTN SbiError + ) +{ + switch (SbiError) { + case SBI_SUCCESS: + return EFI_SUCCESS; + case SBI_ERR_FAILED: + return EFI_DEVICE_ERROR; + break; + case SBI_ERR_NOT_SUPPORTED: + return EFI_UNSUPPORTED; + break; + case SBI_ERR_INVALID_PARAM: + return EFI_INVALID_PARAMETER; + break; + case SBI_ERR_DENIED: + return EFI_ACCESS_DENIED; + break; + case SBI_ERR_INVALID_ADDRESS: + return EFI_LOAD_ERROR; + break; + case SBI_ERR_ALREADY_AVAILABLE: + return EFI_ALREADY_STARTED; + break; + default: + // + // Reaches here only if SBI has defined a new error type + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + break; + } +} + +/** + Clear pending timer interrupt bit and set timer for next event after Tim= e. + + To clear the timer without scheduling a timer event, set Time to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] Time The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ) +{ + SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time); +} + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ) +{ + SBI_RET Ret; + + Ret =3D SbiCall ( + SBI_EXT_SRST, + SBI_EXT_SRST_RESET, + 2, + ResetType, + ResetReason + ); + + return TranslateError (Ret.Error); +} + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ) +{ + *FirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT *)RiscVGetSupervisorScr= atch (); +} + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + RiscVSetSupervisorScratch ((UINT64)FirmwareContext); +} + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + GetFirmwareContext (FirmwareContextPtr); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + SetFirmwareContext (FirmwareContextPtr); +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97444): https://edk2.groups.io/g/devel/message/97444 Mute This Topic: https://groups.io/mt/95687624/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97445+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97445+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109010; cv=none; d=zohomail.com; s=zohoarc; b=T/BU997hV0LRX/3BwbV/w0mbL0KnrMA0hy7XgeuhbMXKagAjUVLcYBspWY2dUmumWz62mKC64r8+G0WFp1TklLZqYHGtoMgVmVCLaZ1+zarYsenTi+IgoG3UTA1p8jpSvQ8NWnOF6XNp2vJw1JIBZewat/ormFNvrIJdJhx/kbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109010; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TF4ga+vs24en2rQnP2Xlo9kFAK+OzrjcNtTlPSTW+oc=; b=h0l6CbgDM2jMeknrPv1y4S7iW1nNbWfRX5X/mjpNwnaHO3Q8mGqxsGNaDZd1GNj5a2ikfhdpV+y81fafz5dGlX3XL/xJd0+3dgMNiwydv2yEyVYJ1qRm/i4TzmxF2j9n0pjjsOxFu9Aa/1ArDG83yMBFuM4HWUUfSttFt+imlbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97445+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109009928436.4278701180823; Thu, 15 Dec 2022 04:56:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id vONkYY1788612xCck5poob8C; Thu, 15 Dec 2022 04:56:49 -0800 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web10.132060.1671109008930741457 for ; Thu, 15 Dec 2022 04:56:49 -0800 X-Received: by mail-pf1-f176.google.com with SMTP id t18so6605533pfq.13 for ; Thu, 15 Dec 2022 04:56:48 -0800 (PST) X-Gm-Message-State: sTxxB6rQGz8rbf8IUFvCO40Fx1787277AA= X-Google-Smtp-Source: AA0mqf66NFfcCde/KWzf2afVgAqm4crBcB9F1SaQRJrXcg2UMELeSQvzbGPec8cLJ2H9ZA7zqYvibA== X-Received: by 2002:a62:3342:0:b0:575:ff07:cb1e with SMTP id z63-20020a623342000000b00575ff07cb1emr26116492pfz.31.1671109008000; Thu, 15 Dec 2022 04:56:48 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:47 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 05/23] UefiCpuPkg: Add CpuTimerDxe module Date: Thu, 15 Dec 2022 18:26:08 +0530 Message-Id: <20221215125626.545372-6-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109009; bh=9XIgDJI7q2iPObs+6s8XOOKkTP4X8Uv+WOtK94HA6Cc=; h=Cc:Date:From:Reply-To:Subject:To; b=qMWT5IiG4kJa6fRK/AkTUAXlrwT5kmpYAswUW1aWl+/m8KQS2kIlS362PkUjDIDWLx1 U64xteMHnYbpmFSN18OWGa9LDtLUaKQ3OZvp2mZKuf/UXwn8XZqivgnCKw7gLfEaefauq kctcWx7y+D8j7Dq1BygGLaK11x6RiBhjMQo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109011406100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- UefiCpuPkg/UefiCpuPkg.dsc | 3 + UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf | 51 ++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h | 177 ++++++++++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c | 294 ++++++++++++++++++++ UefiCpuPkg/CpuTimerDxe/CpuTimer.uni | 14 + UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni | 12 + 6 files changed, 551 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f9a46089d2c7..96f6770281fe 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -195,5 +195,8 @@ [Components.IA32, Components.X64] [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandle= rLibUnitTest.inf =20 +[Components.RISCV64] + UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf + [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf b/UefiCpuPkg/CpuTimerDx= e/CpuTimerDxe.inf new file mode 100644 index 000000000000..d7706328b591 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf @@ -0,0 +1,51 @@ +## @file +# Timer Arch protocol module +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D CpuTimerDxe + MODULE_UNI_FILE =3D CpuTimer.uni + FILE_GUID =3D 055DDAC6-9142-4013-BF20-FC2E5BC325C9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D TimerDriverInitialize +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + CpuLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Sources.RISCV64] + RiscV64/Timer.h + RiscV64/Timer.c + +[Protocols] + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiTimerArchProtocolGuid ## PRODUCES + +[Depex] + gEfiCpuArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + CpuTimerExtra.uni diff --git a/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h b/UefiCpuPkg/CpuTimerDx= e/RiscV64/Timer.h new file mode 100644 index 000000000000..586eb0cfadb4 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h @@ -0,0 +1,177 @@ +/** @file + RISC-V Timer Architectural Protocol definitions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TIMER_H_ +#define TIMER_H_ + +#include + +#include +#include + +#include +#include +#include +#include + +// +// RISC-V use 100us timer. +// The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units +// +#define DEFAULT_TIMER_TICK_DURATION 100000 + +extern VOID +RiscvSetTimerPeriod ( + UINT32 TimerPeriod + ); + +// +// Function Prototypes +// + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +; + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +; + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +; + +#endif diff --git a/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c b/UefiCpuPkg/CpuTimerDx= e/RiscV64/Timer.c new file mode 100644 index 000000000000..db153f715e60 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c @@ -0,0 +1,294 @@ +/** @file + RISC-V Timer Architectural Protocol + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "Timer.h" + +// +// The handle onto which the Timer Architectural Protocol will be installed +// +STATIC EFI_HANDLE mTimerHandle =3D NULL; + +// +// The Timer Architectural Protocol that this driver produces +// +EFI_TIMER_ARCH_PROTOCOL mTimer =3D { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +// +// Pointer to the CPU Architectural Protocol instance +// +EFI_CPU_ARCH_PROTOCOL *mCpu; + +// +// The notification function to call on every timer interrupt. +// A bug in the compiler prevents us from initializing this here. +// +STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; + +// +// The current period of the timer interrupt +// +STATIC UINT64 mTimerPeriod =3D 0; + +/** + Timer Interrupt Handler. + + @param InterruptType The type of interrupt that occured + @param SystemContext A pointer to the system context when the interru= pt occured +**/ +VOID +EFIAPI +TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 RiscvTimer; + + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + if (mTimerNotifyFunction !=3D NULL) { + mTimerNotifyFunction (mTimerPeriod); + } + + RiscVDisableTimerInterrupt (); // Disable SMode timer int + RiscVClearPendingTimerInterrupt (); + if (mTimerPeriod =3D=3D 0) { + gBS->RestoreTPL (OriginalTPL); + RiscVDisableTimerInterrupt (); // Disable SMode timer int + return; + } + + RiscvTimer =3D RiscVReadTimer (); + SbiSetTimer (RiscvTimer +=3D mTimerPeriod); + gBS->RestoreTPL (OriginalTPL); + RiscVEnableTimerInterrupt (); // enable SMode timer int +} + +/** + + This function registers the handler NotifyFunction so it is called every= time + the timer interrupt fires. It also passes the amount of time since the = last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS= is + returned. If the CPU does not support registering a timer interrupt han= dler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a h= andler + when a handler is already registered, then EFI_ALREADY_STARTED is return= ed. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ER= ROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fire= s. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so i= t can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support time= r interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a = handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a hand= ler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be reg= istered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", Notify= Function)); + mTimerNotifyFunction =3D NotifyFunction; + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 RiscvTimer; + + DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod)); + + if (TimerPeriod =3D=3D 0) { + mTimerPeriod =3D 0; + RiscVDisableTimerInterrupt (); // Disable SMode timer int + return EFI_SUCCESS; + } + + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us + RiscvTimer =3D RiscVReadTimer (); + SbiSetTimer (RiscvTimer + mTimerPeriod); + + mCpu->EnableInterrupt (mCpu); + RiscVEnableTimerInterrupt (); // enable SMode timer int + return EFI_SUCCESS; +} + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + *TimerPeriod =3D mTimerPeriod; + return EFI_SUCCESS; +} + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize the pointer to our notify function. + // + mTimerNotifyFunction =3D NULL; + + // + // Make sure the Timer Architectural Protocol is not already installed i= n the system + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid); + + // + // Find the CPU architectural protocol. + // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= )&mCpu); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be disabled + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, 0); + ASSERT_EFI_ERROR (Status); + + // + // Install interrupt handler for RISC-V Timer. + // + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be enabled at its default period + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATI= ON); + ASSERT_EFI_ERROR (Status); + + // + // Install the Timer Architectural Protocol onto a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mTimerHandle, + &gEfiTimerArchProtocolGuid, + &mTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimer.uni b/UefiCpuPkg/CpuTimerDxe/C= puTimer.uni new file mode 100644 index 000000000000..76de1f3f352a --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/CpuTimer.uni @@ -0,0 +1,14 @@ +// /** @file +// +// Timer Arch protocol strings. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Timer driver that= provides Timer Arch protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "Timer driver that= provides Timer Arch protocol." diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni b/UefiCpuPkg/CpuTimer= Dxe/CpuTimerExtra.uni new file mode 100644 index 000000000000..ceb93a7ce82f --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// Timer Localized Strings and Content +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Timer DXE Driver" --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97445): https://edk2.groups.io/g/devel/message/97445 Mute This Topic: https://groups.io/mt/95687627/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97446+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97446+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109012; cv=none; d=zohomail.com; s=zohoarc; b=GSOi0rww9vuoU6wwzgni0LrRiKQCqDxS+MwLzagDbxSf+REeZFDJLTADviKHmFxNyjXPO+yhJWn8lDksFe+kicJM1w+tjgqEcqawU+8ltcrDi/5BNJayG+NTYWl7EiVHWOYgUN9X1ieDyfHRKIGkbTkBh5J5MVs3bghTiokCCnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RXRaC/svRSWSh8RR5jEPnA/s8l6xO30JX6rhhpaHm/o=; b=SbnzWzg8tBRaCiM7vkt9frMutaH4P4vTKgQrFH3+oBgKHTI9z+zuq/aOrAAIdScaVPffudwZJ3mwevA1U8wSC/bdZZv/ubXPmYkCFXKJPhL/gEl03wuEa0Rk/oaU+t7z73n1lfZzDvBwleFEYYpD6WuqWWv7RWdTX5Onb17DmjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97446+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109012214529.5879180130646; Thu, 15 Dec 2022 04:56:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id pITnYY1788612xM6P5cqgYOm; Thu, 15 Dec 2022 04:56:51 -0800 X-Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web10.132061.1671109011214247238 for ; Thu, 15 Dec 2022 04:56:51 -0800 X-Received: by mail-pg1-f169.google.com with SMTP id s196so4105937pgs.3 for ; Thu, 15 Dec 2022 04:56:51 -0800 (PST) X-Gm-Message-State: 1nRkzbRqjrpXHXKcAjx9lFogx1787277AA= X-Google-Smtp-Source: AA0mqf4TQANfDzLybf8TSjkp5KUSilxW9ENnBlJ8EZfiMaTiWWPFEYzVerpT04ny3oS1Wt4Nc0AZhQ== X-Received: by 2002:a05:6a00:1696:b0:56a:beee:d0a7 with SMTP id k22-20020a056a00169600b0056abeeed0a7mr36888659pfc.26.1671109010522; Thu, 15 Dec 2022 04:56:50 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:50 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 06/23] UefiCpuPkg/CpuExceptionHandlerLib: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:09 +0530 Message-Id: <20221215125626.545372-7-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109011; bh=hkLI4Gpd0XN3DA02UkMDw0vICbEhctJGuli2sYrzf5Y=; h=Cc:Date:From:Reply-To:Subject:To; b=mUaaL8y3fFH+YO9cstUxdeZTdpjFVAohBE4URwQ0TcHYAwMRz4/IKQyFRqBK37T37Pi ctxTyi39jbBJ2SA/Sk3wZGbX4ofDOgIJjm3jmnmI+41679hbE+iaenJCyaH5OcVPL9uhl X2kQ4kGZ88jmyK+Kht43bnuEUKygd9HaX2U= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109013455100010 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add Cpu Exception Handler library for RISC-V. This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- UefiCpuPkg/UefiCpuPkg.dsc = | 1 + UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLi= b.inf | 42 +++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h= | 116 +++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c= | 133 ++++++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S = | 105 ++++++++++++++++ 5 files changed, 397 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 96f6770281fe..251a8213f022 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -197,6 +197,7 @@ [Components.X64] =20 [Components.RISCV64] UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandler= Lib.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExcept= ionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64Cp= uExceptionHandlerLib.inf new file mode 100644 index 000000000000..82ca22c4bfec --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHand= lerLib.inf @@ -0,0 +1,42 @@ +## @file +# RISC-V CPU Exception Handler Library +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseRiscV64CpuExceptionHandlerLib + MODULE_UNI_FILE =3D BaseRiscV64CpuExceptionHandlerLib.uni + FILE_GUID =3D 6AB0D5FD-E615-45A3-9374-E284FB061FC9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CpuExceptionHandlerLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/SupervisorTrapHandler.S + RiscV64/CpuExceptionHandlerLib.c + RiscV64/CpuExceptionHandlerLib.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + SerialPortLib + PrintLib + SynchronizationLib + PeCoffGetEntryPointLib + MemoryAllocationLib + DebugLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.h new file mode 100644 index 000000000000..30f47e87552b --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.h @@ -0,0 +1,116 @@ +/** @file + + RISC-V Exception Handler library definition file. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_ +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_ + +#include + +/** + Trap Handler for S-mode + +**/ +VOID +SupervisorModeTrap ( + VOID + ); + +// +// Index of SMode trap register +// +#define SMODE_TRAP_REGS_zero 0 +#define SMODE_TRAP_REGS_ra 1 +#define SMODE_TRAP_REGS_sp 2 +#define SMODE_TRAP_REGS_gp 3 +#define SMODE_TRAP_REGS_tp 4 +#define SMODE_TRAP_REGS_t0 5 +#define SMODE_TRAP_REGS_t1 6 +#define SMODE_TRAP_REGS_t2 7 +#define SMODE_TRAP_REGS_s0 8 +#define SMODE_TRAP_REGS_s1 9 +#define SMODE_TRAP_REGS_a0 10 +#define SMODE_TRAP_REGS_a1 11 +#define SMODE_TRAP_REGS_a2 12 +#define SMODE_TRAP_REGS_a3 13 +#define SMODE_TRAP_REGS_a4 14 +#define SMODE_TRAP_REGS_a5 15 +#define SMODE_TRAP_REGS_a6 16 +#define SMODE_TRAP_REGS_a7 17 +#define SMODE_TRAP_REGS_s2 18 +#define SMODE_TRAP_REGS_s3 19 +#define SMODE_TRAP_REGS_s4 20 +#define SMODE_TRAP_REGS_s5 21 +#define SMODE_TRAP_REGS_s6 22 +#define SMODE_TRAP_REGS_s7 23 +#define SMODE_TRAP_REGS_s8 24 +#define SMODE_TRAP_REGS_s9 25 +#define SMODE_TRAP_REGS_s10 26 +#define SMODE_TRAP_REGS_s11 27 +#define SMODE_TRAP_REGS_t3 28 +#define SMODE_TRAP_REGS_t4 29 +#define SMODE_TRAP_REGS_t5 30 +#define SMODE_TRAP_REGS_t6 31 +#define SMODE_TRAP_REGS_sepc 32 +#define SMODE_TRAP_REGS_sstatus 33 +#define SMODE_TRAP_REGS_sie 34 +#define SMODE_TRAP_REGS_last 35 + +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__) +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last) + +#pragma pack(1) +typedef struct { + // + // Below are follow the format of EFI_SYSTEM_CONTEXT + // + UINT64 zero; + UINT64 ra; + UINT64 sp; + UINT64 gp; + UINT64 tp; + UINT64 t0; + UINT64 t1; + UINT64 t2; + UINT64 s0; + UINT64 s1; + UINT64 a0; + UINT64 a1; + UINT64 a2; + UINT64 a3; + UINT64 a4; + UINT64 a5; + UINT64 a6; + UINT64 a7; + UINT64 s2; + UINT64 s3; + UINT64 s4; + UINT64 s5; + UINT64 s6; + UINT64 s7; + UINT64 s8; + UINT64 s9; + UINT64 s10; + UINT64 s11; + UINT64 t3; + UINT64 t4; + UINT64 t5; + UINT64 t6; + // + // Below are the additional information to + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap + // and not public to EFI environment. + // + UINT64 sepc; + UINT64 sstatus; + UINT64 sie; +} SMODE_TRAP_REGISTERS; +#pragma pack() + +#endif diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.c new file mode 100644 index 000000000000..f1ee7d236aec --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.c @@ -0,0 +1,133 @@ +/** @file + RISC-V Exception Handler library implementation. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "CpuExceptionHandlerLib.h" + +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; + +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + RiscVSetSupervisorStvec ((UINT64)SupervisorModeTrap); + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler)); + mInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} + +/** + Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. + + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. + + @retval EFI_SUCCESS The stacks are assigned successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. +**/ +EFI_STATUS +EFIAPI +InitializeSeparateExceptionStacks ( + IN VOID *Buffer, + IN OUT UINTN *BufferSize + ) +{ + return EFI_SUCCESS; +} + +/** + Supervisor mode trap handler. + + @param[in] SmodeTrapReg Registers before trap occurred. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + SMODE_TRAP_REGISTERS *SmodeTrapReg + ) +{ + UINTN SCause; + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg; + // + // Check scasue register. + // + SCause =3D (UINTN)RiscVGetSupervisorTrapCause (); + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) { + // + // This is interrupt event. + // + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1)); + if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) { + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext); + } + } +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTr= apHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorT= rapHandler.S new file mode 100644 index 000000000000..649c4c5becf4 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandl= er.S @@ -0,0 +1,105 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuExceptionHandlerLib.h" + + .align 3 + .section .entry, "ax", %progbits + .globl SupervisorModeTrap +SupervisorModeTrap: + addi sp, sp, -SMODE_TRAP_REGS_SIZE + + /* Save all general regisers except SP */ + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + csrr t0, CSR_SSTATUS + and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE) + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + csrr t0, CSR_SEPC + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrr t0, CSR_SIE + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP */ + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrw CSR_SEPC, t0 + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + csrw CSR_SIE, t0 + csrr t0, CSR_SSTATUS + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + or t0, t0, t1 + csrw CSR_SSTATUS, t0 + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + addi sp, sp, SMODE_TRAP_REGS_SIZE + sret --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97446): https://edk2.groups.io/g/devel/message/97446 Mute This Topic: https://groups.io/mt/95687628/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97447+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97447+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109014; cv=none; d=zohomail.com; s=zohoarc; b=kzN7K5a057jLPzjcN/XjDqvgdyQX6qc/wigVV6h99Twv4wmMPgmGOUsZ8ERgEvDYBK+232lg/99MqEh03nInqGpvvSiliqpAr37amlitsCAC5xFncfMGtUU6vKLTk7vOvCXaAC4RXwONlOFX1jMeHzwChZCYyEL5WQzNwTUQ3EI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109014; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Y+pnB0P8fCbNFLTACPPQy3xP3K39VDbNI3xNppnOE8I=; b=X+9WlAKKFT771+5Y34tMFRea5xKOs7JKQwSH/niHGgS9z9fSt/GKM++/WE5f0fKx/XbKZdLEGezxRf3h43QvyaTXbG4xAw03cwojece0DuVsV9FFBe3r3HMHU7X3ZtHWk0inLMMMVueWNr4daR5A84rsmmfJztBesygTc2A0SWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97447+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109014763685.5128852773043; Thu, 15 Dec 2022 04:56:54 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id xwUhYY1788612xx7PIzrbHdH; Thu, 15 Dec 2022 04:56:54 -0800 X-Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) by mx.groups.io with SMTP id smtpd.web10.132064.1671109014026124484 for ; Thu, 15 Dec 2022 04:56:54 -0800 X-Received: by mail-pl1-f181.google.com with SMTP id g10so6737403plo.11 for ; Thu, 15 Dec 2022 04:56:53 -0800 (PST) X-Gm-Message-State: VMKn14WBdcsWrk1GizgLscAkx1787277AA= X-Google-Smtp-Source: AA0mqf7hsugY8WjaH7Q2j8nk8NNhjazxY3CVYpqcR+07xECa3Im+8lWj1xS8athMmU5DS13g+RodBg== X-Received: by 2002:a05:6a20:6983:b0:a3:754c:2769 with SMTP id t3-20020a056a20698300b000a3754c2769mr39388945pzk.40.1671109013189; Thu, 15 Dec 2022 04:56:53 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:52 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 07/23] UefiCpuPkg/CpuDxe: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:10 +0530 Message-Id: <20221215125626.545372-8-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109014; bh=wY1IWTZnnwmeXgI/A0iGCZyHVryDye8wv29GNmwlP5Y=; h=Cc:Date:From:Reply-To:Subject:To; b=gPCZBijnOtW5p3uBnTIDL1HLSBjRCdBs4LZQTWqXOMH4Dnoz9Hsg5C/hw0eYOQPBmtq b8I4kzIUg+jiGC3JIWdj7Xk14qi3/XMnCUmZR4UkCS6Ay8S2Wgogis+D2B+scX86HVkdo PX/XYNE3L7nlfiWd2tMqGJBe5qi1nRV6vbE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109015553100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- UefiCpuPkg/UefiCpuPkg.dsc | 1 + UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf | 68 ++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 199 +++++++++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 365 ++++++++++++++++++++ 4 files changed, 633 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 251a8213f022..8f2be6cd1b05 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -198,6 +198,7 @@ [Components.X64] [Components.RISCV64] UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandler= Lib.inf + UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxe/CpuDxe= RiscV64.inf new file mode 100644 index 000000000000..5e590d03754f --- /dev/null +++ b/UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf @@ -0,0 +1,68 @@ +## @file +# RISC-V CPU DXE module. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D CpuDxeRiscV64 + MODULE_UNI_FILE =3D CpuDxe.uni + FILE_GUID =3D BDEA19E2-778F-473C-BF82-5E38D6A27765 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeCpu + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + CpuExceptionHandlerLib + HobLib + ReportStatusCodeLib + TimerLib + PeCoffGetEntryPointLib + RiscVSbiLib + +[Sources] + RiscV64/CpuDxe.c + RiscV64/CpuDxe.h + +[Protocols] + gEfiCpuArchProtocolGuid ## PRODUCES + gRiscVEfiBootProtocolGuid ## PRODUCES + +[Guids] + gIdleLoopEventGuid ## CONSUMES ## E= vent + +[Ppis] + gEfiSecPlatformInformation2PpiGuid ## UNDEFINED # HOB + gEfiSecPlatformInformationPpiGuid ## UNDEFINED # HOB + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##= CONSUMES + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + CpuDxeExtra.uni diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.h new file mode 100644 index 000000000000..49f4e119665a --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h @@ -0,0 +1,199 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef CPU_DXE_H_ +#define CPU_DXE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c new file mode 100644 index 000000000000..7551e0653603 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -0,0 +1,365 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuDxe.h" + +// +// Global Variables +// +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is = not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + mInterruptState =3D TRUE; + return EFI_SUCCESS; +} + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + mInterruptState =3D FALSE; + return EFI_SUCCESS; +} + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D mInterruptState; + return EFI_SUCCESS; +} + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + if (TimerValue =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (TimerIndex !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + *TimerValue =3D (UINT64)RiscVReadTimer (); + if (TimerPeriod !=3D NULL) { + *TimerPeriod =3D DivU64x32 ( + 1000000000000000u, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ); + } + + return EFI_SUCCESS; +} + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__)); + return EFI_SUCCESS; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + InitializeCpuExceptionHandlers (NULL); + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + // + // Install Boot protocol + // + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, + &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97447): https://edk2.groups.io/g/devel/message/97447 Mute This Topic: https://groups.io/mt/95687629/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97448+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97448+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109017; cv=none; d=zohomail.com; s=zohoarc; b=NlntO2kLBb20rShdE4EDHjagVgxdWsrxd3PolfcONRIlRyj7AeSlfQW9L+HPPyg+wBm3LbJFfLBzPBBreFIoDH01YyG54JtQKzuCOcnrUXGgPPXQMIiGk10DsK9itwpFtSgPu12pfRYaz27wbQBGT5l3bMK7jGtpe8/xNIZ1pw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109017; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0x5fFvPe6sG+quFtaOYeeugn87P2O5vuiAhT5iMfCBM=; b=iDy9pz7fFxQUSsiXOiaVHJjueXNQguMil5odMcUAQcbRU7cPcbeOiWb7yQM+ow8Xmb4DwB9AWybJjvOvVnCk7sTHmpcxhsArrfKtACh6v+r/rqjqMsE+5Mwks8OOt57NGlMjaPUe3jK8bzkSqI+1T30GXKBDNSXsPz3OreBQrg8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97448+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16711090174741.4308549596203193; Thu, 15 Dec 2022 04:56:57 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ew9TYY1788612xKfUnhdXB8E; Thu, 15 Dec 2022 04:56:56 -0800 X-Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web10.132065.1671109016309471170 for ; Thu, 15 Dec 2022 04:56:56 -0800 X-Received: by mail-pf1-f172.google.com with SMTP id g1so6646986pfk.2 for ; Thu, 15 Dec 2022 04:56:56 -0800 (PST) X-Gm-Message-State: K2H2u2xkkJpSjl7QtDgnC2M8x1787277AA= X-Google-Smtp-Source: AA0mqf7CzmQBoIW0rK6QGw/MKv6W+ZmyQWihjomeNXj+vyVQQxEDHmnadwGx0bILAt5aWxXQBgO8yQ== X-Received: by 2002:a05:6a00:2481:b0:576:3005:bb4d with SMTP id c1-20020a056a00248100b005763005bb4dmr38428752pfv.31.1671109015594; Thu, 15 Dec 2022 04:56:55 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:55 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 08/23] UefiCpuPkg/CpuTimerLib: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:11 +0530 Message-Id: <20221215125626.545372-9-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109016; bh=OHg7q1y+rYdFaV73YBxVis6mlTlxCoyAwXw+Mhtt3dc=; h=Cc:Date:From:Reply-To:Subject:To; b=UqP23N+RH6O+rWgrIo1j7SaBF7rSqQ1HmX6D3lBDj5zFZwxX/PM5zE2yybBQicpU4En 5WS0sXU0/tkocYMDynth1wBu4Kz4VE7PnckgStCElbqafnGRFFINwbJNNuIeAKnPjfG34 47U8WMpxoMCFqAoMC9LCwi5sukzLb1zVgzg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109019466100007 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- UefiCpuPkg/UefiCpuPkg.dsc | 1 + UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf | 32 ++++ UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++++++++= ++++++++++ 3 files changed, 232 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 8f2be6cd1b05..2df02bf75a35 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -199,6 +199,7 @@ [Components.RISCV64] UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandler= Lib.inf UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf + UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf b/Ue= fiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf new file mode 100644 index 000000000000..c920e8e098b5 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf @@ -0,0 +1,32 @@ +## @file +# RISC-V Base CPU Timer Library Instance +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseRisV64CpuTimerLib + FILE_GUID =3D B635A600-EA24-4199-88E8-5761EEA96A51 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + +[Sources] + RiscV64/CpuTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c b/UefiCpu= Pkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 000000000000..9c8efc0f3530 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,199 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D RiscVReadTimer () + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS = - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuC= oreCrystalClockFrequency), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= PcdGet64 (PcdCpuCoreCrystalClockFrequency)); + + return NanoSeconds; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97448): https://edk2.groups.io/g/devel/message/97448 Mute This Topic: https://groups.io/mt/95687630/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97449+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97449+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109019; cv=none; d=zohomail.com; s=zohoarc; b=dvp0pxXyknthQNOgPYE+wO9grADxaUoXH94fb+0zhAw5qGn0p3EC4O3ZawgkGKsh01F6vFjbibrKfGBApUcXhaUxiJR7vJKKc6pKzm9JFz9JzyzCQTyZtiPF8ik9cDLn2UrffyikbGg0yVZSW2XPjX876LaczrvxGH8Cd5zVxQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109019; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9QksOH9kGP+CDs6UvDguq+qzl5EiujNl9gRtprNZT2I=; b=aOOrA8orzi2JoBvLycay846o20JSVA5I8ZMLUMaTjFFYMZ5QkLBUYES6y6fYHxhtuWDTV/PIfvmAI+L9BXmosMWFHp1I7tl8CPCqHwvHy9HxYcPEXh+F+qoaOmJdnimn2cZeL8rQW0dK0jWOWzL3jZzupae5cNBpZWsI5AgcukQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97449+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167110901949055.32019871085549; Thu, 15 Dec 2022 04:56:59 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4vOgYY1788612xHYdOoMysYG; Thu, 15 Dec 2022 04:56:59 -0800 X-Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) by mx.groups.io with SMTP id smtpd.web11.132926.1671109018611003384 for ; Thu, 15 Dec 2022 04:56:58 -0800 X-Received: by mail-pg1-f170.google.com with SMTP id 79so4079948pgf.11 for ; Thu, 15 Dec 2022 04:56:58 -0800 (PST) X-Gm-Message-State: lf8uSmxxCiBGYWGyZH2nhMH7x1787277AA= X-Google-Smtp-Source: AA0mqf4Boz8XjdggpeIMCalWwl1MDeK1YaezkoFF2qO861S9oDx4himdQxp4Rp3uY2wBmxACG4x9yA== X-Received: by 2002:a05:6a00:1d12:b0:578:74bc:c6da with SMTP id a18-20020a056a001d1200b0057874bcc6damr18922576pfx.17.1671109017812; Thu, 15 Dec 2022 04:56:57 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:57 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 09/23] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file Date: Thu, 15 Dec 2022 18:26:12 +0530 Message-Id: <20221215125626.545372-10-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109019; bh=GHI9k1nHHDEGVSMRrJ4Af/fQTkCiYWEEmJdFhVKu87g=; h=Cc:Date:From:Reply-To:Subject:To; b=a/sGdqe0SbX+2jI8qt95Aa4yTzU4FRkCATXpQFHVfyto98B38aq+j915asCvrb0sXpj 4Z3HA46CWRjp/tXxWJVv2/Ycl+IsBZm3BATRKAxBceHuKw3AivZuG6XRySjtVwdKdMrxe tYutw4tsW//vTv4evpGhqqXx0Pe7d/TbHDo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109021392100009 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index a377366798b0..953361ba0479 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -27,6 +27,7 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ + "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h" ] }, "CompilerPlugin": { --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97449): https://edk2.groups.io/g/devel/message/97449 Mute This Topic: https://groups.io/mt/95687631/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97450+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97450+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109021; cv=none; d=zohomail.com; s=zohoarc; b=Oa216/HVLoTVVxIfV1k2MmFsTNlZAEd8eUFW0ZTTuVb892YWa5h60KnaB4UsRBJ1LG+sPeFx42LoZtyQuHhcmNvIKMQaUTRt5iNdg6LKFtuCUavDOTbsXAxgtiPjK1WHPDzGSxMmbB2r4f7W1iXby2I/jr8irVi/ndoGMBpYMkQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109021; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=38Tkcz6NKHSFqk4mM2ttXn2S42hyrk1onaewB1ddgtY=; b=GNmB9aHmWDmep1r90g0SED7aMsVeA9XIbdlB115pxzq8EsJstIq7B0WqSfplEfc4uAK8M1lOQEGVRhc8CoHgWxNGy4P5M4A+rt2gC64qRrmU9Bxqp1e6QxGykts+326JdqsomK66994rzH4Vt4pZpCW3jGpVXzmQzWCPF9JkxeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97450+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167110902175737.157179805798364; Thu, 15 Dec 2022 04:57:01 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id c7u5YY1788612xYHfwv223ko; Thu, 15 Dec 2022 04:57:01 -0800 X-Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web11.132914.1671108999018885374 for ; Thu, 15 Dec 2022 04:57:01 -0800 X-Received: by mail-pg1-f169.google.com with SMTP id q71so4091367pgq.8 for ; Thu, 15 Dec 2022 04:57:00 -0800 (PST) X-Gm-Message-State: 5blPgCe4heDzasXSWueda4hSx1787277AA= X-Google-Smtp-Source: AA0mqf7jdcSHbBTNtJkfbxIhz5VZdeiH8n6foz/OAtZOWBwBe5EBrGaOIMydxagqg/5CcRVFxpSptQ== X-Received: by 2002:a05:6a00:26c5:b0:576:fb7c:7aa3 with SMTP id p5-20020a056a0026c500b00576fb7c7aa3mr26166111pfw.14.1671109020397; Thu, 15 Dec 2022 04:57:00 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:59 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Abner Chang , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 10/23] EmbeddedPkg: Enable PcdPrePiCpuIoSize for RISC-V Date: Thu, 15 Dec 2022 18:26:13 +0530 Message-Id: <20221215125626.545372-11-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109021; bh=7gkyE4x8fWDUMJqdHfpn5kDrRtTZjo/gSqGu2vOZnpw=; h=Cc:Date:From:Reply-To:Subject:To; b=mWj6xJ3akKx6Yyrr82IH+N9NtI5gN9O+KzfjtvPRW0wpEpgassKhHYqBYvi3i8VxviY FSBdlecPLu1fdTqc+Uieoq2D4qeDoKunIIMOujr1onizUGBmOZLKOCx1JK7LwbJuMVc1E 4OpAHdwXdra86ZGWfLJrTaKNGyjUOW82x5Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109023393100013 Content-Type: text/plain; charset="utf-8" This PCD is required to be enabled so that PrePiLib can be used in RISC-V. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Abner Chang Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- EmbeddedPkg/EmbeddedPkg.dec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index 341ef5e6a679..e7407a300a76 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -165,6 +165,9 @@ [PcdsFixedAtBuild.IA32] [PcdsFixedAtBuild.X64] gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x00000011 =20 +[PcdsFixedAtBuild.RISCV64] + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16|UINT8|0x00000011 + [PcdsFixedAtBuild.common, PcdsDynamic.common] # # Value to add to a host address to obtain a device address, using --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97450): https://edk2.groups.io/g/devel/message/97450 Mute This Topic: https://groups.io/mt/95687632/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97451+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97451+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109025; cv=none; d=zohomail.com; s=zohoarc; b=mkIXVSTbOUmQadNkg5nrTzPZkgfnD8lNTE1lsreIKU4kh8evlqBHMHyTRR/Lf72NPmvTedbsV+xeQOb3J976PD6XtEvZF5hzbWYweCaSv1S0XtDdwT0w0Wn027CxUIVOIs5Yo01Edwnpl9NQ7ktyleo5UowIA5lCfB9ES4UjvJI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109025; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=UGzixEfdtPzqHSz/m/7YLH/rYRbFqOgNv9Tl3cUEqT8=; b=Xsx/YPyuPhb8lnkgNQRE0jrZcNvMmO/0OYe6sXIjqvQM2PQEoUiiByeZ+jobW/neL8ht5z14H12VvlPrDfOtf7WKFleAopScgrMJlsHU8MzLURgGo/PhFNbcUWtWEz+neQGVaoQJ/5/86O2BpEHBU4qNTIl3fTI8D4GiGYvSIWo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97451+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16711090256541010.3385501584529; Thu, 15 Dec 2022 04:57:05 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3vIzYY1788612xGW3Q38vZo8; Thu, 15 Dec 2022 04:57:05 -0800 X-Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) by mx.groups.io with SMTP id smtpd.web10.132069.1671109024584539938 for ; Thu, 15 Dec 2022 04:57:04 -0800 X-Received: by mail-pj1-f42.google.com with SMTP id q17-20020a17090aa01100b002194cba32e9so2661526pjp.1 for ; Thu, 15 Dec 2022 04:57:04 -0800 (PST) X-Gm-Message-State: W5LhU8ExyEwOySJ5LKAnhxJJx1787277AA= X-Google-Smtp-Source: AA0mqf5BdmgLiyd13TZtnobLNTRZAwMtRU7p+Odp0ZjqUGV2oPmAZ/5sX1+xowA+e0VIQNBeogdNTA== X-Received: by 2002:a05:6a20:9e4a:b0:ac:1265:d5bb with SMTP id mt10-20020a056a209e4a00b000ac1265d5bbmr31051406pzb.49.1671109023803; Thu, 15 Dec 2022 04:57:03 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:03 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Abner Chang , Daniel Schaefer , Jian J Wang , Liming Gao , Andrew Fish , Michael D Kinney , Ard Biesheuvel Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 11/23] EmbeddedPkg/NvVarStoreFormattedLib: Migrate to MdeModulePkg Date: Thu, 15 Dec 2022 18:26:14 +0530 Message-Id: <20221215125626.545372-12-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109025; bh=Et30rk3tmcq65y8on6paMEPz7eHIDII1+mSjVvaq0O0=; h=Cc:Date:From:Reply-To:Subject:To; b=dHmKI6vLJKrQ+e6tbwB7UB8c81afDDmTgkREqsOo/zM5fxIbHgm3PWVspYMdWrAlj3x 7G7nDyv8tP00GEZq8aRo90VceL1dT+EZejzkuXRPkJwvA3SWmxAjeTr2rgdUN29AYbJRK JKmpvLntH08Z/NirK0byVJvUQ37rMuqnhxE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109027433100002 Content-Type: text/plain; charset="utf-8" This library is required by NorFlashDxe. Since it will be used by both virtual and real platforms, migrate this library to MdeModulePkg. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Abner Chang Cc: Daniel Schaefer Cc: Jian J Wang Cc: Liming Gao Cc: Andrew Fish Cc: Michael D Kinney Signed-off-by: Sunil V L Acked-by: Ard Biesheuvel Reviewed-by: Andrei Warkentin --- EmbeddedPkg/EmbeddedPkg.dec = | 3 --- MdeModulePkg/MdeModulePkg.dec = | 3 +++ MdeModulePkg/MdeModulePkg.dsc = | 2 ++ {EmbeddedPkg =3D> MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreF= ormattedLib.inf | 1 - {EmbeddedPkg =3D> MdeModulePkg}/Include/Guid/NvVarStoreFormatted.h = | 0 {EmbeddedPkg =3D> MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreF= ormattedLib.c | 0 6 files changed, 5 insertions(+), 4 deletions(-) diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index e7407a300a76..68702867312b 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -69,9 +69,6 @@ [Guids.common] # HII form set GUID for ConsolePrefDxe driver gConsolePrefFormSetGuid =3D { 0x2d2358b4, 0xe96c, 0x484d, { 0xb2, 0xdd, = 0x7c, 0x2e, 0xdf, 0xc7, 0xd5, 0x6f } } =20 - ## Include/Guid/NvVarStoreFormatted.h - gEdkiiNvVarStoreFormattedGuid =3D { 0xd1a86e3f, 0x0707, 0x4c35, { 0x83, = 0xcd, 0xdc, 0x2c, 0x29, 0xc8, 0x91, 0xa3 } } - [Protocols.common] gHardwareInterruptProtocolGuid =3D { 0x2890B3EA, 0x053D, 0x1643, { 0xAD= , 0x0C, 0xD6, 0x48, 0x08, 0xDA, 0x3F, 0xF1 } } gHardwareInterrupt2ProtocolGuid =3D { 0x32898322, 0x2da1, 0x474a, { 0xba= , 0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94, 0x70 } } diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index be5e829ca9c5..e46bfd6d593c 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -412,6 +412,9 @@ [Guids] ## Include/Guid/MigratedFvInfo.h gEdkiiMigratedFvInfoGuid =3D { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4,= 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } } =20 + ## Include/Guid/NvVarStoreFormatted.h + gEdkiiNvVarStoreFormattedGuid =3D { 0xd1a86e3f, 0x0707, 0x4c35, { 0x83, = 0xcd, 0xdc, 0x2c, 0x29, 0xc8, 0x91, 0xa3 } } + # # GUID defined in UniversalPayload # diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc index 659482ab737f..4142e1178dcd 100644 --- a/MdeModulePkg/MdeModulePkg.dsc +++ b/MdeModulePkg/MdeModulePkg.dsc @@ -104,6 +104,7 @@ [LibraryClasses] VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibN= ull.inf VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + NvVarStoreFormattedLib|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVar= StoreFormattedLib.inf =20 [LibraryClasses.EBC.PEIM] IoLib|MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf @@ -443,6 +444,7 @@ [Components] MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.i= nf + MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf =20 [Components.IA32, Components.X64, Components.AARCH64] MdeModulePkg/Universal/EbcDxe/EbcDxe.inf diff --git a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLi= b.inf similarity index 96% rename from EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf rename to MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLi= b.inf index e2eed26c5b2d..5e8cd94cc9e0 100644 --- a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf +++ b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf @@ -32,7 +32,6 @@ [Sources] NvVarStoreFormattedLib.c =20 [Packages] - EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec =20 diff --git a/EmbeddedPkg/Include/Guid/NvVarStoreFormatted.h b/MdeModulePkg/= Include/Guid/NvVarStoreFormatted.h similarity index 100% rename from EmbeddedPkg/Include/Guid/NvVarStoreFormatted.h rename to MdeModulePkg/Include/Guid/NvVarStoreFormatted.h diff --git a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.c b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c similarity index 100% rename from EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.c rename to MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLi= b.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97451): https://edk2.groups.io/g/devel/message/97451 Mute This Topic: https://groups.io/mt/95687633/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97452+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97452+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109028; cv=none; d=zohomail.com; s=zohoarc; b=KZDX3JtMinGE3wxS7m2Rg1oP7yktS78QxXKA/c0rZXyoAM+3YL1/tQhcLAEnX+v+fObF99kGhCWEP55VzQF77/PpHowo0QodTlAQPiqVSfkpGtSRblO2goXXakGcD2GfupOEoNhvcFzHjFXbPPplAi3OMZ3ueJJ5O+eGr1KSaOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109028; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kAJXDd+LaRloCcE8/cWpMJMT4FmUYlu71Q6ypjZQeEU=; b=T9j2Wx0rzKo2FQ5gs/ZHVEuIHk+LYYlefEnPH9KwG4gErA/213NHjt1fitTdYtHf4TazcaIDi3Gt9znqf5oFR05phT31U1TSckGdZA0xKMsIFgIqzSGXAE/HT4r/PQq9RvUUvSsF+QTkzMfMS9Jg6ToKdzBoxsJJnp/o9DGOlvk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97452+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109028159760.8800378043558; Thu, 15 Dec 2022 04:57:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1Q3EYY1788612xQzh08mEHjl; Thu, 15 Dec 2022 04:57:07 -0800 X-Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web11.132929.1671109026861172153 for ; Thu, 15 Dec 2022 04:57:06 -0800 X-Received: by mail-pg1-f169.google.com with SMTP id 62so4078394pgb.13 for ; Thu, 15 Dec 2022 04:57:06 -0800 (PST) X-Gm-Message-State: NCWJVsUNMjbpNmDjdxbTgSELx1787277AA= X-Google-Smtp-Source: AA0mqf4Gr9A4CsNZ0d4KRNBDPO9iyRGoKCE9hLle3+QldrPme9tKii6FngS8zp8hoTlYVihFcpLgpw== X-Received: by 2002:a62:1a8a:0:b0:56e:9a2c:152b with SMTP id a132-20020a621a8a000000b0056e9a2c152bmr28304580pfa.24.1671109026202; Thu, 15 Dec 2022 04:57:06 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:05 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 12/23] ArmVirtPkg: Update the references to NvVarStoreFormattedLib Date: Thu, 15 Dec 2022 18:26:15 +0530 Message-Id: <20221215125626.545372-13-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109027; bh=6IcBsjstVuwh9sleErlcM5/uqtyYd7dZEYcRtRbA6g0=; h=Cc:Date:From:Reply-To:Subject:To; b=hTuVnl9cTyaAXKNeteLJ5X+/nJ5S8rsxSeni8AihgK4T8Jb/EpqSuW0qmPFitoNelpT sFckVCtl+0t8q95XOGG6glrMVRQD10Te1sdgZ9aSPbxO55LPD3OJ0up7kzktDaJSpq6gC hIgAKgFyTlYPVVHKyDlINZRIyEL/AXkk3Gw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109029426100005 Content-Type: text/plain; charset="utf-8" The NvVarStoreFormattedLib library is moved to MdeModulePkg. So, updates its users with the new location. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- ArmVirtPkg/ArmVirtKvmTool.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 2 +- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc index 2ba00bd08ff1..6aee7e208154 100644 --- a/ArmVirtPkg/ArmVirtKvmTool.dsc +++ b/ArmVirtPkg/ArmVirtKvmTool.dsc @@ -263,7 +263,7 @@ [Components.common] MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } =20 diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index f77443229e8e..f5bc6a3f321d 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -383,7 +383,7 @@ [Components.common] MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index f5db3ac432f3..20e735dc5808 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -294,7 +294,7 @@ [Components.common] MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97452): https://edk2.groups.io/g/devel/message/97452 Mute This Topic: https://groups.io/mt/95687634/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97453+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97453+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109030; cv=none; d=zohomail.com; s=zohoarc; b=Jda6lvn/LhSpnCW6abS28QtVsYXpHmNVxPP/JOkIet8PmBIynfWgdeioz4clrsZmtTJ2DxN2U2Km+wolrULo+7fHF1vIq4ERb6ptNNbjKMZr1l5Ps6fP75Pg5fxz63i3eS1dsQ93n8EKcL9/q3fGZ/bgZ8fxz5CjaEmtpeQwJjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109030; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=P5ECRxKsIBWtH9tFfz1gGLgSxpFWFkV9nEIg59TRLyU=; b=cd6PZ3oS3mN0NNOnH34dZva0xVB3bqKvpaKQWNzAf9VJ3gfsUd9GkNnkDrOmGyUoAbMXVHeV6hOiRfPcsWBkxlpnkMdyqnVXG8Y5dv08wypAlWkietf7v1IQZIzDwkKZMlyScXLEX3GS0yOibW0TbyX8BsJasV/HmhdugVv7osg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97453+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109030774825.6277117570185; Thu, 15 Dec 2022 04:57:10 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4W2yYY1788612xP4OqeyRJoz; Thu, 15 Dec 2022 04:57:10 -0800 X-Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) by mx.groups.io with SMTP id smtpd.web11.132930.1671109029337538238 for ; Thu, 15 Dec 2022 04:57:09 -0800 X-Received: by mail-pg1-f173.google.com with SMTP id 82so4134987pgc.0 for ; Thu, 15 Dec 2022 04:57:09 -0800 (PST) X-Gm-Message-State: 5VoAggXrUDrvrGIjyzaLqjaxx1787277AA= X-Google-Smtp-Source: AA0mqf4G51tJoQR8VHrEbT3BiWaChbh7mExthW0O3lv8Qq0z+NiQU8eAfNBpYuaK3j6IA59o2cjvHQ== X-Received: by 2002:aa7:8818:0:b0:577:9807:543b with SMTP id c24-20020aa78818000000b005779807543bmr28779160pfo.16.1671109028503; Thu, 15 Dec 2022 04:57:08 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:08 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 13/23] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Date: Thu, 15 Dec 2022 18:26:16 +0530 Message-Id: <20221215125626.545372-14-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109030; bh=0hSHHTWYv/zXv6kWXgnTTPLJc6RbQ2AVgId6do8dOKo=; h=Cc:Date:From:Reply-To:Subject:To; b=mgG0WS/0TtVcFuYlZnhbyZ31nkdAWrwaF5jKCSzA777ZtBV3ow7JBc5YGzq0sL/SUon bNHbb/CdyoQTW8N/+5Vlq8TGMNsG9pRK7SpjzZZ1T6OpwSgTREPiNyG9ytX7bu3o6PUrW 8chE7lPTSTxvyt0vkXLYme2K2/xumHWMyJc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109031439100010 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This module is required by other architectures like RISC-V. Hence, move this to OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- ArmVirtPkg/ArmVirtPkg.dec | 9 = --------- OvmfPkg/OvmfPkg.dec | 7 = +++++++ {ArmVirtPkg =3D> OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf | = 3 +-- {ArmVirtPkg =3D> OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c | 0 4 files changed, 8 insertions(+), 11 deletions(-) diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec index 89d21ec3a364..4645c91a8375 100644 --- a/ArmVirtPkg/ArmVirtPkg.dec +++ b/ArmVirtPkg/ArmVirtPkg.dec @@ -34,8 +34,6 @@ [Guids.common] gEarly16550UartBaseAddressGuid =3D { 0xea67ca3e, 0x1f54, 0x436b, { 0x9= 7, 0x88, 0xd4, 0xeb, 0x29, 0xc3, 0x42, 0x67 } } gArmVirtSystemMemorySizeGuid =3D { 0x504eccb9, 0x1bf0, 0x4420, { 0x8= 6, 0x5d, 0xdc, 0x66, 0x06, 0xd4, 0x13, 0xbf } } =20 - gArmVirtVariableGuid =3D { 0x50bea1e5, 0xa2c5, 0x46e9, { 0x9b, 0x3a, 0= x59, 0x59, 0x65, 0x16, 0xb0, 0x0a } } - [PcdsFeatureFlag] # # Feature Flag PCD that defines whether TPM2 support is enabled @@ -69,10 +67,3 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # Cloud Hypervisor has no other way to pass Rsdp address to the guest ex= cept use a PCD. # gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x000000= 05 - -[PcdsDynamic] - # - # Whether to force disable ACPI, regardless of the fw_cfg settings - # exposed by QEMU - # - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x00000003 diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 5f5556c67c6c..7df05770b5d6 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -151,6 +151,7 @@ [Guids] gConfidentialComputingSevSnpBlobGuid =3D {0x067b1f5f, 0xcf26, 0x44c5, {= 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}} gUefiOvmfPkgPlatformInfoGuid =3D {0xdec9b486, 0x1f16, 0x47c7, {= 0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}} gVMMBootOrderGuid =3D {0x668f4529, 0x63d0, 0x4bb5, {= 0xb6, 0x5d, 0x6f, 0xbb, 0x9d, 0x36, 0xa4, 0x4a}} + gOvmfVariableGuid =3D {0x50bea1e5, 0xa2c5, 0x46e9, {= 0x9b, 0x3a, 0x59, 0x59, 0x65, 0x16, 0xb0, 0x0a}} =20 [Ppis] # PPI whose presence in the PPI database signals that the TPM base addre= ss @@ -460,6 +461,12 @@ [PcdsDynamic, PcdsDynamicEx] ## This PCD records LASA field in CC EVENTLOG ACPI table. gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLasa|0|UINT64|0x67 =20 + # + # Whether to force disable ACPI, regardless of the fw_cfg settings + # exposed by QEMU + # + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69 + [PcdsFeatureFlag] gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf b/Ovm= fPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf similarity index 89% rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf index e900aa992661..85873f73b2eb 100644 --- a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf +++ b/OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf @@ -19,7 +19,6 @@ [Sources] PlatformHasAcpiDtDxe.c =20 [Packages] - ArmVirtPkg/ArmVirtPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -38,7 +37,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] gEfiVariableArchProtocolGuid diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c b/OvmfP= kg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c similarity index 100% rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97453): https://edk2.groups.io/g/devel/message/97453 Mute This Topic: https://groups.io/mt/95687635/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97454+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97454+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109032; cv=none; d=zohomail.com; s=zohoarc; b=PoGpPYvpRB4iGGRv2beZl2YSN/8uc4B7gS+nR3eF6UAk8y8a2kPNi5q+YYqZuSbMx4iG6HBicgY24QoqtHuRIQGRShHyBgZk8CyV73z+yCP2giRC6vy+KTSLXF0TG/jCpqmEL5UtGYRW8+chZMX9RJxcTXxGBkdO/kYDDic6g6c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109032; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=G2tGVRlFd/XycJZZmp9ZDv/viDuRqohn0fv4Lyr/JYw=; b=aOPSV+K2Qq8BNw6BVqTvoyxnn3sMdX6LNbMSqlsJ5CHTqOB/ZCA0i8/ykNh5sk+PBujn3U2lJoHKnK9xkdrN9K8fR23p6UwQL20cbanlfzn/zZIMblfjpZNgjai3+rZpw6caX5IiHwCiAgbGEmeRewg1glpKz1zvUTcNtAA878g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97454+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109032323468.99536756181806; Thu, 15 Dec 2022 04:57:12 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1DLfYY1788612xNynZkNVd5a; Thu, 15 Dec 2022 04:57:12 -0800 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web10.132060.1671109008930741457 for ; Thu, 15 Dec 2022 04:57:11 -0800 X-Received: by mail-pf1-f176.google.com with SMTP id t18so6606142pfq.13 for ; Thu, 15 Dec 2022 04:57:11 -0800 (PST) X-Gm-Message-State: DYh81Oku6Z2d8m9yPvZKXk4Bx1787277AA= X-Google-Smtp-Source: AA0mqf5847rdwZSY3anLHnj6ogtJotv9+/JV3T8Kja0gocmPctMB2hBQNdqvUz0a6LukNtrhZ+wzxw== X-Received: by 2002:a05:6a00:26f7:b0:577:5913:5b25 with SMTP id p55-20020a056a0026f700b0057759135b25mr29601318pfw.22.1671109031029; Thu, 15 Dec 2022 04:57:11 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:10 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 14/23] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe Date: Thu, 15 Dec 2022 18:26:17 +0530 Message-Id: <20221215125626.545372-15-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109032; bh=BETFcJ3T9xCWa1fyv/bOLLO3iqkah3nY5LRXIhJ+wQQ=; h=Cc:Date:From:Reply-To:Subject:To; b=PL0s3C8bEaGnNFXHcjnvLCP71wmrA1xnjGlQ9leSVBXrhavxLChfhDpP/8+yYMWynL8 YFss/W1huMBw7dWhuGktssHa2JuNsKfxfVPwj+yL/EeR2v1amDKLaZECLsiVd/bniroC1 PdKQaqH9KOj/QGjE8oVvDNZhlek8kRekGrU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109033452100013 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 PlatformHasAcpiDtDxe is required by other architectures also. Hence, it is moved to OvmfPkg. So, update the consumers of this module with the new location. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 4 ++-- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf | 2 +- ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 2 +- ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc index 7ca7a391d9cf..c975e139a216 100644 --- a/ArmVirtPkg/ArmVirtCloudHv.dsc +++ b/ArmVirtPkg/ArmVirtCloudHv.dsc @@ -198,7 +198,7 @@ [PcdsDynamicDefault.common] gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 =20 [PcdsDynamicHii] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGui= d|0x0|FALSE|NV,BS + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS =20 ##########################################################################= ###### # diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index f5bc6a3f321d..0390b660c0a8 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -300,7 +300,7 @@ [PcdsPatchableInModule] !endif =20 [PcdsDynamicHii] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGui= d|0x0|FALSE|NV,BS + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS =20 !if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS @@ -569,7 +569,7 @@ [Components.common] # # ACPI Support # - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf [Components.AARCH64] MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index 20e735dc5808..f3fd04ffd978 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -457,7 +457,7 @@ [Components.common] # # ACPI Support # - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf [Components.AARCH64] MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { diff --git a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf= b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf index 4af06b2a6746..7cad40e11f33 100644 --- a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf +++ b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf @@ -36,7 +36,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] gEfiVariableArchProtocolGuid diff --git a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf b/ArmVirt= Pkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf index 1cf25780f830..5888fcdc0b26 100644 --- a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf +++ b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf @@ -37,7 +37,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] TRUE diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuF= vMain.fdf.inc index e06ca7424476..8a063bac04ac 100644 --- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc +++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc @@ -141,7 +141,7 @@ [FV.FvMain] # # ACPI Support # - INF ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf !if $(ARCH) =3D=3D AARCH64 INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97454): https://edk2.groups.io/g/devel/message/97454 Mute This Topic: https://groups.io/mt/95687636/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97455+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97455+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109035; cv=none; d=zohomail.com; s=zohoarc; b=i2EcMzPdhMiBY7pBv5XnJqmCXJCIUucbzETrd42vqRmbPG7e9Hq+pxBvhc+2LA2WQlCugPZgqMPvAPAQzdpfx+Dbad5/jToodgeYNTjk0CqHlSrjzTstnjPo6OyBD8HJY8ugyU7qKKruCtYrqp/Xuc9iDepADum0lSdN+VkY/10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109035; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=UVr3WkSBwS7bmPxcnw36y+XosoXoAHzBs89yOhi4Y8w=; b=S3X3rR0yCjIX/oZpghrul45n4/zjR8T0aNzn5rLpZraAXcDizDXqIjOzzAXLBH10dk75b9rVvT+5Qf3/0/V1gQMg/2wJMMCUEf4+lrxM++irxcx8OfmjWi+PQ2/+BMAqcLQYkT6k57kfRlwGqHVDj+738669Q8qXU4wRdy6BSCo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97455+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109035740501.26368174375307; Thu, 15 Dec 2022 04:57:15 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id hE1IYY1788612xTEr04PIRDg; Thu, 15 Dec 2022 04:57:15 -0800 X-Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) by mx.groups.io with SMTP id smtpd.web10.132073.1671109034775127028 for ; Thu, 15 Dec 2022 04:57:14 -0800 X-Received: by mail-pf1-f170.google.com with SMTP id 130so6626732pfu.8 for ; Thu, 15 Dec 2022 04:57:14 -0800 (PST) X-Gm-Message-State: hUGv1LTBsoxMJoeAPuAjJu7Fx1787277AA= X-Google-Smtp-Source: AA0mqf7mcCtnqe3CmieJxtvTzlVrRUNkops2KsoX6pk4UIsUMiZ0oQewZiHtnVQusxpxoRhlhxc6aA== X-Received: by 2002:a62:17d5:0:b0:577:2a9:ec82 with SMTP id 204-20020a6217d5000000b0057702a9ec82mr25937373pfx.5.1671109033936; Thu, 15 Dec 2022 04:57:13 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:13 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 15/23] OvmfPkg: Add VirtNorFlashPlatformLib library Date: Thu, 15 Dec 2022 18:26:18 +0530 Message-Id: <20221215125626.545372-16-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109035; bh=35kLxscwt4pXtBE1cB4bRQQvtL2zxOT1T9eY4/k4Rfc=; h=Cc:Date:From:Reply-To:Subject:To; b=M9M5gynD1A9gXJogr2VdHw5Wu4wCgZdYoqp1iqbcmpjsHTao8xK41JIU1Pkh00FPPsb qvKnTPx6G9QcVtwI1VAzdtOZ8zeRCjP6BSIZKwoasLE8jMZ7qYlKW6uG/tUZ79Ice/sHq w3gZcPxdPM1hm46zhZ31gPPUENkzzs2mpaA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109037495100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add the VirtNorFlashPlatformLib library for qemu virt machines. Add two instances of the library. One which uses DT information and the other which is static. They are copied from ArmVirtPkg and SbsaQemu. Two PCD variables used by the library are added in the OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- OvmfPkg/OvmfPkg.dec | = 4 + OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf | 4= 0 ++++++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf | 3= 0 +++++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c | 13= 6 ++++++++++++++++++++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 4= 0 ++++++ 5 files changed, 250 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 7df05770b5d6..7e1c2fc42412 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -409,6 +409,10 @@ [PcdsFixedAtBuild] # check to decide whether to abort dispatch of the driver it is linked = into. gUefiOvmfPkgTokenSpaceGuid.PcdEntryPointOverrideFwCfgVarName|""|VOID*|0x= 68 =20 + ## The base address and size of the FVMAIN + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress|0|UINT64|0x71 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize|0|UINT32|0x72 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTree= Lib.inf b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib= .inf new file mode 100644 index 000000000000..5b7a45d15782 --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf @@ -0,0 +1,40 @@ +#/** @file +# +# Component description file for VirtNorFlashDeviceTreeLib module +# +# Copyright (c) 2014, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VirtNorFlashDeviceTreeLib + FILE_GUID =3D 42C30D8E-BFAD-4E77-9041-E7DAAE88DF7A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VirtNorFlashPlatformLib + +[Sources.common] + VirtNorFlashDeviceTreeLib.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + +[Protocols] + gFdtClientProtocolGuid ## CONSUMES + +[Depex] + gFdtClientProtocolGuid + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.= inf b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf new file mode 100644 index 000000000000..4e87bd437380 --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf @@ -0,0 +1,30 @@ +#/** @file +# +# Component description file for VirtNorFlashStaticLib module +# +# Copyright (c) 2014, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VirtNorFlashStaticLib + FILE_GUID =3D 064742F1-E531-4D7D-A154-22315889CC23 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VirtNorFlashPlatformLib + +[Sources.common] + VirtNorFlashStaticLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTree= Lib.c b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c new file mode 100644 index 000000000000..08750e66095d --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c @@ -0,0 +1,136 @@ +/** @file + + Copyright (c) 2014-2018, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include +#include + +#include + +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB + +#define MAX_FLASH_BANKS 4 + +EFI_STATUS +VirtNorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevices[MAX_FLASH_BANKS]; + +EFI_STATUS +VirtNorFlashPlatformGetDevices ( + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + FDT_CLIENT_PROTOCOL *FdtClient; + INT32 Node; + EFI_STATUS Status; + EFI_STATUS FindNodeStatus; + CONST UINT32 *Reg; + UINT32 PropSize; + UINT32 Num; + UINT64 Base; + UINT64 Size; + + Status =3D gBS->LocateProtocol ( + &gFdtClientProtocolGuid, + NULL, + (VOID **)&FdtClient + ); + ASSERT_EFI_ERROR (Status); + + Num =3D 0; + for (FindNodeStatus =3D FdtClient->FindCompatibleNode ( + FdtClient, + "cfi-flash", + &Node + ); + !EFI_ERROR (FindNodeStatus) && Num < MAX_FLASH_BANKS; + FindNodeStatus =3D FdtClient->FindNextCompatibleNode ( + FdtClient, + "cfi-flash", + Node, + &Node + )) + { + Status =3D FdtClient->GetNodeProperty ( + FdtClient, + Node, + "reg", + (CONST VOID **)&Reg, + &PropSize + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: GetNodeProperty () failed (Status =3D=3D %r)\n", + __FUNCTION__, + Status + )); + continue; + } + + ASSERT ((PropSize % (4 * sizeof (UINT32))) =3D=3D 0); + + while (PropSize >=3D (4 * sizeof (UINT32)) && Num < MAX_FLASH_BANKS) { + Base =3D SwapBytes64 (ReadUnaligned64 ((VOID *)&Reg[0])); + Size =3D SwapBytes64 (ReadUnaligned64 ((VOID *)&Reg[2])); + Reg +=3D 4; + + PropSize -=3D 4 * sizeof (UINT32); + + // + // Disregard any flash devices that overlap with the primary FV. + // The firmware is not updatable from inside the guest anyway. + // + if ((PcdGet64 (PcdOvmfFvBaseAddress) + PcdGet32 (PcdOvmfFvSize) > Ba= se) && + ((Base + Size) > PcdGet64 (PcdOvmfFvBaseAddress))) + { + continue; + } + + mNorFlashDevices[Num].DeviceBaseAddress =3D (UINTN)Base; + mNorFlashDevices[Num].RegionBaseAddress =3D (UINTN)Base; + mNorFlashDevices[Num].Size =3D (UINTN)Size; + mNorFlashDevices[Num].BlockSize =3D QEMU_NOR_BLOCK_SIZE; + Num++; + } + + // + // UEFI takes ownership of the NOR flash, and exposes its functionality + // through the UEFI Runtime Services GetVariable, SetVariable, etc. Th= is + // means we need to disable it in the device tree to prevent the OS fr= om + // attaching its device driver as well. + // Note that this also hides other flash banks, but the only other fla= sh + // bank we expect to encounter is the one that carries the UEFI execut= able + // code, which is not intended to be guest updatable, and is usually b= acked + // in a readonly manner by QEMU anyway. + // + Status =3D FdtClient->SetNodeProperty ( + FdtClient, + Node, + "status", + "disabled", + sizeof ("disabled") + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "Failed to set NOR flash status to 'disabled'\n"= )); + } + } + + *NorFlashDescriptions =3D mNorFlashDevices; + *Count =3D Num; + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.= c b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c new file mode 100644 index 000000000000..fdc2ccb6294e --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Linaro Ltd. All rights reserved + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include + +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB + +EFI_STATUS +VirtNorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =3D +{ + FixedPcdGet32 (PcdOvmfFdBaseAddress), + FixedPcdGet64 (PcdFlashNvStorageVariableBase), + FixedPcdGet32 (PcdOvmfFirmwareFdSize), + QEMU_NOR_BLOCK_SIZE +}; + +EFI_STATUS +VirtNorFlashPlatformGetDevices ( + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + *NorFlashDescriptions =3D &mNorFlashDevice; + *Count =3D 1; + return EFI_SUCCESS; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97455): https://edk2.groups.io/g/devel/message/97455 Mute This Topic: https://groups.io/mt/95687640/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97456+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97456+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109038; cv=none; d=zohomail.com; s=zohoarc; b=jhf+rcmeeugqZhUMzw4KUDiqhTt+UtR+ZGCdDiYaHM4dBaKD/gfaCcHAcXN1EKNLPrkwwKdwCVePuY7uLcrA1jc0HahD3tx1QwzoiYSVl4ctpY5D/4BilHljzoPMlZSoWrx3YQwz74pI+xZUe6kVSijij1y552+TcZnBsqrKSU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109038; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kSZuxK4MgPHvcTVrqTgmG3pEqtzG2LO8mKx0u8VDNaU=; b=IWa+EfOhDLhLbZ0QjxFZK37cRSow6PDAlkAl7kuB8g6PKQkhmXVLHCEzXN7t9oHCcWmgzQBJTkh4XG6fYpUxRdw0kz3X1q+U9KEmJ7eklSleN40XI8tCCkoCgTsXml9eYadsFifSYIYY4/oykiV9tUc87yhSR2kUuhRMnBllalw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97456+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109038725656.5750140374267; Thu, 15 Dec 2022 04:57:18 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id n8d7YY1788612xeyCncfe5DR; Thu, 15 Dec 2022 04:57:17 -0800 X-Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by mx.groups.io with SMTP id smtpd.web11.132934.1671109037322333443 for ; Thu, 15 Dec 2022 04:57:17 -0800 X-Received: by mail-pf1-f182.google.com with SMTP id a14so6646800pfa.1 for ; Thu, 15 Dec 2022 04:57:17 -0800 (PST) X-Gm-Message-State: np9D8v4W5UmSOqXN767vBTOfx1787277AA= X-Google-Smtp-Source: AA0mqf4ZwEl0l9cpi2HYxDebQnxcPLUwVccJsRST9dzik7E0AizTCpbSku849FNg/tpTNsWkff6wBg== X-Received: by 2002:a05:6a00:1513:b0:576:f7bd:92d4 with SMTP id q19-20020a056a00151300b00576f7bd92d4mr37604277pfu.30.1671109036403; Thu, 15 Dec 2022 04:57:16 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:16 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 16/23] OvmfPkg/PlatformInitLib: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:19 +0530 Message-Id: <20221215125626.545372-17-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109037; bh=GiyfriSa/DkFS8TL65nv4LfVu2ZEd05OiZFiIsf5GdQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ombn81kj/uXfX5Qu9lzj2g18LoZ0n7pHW9FgtU1LNku5nUV7Y3LL7BLPHYUh1eCZOUl eXE71gwHEM1RG5ksbyRuoVgPWIbz/+396GAId6H5n7zT4t/bYpGkqp+/I1tuhZPevyjui qJgMmtv3KP3KU0kWyo+8nICYsYgsLS4ThKA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109039499100006 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is copied from edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/FdtPeim but added as part of library instead of a separate module. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitLib.inf | 51 ++++ OvmfPkg/Include/Library/PlatformInitLib.h | 39 +++ OvmfPkg/Library/PlatformInitLib/RiscV64/Cpu.c | 33 +++ OvmfPkg/Library/PlatformInitLib/RiscV64/Memory.c | 263 +++++= +++++++++++++++ OvmfPkg/Library/PlatformInitLib/RiscV64/Platform.c | 83 ++++++ 5 files changed, 469 insertions(+) diff --git a/OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitLib.inf= b/OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitLib.inf new file mode 100644 index 000000000000..323e9b17970f --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitLib.inf @@ -0,0 +1,51 @@ +## @file +# Platform Initialization Lib for RISC-V +# +# This module provides platform specific functions for RISC-V. +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseRiscV64PlatformInitLib + FILE_GUID =3D 0D1B3448-4D8E-44EE-80C9-907443047F79 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformInitLib|SEC PEIM + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/Platform.c + RiscV64/Cpu.c + RiscV64/Memory.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + IoLib + HobLib + RiscVSbiLib + FdtLib + MemoryAllocationLib + +[Guids] + gFdtHobGuid + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index bf6f90a5761c..09fe1d9bf2c0 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -291,4 +291,43 @@ PlatformInitEmuVariableNvStore ( IN VOID *EmuVariableNvStore ); =20 +/** + Perform Platform PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ); + +/** + Perform Memory PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +MemoryPeimInitialization ( + VOID + ); + +/** + Perform CPU PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +CpuPeimInitialization ( + VOID + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/RiscV64/Cpu.c b/OvmfPkg/Librar= y/PlatformInitLib/RiscV64/Cpu.c new file mode 100644 index 000000000000..2c16df697e37 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/RiscV64/Cpu.c @@ -0,0 +1,33 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include + +/** + Cpu Peim initialization. + +**/ +EFI_STATUS +CpuPeimInitialization ( + VOID + ) +{ + // + // for MMU type >=3D sv39 + // + BuildCpuHob (56, 32); + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/PlatformInitLib/RiscV64/Memory.c b/OvmfPkg/Lib= rary/PlatformInitLib/RiscV64/Memory.c new file mode 100644 index 000000000000..70935b07b56b --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/RiscV64/Memory.c @@ -0,0 +1,263 @@ +/** @file + Memory Detection for Virtual Machines. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +/** + Build reserved memory range resource HOB. + + @param MemoryBase Reserved memory range base address. + @param MemorySize Reserved memory range size. + +**/ +STATIC +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +STATIC +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +STATIC +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Configure MMU +**/ +STATIC +VOID +InitMmu ( + ) +{ + // + // Set supervisor translation mode to Bare mode + // + RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 6= 0); + DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.= \n", __FUNCTION__)); +} + +/** + Publish system RAM and reserve memory regions. + +**/ +STATIC +VOID +InitializeRamRegions ( + EFI_PHYSICAL_ADDRESS SystemMemoryBase, + UINT64 SystemMemorySize, + EFI_PHYSICAL_ADDRESS MmodeResvBase, + UINT64 MmodeResvSize + ) +{ + /* + * M-mode FW can be loaded anywhere in memory but should not overlap + * with the EDK2. This can happen if some other boot code loads the + * M-mode firmware. + * + * The M-mode firmware memory should be marked as reserved memory + * so that OS doesn't use it. + */ + DEBUG (( + DEBUG_INFO, + "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, + MmodeResvBase, + MmodeResvBase + MmodeResvSize + )); + AddReservedMemoryBaseSizeHob (MmodeResvBase, MmodeResvSize); + + if (MmodeResvBase > SystemMemoryBase) { + AddMemoryRangeHob (SystemMemoryBase, MmodeResvBase); + } + + AddMemoryRangeHob ( + MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize + ); +} + +/** + Initialize memory hob based on the DTB information. + + @return EFI_SUCCESS The memory hob added successfully. + +**/ +EFI_STATUS +MemoryPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + UINT64 CurBase, CurSize; + INT32 Node, Prev; + INT32 Len; + VOID *FdtPointer; + EFI_PHYSICAL_ADDRESS MmodeResvBase; + UINT64 MmodeResvSize; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + /* try to locate the reserved memory opensbi node */ + Node =3D fdt_path_offset (FdtPointer, "/reserved-memory/mmode_resv0"); + if (Node >=3D 0) { + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + MmodeResvBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + MmodeResvSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + } + } + + // Look for the lowest memory node + for (Prev =3D 0; ; Prev =3D Node) { + Node =3D fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + + // Check for memory node + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG (( + DEBUG_INFO, + "%a: System RAM @ 0x%lx - 0x%lx\n", + __FUNCTION__, + CurBase, + CurBase + CurSize - 1 + )); + + if ((MmodeResvBase >=3D CurBase) && ((MmodeResvBase + MmodeResvSiz= e) <=3D (CurBase + CurSize))) { + InitializeRamRegions ( + CurBase, + CurSize, + MmodeResvBase, + MmodeResvSize + ); + } else { + AddMemoryBaseSizeHob (CurBase, CurSize); + } + } else { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to parse FDT memory node\n", + __FUNCTION__ + )); + } + } + } + + InitMmu (); + + BuildMemoryTypeInformationHob (); + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/PlatformInitLib/RiscV64/Platform.c b/OvmfPkg/L= ibrary/PlatformInitLib/RiscV64/Platform.c new file mode 100644 index 000000000000..1556d26426c2 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/RiscV64/Platform.c @@ -0,0 +1,83 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include +#include +#include +#include +#include +#include + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUN= CTION__, FdtPointer)); + Base =3D FdtPointer; + if (fdt_check_header (Base) !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + if (NewBase =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n", __FUNC= TION__)); + return EFI_UNSUPPORTED; + } + + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + if (FdtHobData =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + *FdtHobData =3D (UINTN)NewBase; + + BuildFvHob (PcdGet64 (PcdOvmfFvBaseAddress), PcdGet32 (PcdOvmfFvSize)); + + return EFI_SUCCESS; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97456): https://edk2.groups.io/g/devel/message/97456 Mute This Topic: https://groups.io/mt/95687641/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97457+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97457+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109040; cv=none; d=zohomail.com; s=zohoarc; b=OuyOyZ4V/jzNY8LuchWD0CwSJVZGV9EhmA0F+AA31GvXO4p7cMtTu091H459XUtXUEtQHAHtXcFHYiPaDZKigOiGWYnB8jypGe/f8Bm+N069ZOr3lBr9VW2E/EbX49R5gy55MqUxCOJle5Bz88orxmQAJx4aBZxHPAPFkG2QdDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109040; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vYZ5G0d7G8tDn2xCRhl4L0mrXtTo4lXQ1UC022cpeX8=; b=C3VGyRwBNEV+3L2OoauN6qJjM3G9eMbcDXIFy4mnH6jJp5I6gUjXPhG4Gk+aMtm3nCFOrnnvkByjxU9+t79Q7cmqXjO5RjG3CsKsxZbWg3o04OjVpmXVSDDazHFZKvCg8FbGXQ50n7RHaNqXBTM6cGB9Rt+70bHmJWKIwQ9p/uQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97457+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109040213522.5837020297155; Thu, 15 Dec 2022 04:57:20 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id HZVsYY1788612xb3PWsRtzSX; Thu, 15 Dec 2022 04:57:19 -0800 X-Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web10.132065.1671109016309471170 for ; Thu, 15 Dec 2022 04:57:19 -0800 X-Received: by mail-pf1-f172.google.com with SMTP id g1so6647605pfk.2 for ; Thu, 15 Dec 2022 04:57:19 -0800 (PST) X-Gm-Message-State: ieapj8NcoHr43MR1YDWFP3xOx1787277AA= X-Google-Smtp-Source: AA0mqf6Yb4HosE9qsgq748RgyflZsOSe1XCLUpj38ekxXBgNWYVXK9KiKv2oQlMTJBgGVqLrBI/4Kg== X-Received: by 2002:a05:6a00:1c95:b0:578:8864:b25c with SMTP id y21-20020a056a001c9500b005788864b25cmr14915225pfw.25.1671109038916; Thu, 15 Dec 2022 04:57:18 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:18 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 17/23] OvmfPkg: Add PrePiHobListPointerLib library Date: Thu, 15 Dec 2022 18:26:20 +0530 Message-Id: <20221215125626.545372-18-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109039; bh=0xiZfP0wKJWn3bf0PscTzW1mCRCfW94DqM5CUPVPjeE=; h=Cc:Date:From:Reply-To:Subject:To; b=fCgCRszBlAgLM8YlegfNzWqqZ0Khz75R0GyfSrMYi4cA2qT+YmnpFSqZTKxrmasCXQV S5gBJ0glXse8wiryTQ7MJko3nTAvyCxyHLLSc68jpzSNwKiobp5AiR5CkM2bZS98COPWq CQ7m6X8YuxawFxibBLJc/AjCIZomOtcu1mk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109041490100010 Content-Type: text/plain; charset="utf-8" This library is required to use the PEI less design for RISC-V qemu virt support. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf | 23 = +++++++ OvmfPkg/Library/PrePiHobListPointerLib/RiscV64/PrePiHobListPointer.c | 65 = ++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.= inf b/OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf new file mode 100644 index 000000000000..4105e60f59e1 --- /dev/null +++ b/OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf @@ -0,0 +1,23 @@ +#/** @file +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PrePiHobListPointerLib + FILE_GUID =3D E3FAFC60-758C-471B-A333-FE704A4C11B4 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PrePiHobListPointerLib + +[Sources.RISCV64] + RiscV64/PrePiHobListPointer.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + UefiCpuPkg/UefiCpuPkg.dec diff --git a/OvmfPkg/Library/PrePiHobListPointerLib/RiscV64/PrePiHobListPoi= nter.c b/OvmfPkg/Library/PrePiHobListPointerLib/RiscV64/PrePiHobListPointer= .c new file mode 100644 index 000000000000..a58b7aae6bee --- /dev/null +++ b/OvmfPkg/Library/PrePiHobListPointerLib/RiscV64/PrePiHobListPointer.c @@ -0,0 +1,65 @@ +/** @file +* +* Copyright (c) 2021, Intel Corporation. All rights reserved.
+* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +/** + Returns the pointer to the HOB list. + + This function returns the pointer to first HOB in the list. + + @return The pointer to the HOB list. + +**/ +VOID * +EFIAPI +PrePeiGetHobList ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return NULL; + } + + return (VOID *)FirmwareContext->PrePiHobList; +} + +/** + Updates the pointer to the HOB list. + + @param HobList Hob list pointer to store + +**/ +EFI_STATUS +EFIAPI +PrePeiSetHobList ( + IN VOID *HobList + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_NOT_READY; + } + + FirmwareContext->PrePiHobList =3D HobList; + return EFI_SUCCESS; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97457): https://edk2.groups.io/g/devel/message/97457 Mute This Topic: https://groups.io/mt/95687642/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97458+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97458+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109043; cv=none; d=zohomail.com; s=zohoarc; b=EcFkzWgFXQ9PgnCobNGnO+pa7exbzccIJz6q1l+UQkMoXtilML3GUGBEgc2tRwfzphkwMcj2LfjyFhn6skv56REDvr1r6KlD2GmxGLS3JEsycxr9ZdhGEYlrPldkxrQfBvQcfXMPcRPgBrCbF3jFVCGkfmz0eL8r1oVLnHz6aCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109043; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xFqay5Por2Ewbr+plU6E5I2S0E6mhs4liVrFkNehYHA=; b=AKtOx/0FwwsysQH9nAmowrmt1yUlswIsGmLAGp57oeHRD9wJMJxdy+M8jf5RNvWnDo+TN54i2VbNd+hVzoPFmHaZjghUnOyvJWOYkqEQMjbjOc847kvsbHiiwVkpw0+av0FC05wDhmNCZvYKfqtcy7eb+ct8BlphHWbl0ZjxiGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97458+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109043224613.2244189722791; Thu, 15 Dec 2022 04:57:23 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Dk1PYY1788612xzLgNtF4FpH; Thu, 15 Dec 2022 04:57:22 -0800 X-Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) by mx.groups.io with SMTP id smtpd.web11.132935.1671109042158146624 for ; Thu, 15 Dec 2022 04:57:22 -0800 X-Received: by mail-pf1-f173.google.com with SMTP id x66so6641503pfx.3 for ; Thu, 15 Dec 2022 04:57:22 -0800 (PST) X-Gm-Message-State: E0TW9mzSIv6ZDWTuYbdutW2Qx1787277AA= X-Google-Smtp-Source: AA0mqf4S29uuNyXGvCm2Tq/5AR+J/SpHDxpilzNc+Qw6KSjcDQB58snFImtU1oMjCETf553DDD1Z6w== X-Received: by 2002:a62:17c4:0:b0:578:43e3:f48e with SMTP id 187-20020a6217c4000000b0057843e3f48emr19312036pfx.16.1671109041199; Thu, 15 Dec 2022 04:57:21 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:20 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 18/23] OvmfPkg: Add PciCpuIo2Dxe driver Date: Thu, 15 Dec 2022 18:26:21 +0530 Message-Id: <20221215125626.545372-19-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109042; bh=cBMbdb1RjvZWAPlbks2UC7fnLDbT66cC8b/iF7cxRDA=; h=Cc:Date:From:Reply-To:Subject:To; b=fziwHssaUU8vILQPQGh3EcBMaql9RH8GpVh4pufYQ7qrpZtiKJj0i7lhInyipjTfkVa 4w8lwHpQjE28+IcV5Ifwct/C7cC+zKVT11qElux31K6pzjXtftFNFB61YdmUak/GOaOAw bVC6K0PWs/aOgk1ZXQTuwXNgE0dp34mpNc8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109043532100013 Content-Type: text/plain; charset="utf-8" Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL to add the translation for IO access. This is copied from ArmPciCpuIo2Dxe driver since this is required by others like RISC-V. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++ OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ++++++++++++++++++++ 2 files changed, 605 insertions(+) diff --git a/OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/OvmfPkg/PciCpuIo2Dxe/P= ciCpuIo2Dxe.inf new file mode 100644 index 000000000000..4f78cfa4067b --- /dev/null +++ b/OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf @@ -0,0 +1,48 @@ +## @file +# Produces the CPU I/O 2 Protocol by using the services of the I/O Librar= y. +# +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PciCpuIo2Dxe + FILE_GUID =3D 9BD3C765-2579-4CF0-9349-D77205565030 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciCpuIo2Initialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PciCpuIo2Dxe.c + +[Packages] + OvmfPkg/OvmfPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation + +[Protocols] + gEfiCpuIo2ProtocolGuid ## PRODUCES + +[Depex] + TRUE diff --git a/OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/OvmfPkg/PciCpuIo2Dxe/Pci= CpuIo2Dxe.c new file mode 100644 index 000000000000..f3bf07e63141 --- /dev/null +++ b/OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.c @@ -0,0 +1,557 @@ +/** @file + Produces the CPU I/O 2 Protocol. + +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include +#include + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Handle for the CPU I/O 2 Protocol +// +STATIC EFI_HANDLE mHandle =3D NULL; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mInStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 0, // EfiCpuIoWidthFifoUint8 + 0, // EfiCpuIoWidthFifoUint16 + 0, // EfiCpuIoWidthFifoUint32 + 0, // EfiCpuIoWidthFifoUint64 + 1, // EfiCpuIoWidthFillUint8 + 2, // EfiCpuIoWidthFillUint16 + 4, // EfiCpuIoWidthFillUint32 + 8 // EfiCpuIoWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mOutStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 1, // EfiCpuIoWidthFifoUint8 + 2, // EfiCpuIoWidthFifoUint16 + 4, // EfiCpuIoWidthFifoUint32 + 8, // EfiCpuIoWidthFifoUint64 + 0, // EfiCpuIoWidthFillUint8 + 0, // EfiCpuIoWidthFillUint16 + 0, // EfiCpuIoWidthFillUint32 + 0 // EfiCpuIoWidthFillUint64 +}; + +/** + Check parameters to a CPU I/O 2 Protocol service request. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port= operation. + @param[in] Width Signifies the width of the I/O or Memory opera= tion. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The n= umber of + bytes moved is Width size * Count, starting at= Address. + @param[in] Buffer For read operations, the destination buffer to= store the results. + For write operations, the source buffer from w= hich to write data. + + @retval EFI_SUCCESS The parameters for this request pass the = checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >=3D EfiCpuIoWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if ((Width >=3D EfiCpuIoWidthFifoUint8) && (Width <=3D EfiCpuIoWidthFifo= Uint64)) { + Count =3D 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + return EFI_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the= maximum + // allowed address. The maximum address implied by the parameters passe= d in is + // Address + Size * Count. If the following condition is met, then the = transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_POR= T_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the C= PU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all overflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count =3D=3D 0) { + if (Address > Limit) { + return EFI_UNSUPPORTED; + } + } else { + MaxCount =3D RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return EFI_UNSUPPORTED; + } + + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return EFI_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != =3D 0) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Reads memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); + } + } + + return EFI_SUCCESS; +} + +/** + Writes memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + } + } + + return EFI_SUCCESS; +} + +/** + Reads I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address +=3D PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } + } + + return EFI_SUCCESS; +} + +/** + Write I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + // + // Make sure the parameters are valid + // + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address +=3D PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + + for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride, = Uint8Buffer +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } + } + + return EFI_SUCCESS; +} + +// +// CPU I/O 2 Protocol instance +// +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D { + { + CpuMemoryServiceRead, + CpuMemoryServiceWrite + }, + { + CpuIoServiceRead, + CpuIoServiceWrite + } +}; + +/** + The user Entry Point for module CpuIo2Dxe. The user code starts with thi= s function. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +PciCpuIo2Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mHandle, + &gEfiCpuIo2ProtocolGuid, + &mCpuIo2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97458): https://edk2.groups.io/g/devel/message/97458 Mute This Topic: https://groups.io/mt/95687643/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97459+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97459+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109045; cv=none; d=zohomail.com; s=zohoarc; b=LPH6n+jctNuxlRDVE5dRS15Z9g0/hAabz/hU8qiCPBpyF6JVJd2lxRKNnjJtHK3aTZSjzBTh5/xx+bYIzrySip1Q1AP3GJJzNgTIkoHnLeSyRJHSmibX6U3n6qdgurckCYp/uQSe0tTEC93RJXdYy3D5epnpY3722Sq7T1uS2Dk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109045; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jQuXRxmama3TrdbEmtcIwKUu+Ep/Y9ZUJLWv5d0Azd4=; b=Oehqh5Y4CO7nH06E4ZOw3/h2m3sWL0LTqkdO6VLu4mhmvnvqz8715/TNTKAKxd71apHI/gEhW3fDx1wVAHfnH6GJ4GDDj+loSbnQ8InEQoNoGxF4qdm/kcx+xsSc2yy7ytCzNuQIeMYrGtcW2P/2o221ARwYWz2F+Ld0TQZ+/KI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97459+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109045809646.9500648382358; Thu, 15 Dec 2022 04:57:25 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id LEFeYY1788612xFyfEnrfYFn; Thu, 15 Dec 2022 04:57:25 -0800 X-Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) by mx.groups.io with SMTP id smtpd.web11.132938.1671109045010538374 for ; Thu, 15 Dec 2022 04:57:25 -0800 X-Received: by mail-pf1-f173.google.com with SMTP id 21so6641721pfw.4 for ; Thu, 15 Dec 2022 04:57:24 -0800 (PST) X-Gm-Message-State: svTdzIamzHJx88lSEDHT6334x1787277AA= X-Google-Smtp-Source: AA0mqf4D3SVfC6cT8mmWk+0qZwjQe/aJARjnpMlpzrwa2E/R8+0MMeDEl5QQ8n5id2tba1GjkR02uQ== X-Received: by 2002:a05:6a00:1d09:b0:578:128b:3a3f with SMTP id a9-20020a056a001d0900b00578128b3a3fmr26769854pfx.15.1671109044325; Thu, 15 Dec 2022 04:57:24 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:23 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Rebecca Cran , Peter Grehan , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 19/23] OvmfPkg/ResetSystemLib: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:22 +0530 Message-Id: <20221215125626.545372-20-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109045; bh=dyT+Fer20C2HVcS1ipnYEL0oLz4IA3gE3zpKsnJ4/Ks=; h=Cc:Date:From:Reply-To:Subject:To; b=wr5vRRks2qaFuXLsQyvlQuMELoNMEA9UqnkUcwUuLfNFTmeS/1Q+lq/kM6/PW2fb6PM b8A5hAn4qG333EejuubIXOUyFkbm/65xdSav/x9/UQe2t7bYVEg8xYz1NCPQcmr3UNs6D bQ0YgfWb3Rpph9Vi0u9PHrHTG3mpeUUYd9c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109047507100018 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is mostly copied from edk2-platforms/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Rebecca Cran Cc: Peter Grehan Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.inf | 38 ++++++ OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c | 20 +++ OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c | 128 +++++++= +++++++++++++ 3 files changed, 186 insertions(+) diff --git a/OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.inf b= /OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.inf new file mode 100644 index 000000000000..f26ddf682625 --- /dev/null +++ b/OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.inf @@ -0,0 +1,38 @@ +## @file +# Base library instance for ResetSystem library class for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseRiscV64ResetSystemLib + FILE_GUID =3D AB45A200-769D-4C10-B0D6-5E1FF5EEBF31 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ResetSystemLib + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/ResetSystemLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + TimerLib + RiscVSbiLib diff --git a/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c b/Ov= mfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c new file mode 100644 index 000000000000..027e235cad11 --- /dev/null +++ b/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c @@ -0,0 +1,20 @@ +/** @file + DXE Reset System Library Shutdown API implementation for OVMF. + + Copyright (C) 2020, Red Hat, Inc. + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include // CpuDeadLoop() +#include // ResetShutdown() + +EFI_STATUS +EFIAPI +DxeResetInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c b/Ovmf= Pkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c new file mode 100644 index 000000000000..14f7653aa8de --- /dev/null +++ b/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c @@ -0,0 +1,128 @@ +/** @file + Reset System Library functions for RISC-V + + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + // Shut down via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE= ); +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform. The platform m= ay + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + // + // Can map to OpenSBI vendor or platform specific reset type. + // + return; +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,= or EfiResetShutdown + the data buffer starts with a Null-terminated = string, optionally + followed by additional binary data. The string= is a description + that the caller may use to further indicate th= e reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97459): https://edk2.groups.io/g/devel/message/97459 Mute This Topic: https://groups.io/mt/95687644/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97460+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97460+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109050; cv=none; d=zohomail.com; s=zohoarc; b=bAgAyCBDvKFVhK1zBnpsButaWMOGi5PfYG91ac1vEN3KJYTdH8MmGvLuZLw2tmKVlRf9DRC7YhEW6FKo9gp8iIv+s7/W310yZzRu9tddHZoYBCrGj365iCMLNz8g3RDK6BCioB8Oe8Ezfg1D4bJ0Q8iXhiX/OxFS3pCKUWCrIDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109050; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Y4BTK9jPo6EXmFatiMnhDSUX/YJiRVTQGezw7PEn8mo=; b=AV4zOxJe2N18JxvaO7sSB+OXYGkQxc1ZdfrT2pMXqrQw5LyMoKpx08lQdHZAxMjB3o9AVSvsTRjh3M3h1UqaSUOYroKmzJsKYfqq/8ztYBrVRylHpxpPxigpnPLS9bYnejxKNSkTeReLRMUmAnmAJUgl/1jVxcTZO66no2zTG1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97460+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16711090501151007.5750552565386; Thu, 15 Dec 2022 04:57:30 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id pW8rYY1788612xXTbxBgQ7W5; Thu, 15 Dec 2022 04:57:29 -0800 X-Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web10.132078.1671109048876074125 for ; Thu, 15 Dec 2022 04:57:28 -0800 X-Received: by mail-pg1-f169.google.com with SMTP id 36so4079572pgp.10 for ; Thu, 15 Dec 2022 04:57:28 -0800 (PST) X-Gm-Message-State: LvGJUKmSfU9thvjhSIhzkqDfx1787277AA= X-Google-Smtp-Source: AA0mqf4FsHah9G6G7ph8rDi9ml+wrrfpLtbk3C8hDjAqaAQPwDRQPry68f6eOBelXl51qr58TPieeA== X-Received: by 2002:a05:6a00:26c5:b0:576:dc87:a8f1 with SMTP id p5-20020a056a0026c500b00576dc87a8f1mr27059077pfw.19.1671109048018; Thu, 15 Dec 2022 04:57:28 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:27 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Brijesh Singh , Erdem Aktas , James Bottomley , Min Xu , Tom Lendacky , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 20/23] OvmfPkg/Sec: Add RISC-V SEC module Date: Thu, 15 Dec 2022 18:26:23 +0530 Message-Id: <20221215125626.545372-21-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109049; bh=3rmRKGOwdhEkmgaegTvColzaSEE5aClH+7vjllutD5M=; h=Cc:Date:From:Reply-To:Subject:To; b=IUpSKrPYdJuLYsF3XDdt3PvIpDFd9LC9khvXjE6YUPSJ2Rw173eCOntQTHcYEste2C2 t0mUMkiCSkmYJEK6X75Knp57WXi0Uy9LxNV6NkPnivln469UTpZ6NzzKkeTXk1gkV7QkQ XVRFIy05h8odcuxgY0kaynqNiv522WBlQoo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109051576100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add the SEC module for RISC-V. It uses the PEI less design. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Min Xu Cc: Tom Lendacky Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- OvmfPkg/Sec/SecMainRiscV64.inf | 58 +++++++++++ OvmfPkg/Sec/RiscV64/SecMain.h | 63 ++++++++++++ OvmfPkg/Sec/RiscV64/SecMain.c | 104 ++++++++++++++++++++ OvmfPkg/Sec/RiscV64/SecEntry.S | 21 ++++ 4 files changed, 246 insertions(+) diff --git a/OvmfPkg/Sec/SecMainRiscV64.inf b/OvmfPkg/Sec/SecMainRiscV64.inf new file mode 100644 index 000000000000..79a9538aebde --- /dev/null +++ b/OvmfPkg/Sec/SecMainRiscV64.inf @@ -0,0 +1,58 @@ +## @file +# SEC Driver for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D SecMainRiscV64 + FILE_GUID =3D 16740C0A-AA84-4F62-A06D-AE328057AE07 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/SecEntry.S + RiscV64/SecMain.c + RiscV64/SecMain.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + IoLib + PeCoffLib + LzmaDecompressLib + PlatformInitLib + RiscVSbiLib + PrePiLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid ## PRODUCES + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress diff --git a/OvmfPkg/Sec/RiscV64/SecMain.h b/OvmfPkg/Sec/RiscV64/SecMain.h new file mode 100644 index 000000000000..9d459dccaad4 --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecMain.h @@ -0,0 +1,63 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +#endif diff --git a/OvmfPkg/Sec/RiscV64/SecMain.c b/OvmfPkg/Sec/RiscV64/SecMain.c new file mode 100644 index 000000000000..054e49ef0c1e --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecMain.c @@ -0,0 +1,104 @@ +/** @file + RISC-V SEC phase module for Qemu Virt. + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +STATIC +EFI_STATUS +EFIAPI +SecInitializePlatform ( + VOID + ) +{ + EFI_STATUS Status; + + MemoryPeimInitialization (); + + CpuPeimInitialization (); + + // Set the Boot Mode + SetBootMode (BOOT_WITH_FULL_CONFIGURATION); + + Status =3D PlatformPeimInitialization (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_STATUS Status; + UINT64 UefiMemoryBase; + UINT64 StackBase; + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __FUNCTION__, + BootHartId, + DeviceTreeAddress + )); + + FirmwareContext.BootHartId =3D BootHartId; + FirmwareContext.FlattenedDeviceTree =3D (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + StackBase =3D (UINT64)FixedPcdGet32 (PcdOvmfSecPeiTempRamBase); + UefiMemoryBase =3D StackBase + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)= - SIZE_32MB; + + // Declare the PI/UEFI memory region + HobList =3D HobConstructor ( + (VOID *)UefiMemoryBase, + SIZE_32MB, + (VOID *)UefiMemoryBase, + (VOID *)StackBase // The top of the UEFI Memory is reserved = for the stacks + ); + PrePeiSetHobList (HobList); + + SecInitializePlatform (); + + // + // Process all libraries constructor function linked to SecMain. + // + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compre= ssed FV. + Status =3D DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status =3D LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/OvmfPkg/Sec/RiscV64/SecEntry.S b/OvmfPkg/Sec/RiscV64/SecEntry.S new file mode 100644 index 000000000000..e919a3cb0e80 --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecEntry.S @@ -0,0 +1,21 @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +.text +.align 3 + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + li a5, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97460): https://edk2.groups.io/g/devel/message/97460 Mute This Topic: https://groups.io/mt/95687645/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97461+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97461+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109052; cv=none; d=zohomail.com; s=zohoarc; b=TqHZcWQolEzCodQG/+Pa91rIvku2OFwpQ/wxd0nkoIi3QIXDKy8nhy5ZdH4TK/tFoMiZfj+aHJADbfmyNNhjSzxVUtRd5duu6fcgRslJJnT7E4S2RiC/fsl/9I+yROdEgVbkOChv99gNLF5bv4OnwZm92nquXumoAC81aN8U4BM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109052; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=opuIzh76NKgCz6fJLRUhw8ePt36Ms0ST+R0AxjE2pgk=; b=e5oMzAwi/YIfb62P5EeQzTBcyY7BClCeV/SHHKBlCSNw01H5K9NfCsioKt0Cu4aT3FhpKwHNPe6uSnJLvtYM4lVavkTm2PC1SaFQXEq+zpDAvVxD6snASRO6Pq321xeN+MCB5nerdbSlibc8BDIw8zz3HBt4kjudHjo51sJS/TM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97461+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109052821732.1299436950246; Thu, 15 Dec 2022 04:57:32 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id A8mNYY1788612xpkIEGu9UON; Thu, 15 Dec 2022 04:57:32 -0800 X-Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by mx.groups.io with SMTP id smtpd.web11.132934.1671109037322333443 for ; Thu, 15 Dec 2022 04:57:31 -0800 X-Received: by mail-pf1-f182.google.com with SMTP id a14so6647200pfa.1 for ; Thu, 15 Dec 2022 04:57:31 -0800 (PST) X-Gm-Message-State: g1Yn82J1ppBAp7TPzkr6CGUfx1787277AA= X-Google-Smtp-Source: AA0mqf71/n9YrYJQbcQqUlnuvLEGwx3eThQ8qhGeyc76zs8k/3YS6mzJPfWkx5Tp65owNdsGjzaVWA== X-Received: by 2002:a05:6a00:1c9c:b0:577:3126:704b with SMTP id y28-20020a056a001c9c00b005773126704bmr29648161pfw.17.1671109050803; Thu, 15 Dec 2022 04:57:30 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:30 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 21/23] OvmfPkg/PlatformBootManagerLib: Add RISC-V instance Date: Thu, 15 Dec 2022 18:26:24 +0530 Message-Id: <20221215125626.545372-22-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109052; bh=fJA5BYps/DVcDZOVq1tkyvYEGfbEAVMe3LmHMld1r3g=; h=Cc:Date:From:Reply-To:Subject:To; b=b7OLVGbhz0NPcg+oWI5fi8lYoLr6jzJFlz7OhOfeD00ZZjkchGpnN6I4hmJSMLLjOXG LSJ9QiD9dqoCANk5gPcNfZsB6tWfXeuCHcwaBf9XntaHL52zDhk/p85hl+Xr2JoFDpKh+ 1A8NfjkUu5zKy4UR6llRJpDlbRREndxD12E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109053603100006 Content-Type: text/plain; charset="utf-8" This is mostly copied from ArmVirtPkg since RISC-V follows similar model. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64PlatformBootManagerLib.in= f | 75 ++ OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.h = | 45 + OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.c = | 1078 ++++++++++++++++++++ OvmfPkg/Library/PlatformBootManagerLib/RiscV64/QemuKernel.c = | 77 ++ 4 files changed, 1275 insertions(+) diff --git a/OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64PlatformBootM= anagerLib.inf b/OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64PlatformBo= otManagerLib.inf new file mode 100644 index 000000000000..cccf339a05a8 --- /dev/null +++ b/OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64PlatformBootManagerL= ib.inf @@ -0,0 +1,75 @@ +## @file +# Implementation for PlatformBootManagerLib library class interfaces for = RISC-V. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D DxeRiscV64PlatformBootManagerLib + FILE_GUID =3D 4FC87DC9-2666-49BB-9023-B5FAA1E9E732 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformBootManagerLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/PlatformBm.c + RiscV64/PlatformBm.h + RiscV64/QemuKernel.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + SecurityPkg/SecurityPkg.dec + ShellPkg/ShellPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BootLogoLib + DebugLib + DevicePathLib + MemoryAllocationLib + PcdLib + PlatformBmPrintScLib + QemuBootOrderLib + QemuLoadImageLib + ReportStatusCodeLib + TpmPlatformHierarchyLib + UefiBootManagerLib + UefiBootServicesTableLib + UefiLib + UefiRuntimeServicesTableLib + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[Guids] + gEfiEndOfDxeEventGroupGuid + gEfiGlobalVariableGuid + gRootBridgesConnectedEventGroupGuid + gUefiShellFileGuid + gEfiTtyTermGuid + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid + gEfiGraphicsOutputProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gVirtioDeviceProtocolGuid diff --git a/OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.h b/= OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.h new file mode 100644 index 000000000000..70c52d9832ca --- /dev/null +++ b/OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.h @@ -0,0 +1,45 @@ +/** @file + Head file for BDS Platform specific code + + Copyright (C) 2015-2016, Red Hat, Inc. + Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BM_H_ +#define _PLATFORM_BM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Download the kernel, the initial ramdisk, and the kernel command line fr= om + QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two + image files, and load and start the kernel from it. + + The kernel will be instructed via its command line to load the initrd fr= om + the same Simple FileSystem. + + @retval EFI_NOT_FOUND Kernel image was not found. + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. + @retval EFI_PROTOCOL_ERROR Unterminated kernel command line. + + @return Error codes from any of the underlying + functions. On success, the function doesn't + return. +**/ +EFI_STATUS +EFIAPI +TryRunningQemuKernel ( + VOID + ); + +#endif // _PLATFORM_BM_H_ diff --git a/OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.c b/= OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.c new file mode 100644 index 000000000000..2559889638ad --- /dev/null +++ b/OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.c @@ -0,0 +1,1078 @@ +/** @file + Implementation for PlatformBootManagerLib library class interfaces. + + Copyright (C) 2015-2016, Red Hat, Inc. + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformBm.h" + +#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >= > 8) } + +#define VERSION_STRING_PREFIX L"RISC-V EDK2 firmware version " + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH SerialDxe; + UART_DEVICE_PATH Uart; + VENDOR_DEFINED_DEVICE_PATH TermType; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_SERIAL_CONSOLE; +#pragma pack () + +STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole =3D { + // + // VENDOR_DEVICE_PATH SerialDxe + // + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH= ) }, + EDKII_SERIAL_PORT_LIB_VENDOR_GUID + }, + + // + // UART_DEVICE_PATH Uart + // + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) = }, + 0, // Reserved + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits + FixedPcdGet8 (PcdUartDefaultParity), // Parity + FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits + }, + + // + // VENDOR_DEFINED_DEVICE_PATH TermType + // + { + { + MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, + DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) + } + // + // Guid to be filled in dynamically + // + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + +#pragma pack (1) +typedef struct { + USB_CLASS_DEVICE_PATH Keyboard; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_USB_KEYBOARD; +#pragma pack () + +STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard =3D { + // + // USB_CLASS_DEVICE_PATH Keyboard + // + { + { + MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, + DP_NODE_LEN (USB_CLASS_DEVICE_PATH) + }, + 0xFFFF, // VendorId: any + 0xFFFF, // ProductId: any + 3, // DeviceClass: HID + 1, // DeviceSubClass: boot + 1 // DeviceProtocol: keyboard + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + +/** + Check if the handle satisfies a particular condition. + + @param[in] Handle The handle to check. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. + + @retval TRUE The condition is satisfied. + @retval FALSE Otherwise. This includes the case when the condition coul= d not + be fully evaluated due to an error. +**/ +typedef +BOOLEAN +(EFIAPI *FILTER_FUNCTION)( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Process a handle. + + @param[in] Handle The handle to process. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. +**/ +typedef +VOID +(EFIAPI *CALLBACK_FUNCTION)( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Locate all handles that carry the specified protocol, filter them with a + callback function, and pass each handle that passes the filter to another + callback. + + @param[in] ProtocolGuid The protocol to look for. + + @param[in] Filter The filter function to pass each handle to. If = this + parameter is NULL, then all handles are process= ed. + + @param[in] Process The callback function to pass each handle to th= at + clears the filter. +**/ +STATIC +VOID +FilterAndProcess ( + IN EFI_GUID *ProtocolGuid, + IN FILTER_FUNCTION Filter OPTIONAL, + IN CALLBACK_FUNCTION Process + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN NoHandles; + UINTN Idx; + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + ProtocolGuid, + NULL /* SearchKey */, + &NoHandles, + &Handles + ); + if (EFI_ERROR (Status)) { + // + // This is not an error, just an informative condition. + // + DEBUG (( + DEBUG_VERBOSE, + "%a: %g: %r\n", + __FUNCTION__, + ProtocolGuid, + Status + )); + return; + } + + ASSERT (NoHandles > 0); + for (Idx =3D 0; Idx < NoHandles; ++Idx) { + CHAR16 *DevicePathText; + STATIC CHAR16 Fallback[] =3D L""; + + // + // The ConvertDevicePathToText() function handles NULL input transpare= ntly. + // + DevicePathText =3D ConvertDevicePathToText ( + DevicePathFromHandle (Handles[Idx]), + FALSE, // DisplayOnly + FALSE // AllowShortcuts + ); + if (DevicePathText =3D=3D NULL) { + DevicePathText =3D Fallback; + } + + if ((Filter =3D=3D NULL) || Filter (Handles[Idx], DevicePathText)) { + Process (Handles[Idx], DevicePathText); + } + + if (DevicePathText !=3D Fallback) { + FreePool (DevicePathText); + } + } + + gBS->FreePool (Handles); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a PCI display dev= ice. +**/ +STATIC +BOOLEAN +EFIAPI +IsPciDisplay ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + + Status =3D gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + // + // This is not an error worth reporting. + // + return FALSE; + } + + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0 /* Offset */, + sizeof Pci / sizeof (UINT32), + &Pci + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status)= ); + return FALSE; + } + + return IS_PCI_DISPLAY (&Pci); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a Virtio RNG devi= ce at + the VIRTIO_DEVICE_PROTOCOL level. +**/ +STATIC +BOOLEAN +EFIAPI +IsVirtioRng ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + VIRTIO_DEVICE_PROTOCOL *VirtIo; + + Status =3D gBS->HandleProtocol ( + Handle, + &gVirtioDeviceProtocolGuid, + (VOID **)&VirtIo + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return (BOOLEAN)(VirtIo->SubSystemDeviceId =3D=3D + VIRTIO_SUBSYSTEM_ENTROPY_SOURCE); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a Virtio RNG devi= ce at + the EFI_PCI_IO_PROTOCOL level. +**/ +STATIC +BOOLEAN +EFIAPI +IsVirtioPciRng ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT16 VendorId; + UINT16 DeviceId; + UINT8 RevisionId; + BOOLEAN Virtio10; + UINT16 SubsystemId; + + Status =3D gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + // + // Read and check VendorId. + // + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_VENDOR_ID_OFFSET, + 1, + &VendorId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + if (VendorId !=3D VIRTIO_VENDOR_ID) { + return FALSE; + } + + // + // Read DeviceId and RevisionId. + // + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_DEVICE_ID_OFFSET, + 1, + &DeviceId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + PCI_REVISION_ID_OFFSET, + 1, + &RevisionId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + // + // From DeviceId and RevisionId, determine whether the device is a + // modern-only Virtio 1.0 device. In case of Virtio 1.0, DeviceId can + // immediately be restricted to VIRTIO_SUBSYSTEM_ENTROPY_SOURCE, and + // SubsystemId will only play a sanity-check role. Otherwise, DeviceId c= an + // only be sanity-checked, and SubsystemId will decide. + // + if ((DeviceId =3D=3D 0x1040 + VIRTIO_SUBSYSTEM_ENTROPY_SOURCE) && + (RevisionId >=3D 0x01)) + { + Virtio10 =3D TRUE; + } else if ((DeviceId >=3D 0x1000) && (DeviceId <=3D 0x103F) && (Revision= Id =3D=3D 0x00)) { + Virtio10 =3D FALSE; + } else { + return FALSE; + } + + // + // Read and check SubsystemId as dictated by Virtio10. + // + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_SUBSYSTEM_ID_OFFSET, + 1, + &SubsystemId + ); + if (EFI_ERROR (Status)) { + goto PciError; + } + + if (Virtio10 && (SubsystemId >=3D 0x40)) { + return TRUE; + } + + if (!Virtio10 && (SubsystemId =3D=3D VIRTIO_SUBSYSTEM_ENTROPY_SOURCE)) { + return TRUE; + } + + return FALSE; + +PciError: + DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status)); + return FALSE; +} + +/** + This CALLBACK_FUNCTION attempts to connect a handle non-recursively, ask= ing + the matching driver to produce all first-level child handles. +**/ +STATIC +VOID +EFIAPI +Connect ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + + Status =3D gBS->ConnectController ( + Handle, // ControllerHandle + NULL, // DriverImageHandle + NULL, // RemainingDevicePath -- produce all children + FALSE // Recursive + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, + "%a: %s: %r\n", + __FUNCTION__, + ReportText, + Status + )); +} + +/** + This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the + handle, and adds it to ConOut and ErrOut. +**/ +STATIC +VOID +EFIAPI +AddOutput ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + DevicePath =3D DevicePathFromHandle (Handle); + if (DevicePath =3D=3D NULL) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: handle %p: device path not found\n", + __FUNCTION__, + ReportText, + Handle + )); + return; + } + + Status =3D EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL= ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: adding to ConOut: %r\n", + __FUNCTION__, + ReportText, + Status + )); + return; + } + + Status =3D EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL= ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: adding to ErrOut: %r\n", + __FUNCTION__, + ReportText, + Status + )); + return; + } + + DEBUG (( + DEBUG_VERBOSE, + "%a: %s: added to ConOut and ErrOut\n", + __FUNCTION__, + ReportText + )); +} + +STATIC +VOID +PlatformRegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINT32 Attributes + ) +{ + EFI_STATUS Status; + INTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status =3D gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **)&LoadedImage + ); + ASSERT_EFI_ERROR (Status); + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + DevicePath =3D DevicePathFromHandle (LoadedImage->DeviceHandle); + ASSERT (DevicePath !=3D NULL); + DevicePath =3D AppendDevicePathNode ( + DevicePath, + (EFI_DEVICE_PATH_PROTOCOL *)&FileNode + ); + ASSERT (DevicePath !=3D NULL); + + Status =3D EfiBootManagerInitializeLoadOption ( + &NewOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + NULL, + 0 + ); + ASSERT_EFI_ERROR (Status); + FreePool (DevicePath); + + BootOptions =3D EfiBootManagerGetLoadOptions ( + &BootOptionCount, + LoadOptionTypeBoot + ); + + OptionIndex =3D EfiBootManagerFindLoadOption ( + &NewOption, + BootOptions, + BootOptionCount + ); + + if (OptionIndex =3D=3D -1) { + Status =3D EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN); + ASSERT_EFI_ERROR (Status); + } + + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + +/** + Remove all MemoryMapped(...)/FvFile(...) and Fv(...)/FvFile(...) boot op= tions + whose device paths do not resolve exactly to an FvFile in the system. + + This removes any boot options that point to binaries built into the firm= ware + and have become stale due to any of the following: + - FvMain's base address or size changed (historical), + - FvMain's FvNameGuid changed, + - the FILE_GUID of the pointed-to binary changed, + - the referenced binary is no longer built into the firmware. + + EfiBootManagerFindLoadOption() used in PlatformRegisterFvBootOption() on= ly + avoids exact duplicates. +**/ +STATIC +VOID +RemoveStaleFvFileOptions ( + VOID + ) +{ + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + UINTN Index; + + BootOptions =3D EfiBootManagerGetLoadOptions ( + &BootOptionCount, + LoadOptionTypeBoot + ); + + for (Index =3D 0; Index < BootOptionCount; ++Index) { + EFI_DEVICE_PATH_PROTOCOL *Node1, *Node2, *SearchNode; + EFI_STATUS Status; + EFI_HANDLE FvHandle; + + // + // If the device path starts with neither MemoryMapped(...) nor Fv(...= ), + // then keep the boot option. + // + Node1 =3D BootOptions[Index].FilePath; + if (!((DevicePathType (Node1) =3D=3D HARDWARE_DEVICE_PATH) && + (DevicePathSubType (Node1) =3D=3D HW_MEMMAP_DP)) && + !((DevicePathType (Node1) =3D=3D MEDIA_DEVICE_PATH) && + (DevicePathSubType (Node1) =3D=3D MEDIA_PIWG_FW_VOL_DP))) + { + continue; + } + + // + // If the second device path node is not FvFile(...), then keep the bo= ot + // option. + // + Node2 =3D NextDevicePathNode (Node1); + if ((DevicePathType (Node2) !=3D MEDIA_DEVICE_PATH) || + (DevicePathSubType (Node2) !=3D MEDIA_PIWG_FW_FILE_DP)) + { + continue; + } + + // + // Locate the Firmware Volume2 protocol instance that is denoted by the + // boot option. If this lookup fails (i.e., the boot option references= a + // firmware volume that doesn't exist), then we'll proceed to delete t= he + // boot option. + // + SearchNode =3D Node1; + Status =3D gBS->LocateDevicePath ( + &gEfiFirmwareVolume2ProtocolGuid, + &SearchNode, + &FvHandle + ); + + if (!EFI_ERROR (Status)) { + // + // The firmware volume was found; now let's see if it contains the F= vFile + // identified by GUID. + // + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileNode; + UINTN BufferSize; + EFI_FV_FILETYPE FoundType; + EFI_FV_FILE_ATTRIBUTES FileAttributes; + UINT32 AuthenticationStatus; + + Status =3D gBS->HandleProtocol ( + FvHandle, + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvProtocol + ); + ASSERT_EFI_ERROR (Status); + + FvFileNode =3D (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)Node2; + // + // Buffer=3D=3DNULL means we request metadata only: BufferSize, Foun= dType, + // FileAttributes. + // + Status =3D FvProtocol->ReadFile ( + FvProtocol, + &FvFileNode->FvFileName, // NameGuid + NULL, // Buffer + &BufferSize, + &FoundType, + &FileAttributes, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + // + // The FvFile was found. Keep the boot option. + // + continue; + } + } + + // + // Delete the boot option. + // + Status =3D EfiBootManagerDeleteLoadOptionVariable ( + BootOptions[Index].OptionNumber, + LoadOptionTypeBoot + ); + DEBUG_CODE_BEGIN (); + CHAR16 *DevicePathString; + + DevicePathString =3D ConvertDevicePathToText ( + BootOptions[Index].FilePath, + FALSE, + FALSE + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_WARN : DEBUG_VERBOSE, + "%a: removing stale Boot#%04x %s: %r\n", + __FUNCTION__, + (UINT32)BootOptions[Index].OptionNumber, + DevicePathString =3D=3D NULL ? L"" : DevicePathString, + Status + )); + if (DevicePathString !=3D NULL) { + FreePool (DevicePathString); + } + + DEBUG_CODE_END (); + } + + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + +STATIC +VOID +PlatformRegisterOptionsAndKeys ( + VOID + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Enter; + EFI_INPUT_KEY F2; + EFI_INPUT_KEY Esc; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + + // + // Register ENTER as CONTINUE key + // + Enter.ScanCode =3D SCAN_NULL; + Enter.UnicodeChar =3D CHAR_CARRIAGE_RETURN; + Status =3D EfiBootManagerRegisterContinueKeyOption (0, &Enter= , NULL); + ASSERT_EFI_ERROR (Status); + + // + // Map F2 and ESC to Boot Manager Menu + // + F2.ScanCode =3D SCAN_F2; + F2.UnicodeChar =3D CHAR_NULL; + Esc.ScanCode =3D SCAN_ESC; + Esc.UnicodeChar =3D CHAR_NULL; + Status =3D EfiBootManagerGetBootManagerMenu (&BootOption); + ASSERT_EFI_ERROR (Status); + Status =3D EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)BootOption.OptionNumber, + 0, + &F2, + NULL + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED); + Status =3D EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)BootOption.OptionNumber, + 0, + &Esc, + NULL + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED); +} + +// +// BDS Platform Functions +// + +/** + Do the platform init, can be customized by OEM/IBV + Possible things that can be done in PlatformBootManagerBeforeConsole: + > Update console variable: 1. include hot-plug devices; + > 2. Clear ConIn and add SOL for AMT + > Register new Driver#### or Boot#### + > Register new Key####: e.g.: F12 + > Signal ReadyToLock event + > Authentication action: 1. connect Auth devices; + > 2. Identify auto logon user. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + UINT16 FrontPageTimeout; + RETURN_STATUS PcdStatus; + EFI_STATUS Status; + + // + // Signal EndOfDxe PI Event + // + EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid); + + // + // Disable the TPM 2 platform hierarchy + // + ConfigureTpmPlatformHierarchy (); + + // + // Dispatch deferred images after EndOfDxe event. + // + EfiBootManagerDispatchDeferredImages (); + + // + // Locate the PCI root bridges and make the PCI bus driver connect each, + // non-recursively. This will produce a number of child handles with Pci= Io on + // them. + // + FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect); + + // + // Signal the ACPI platform driver that it can download QEMU ACPI tables. + // + EfiEventGroupSignal (&gRootBridgesConnectedEventGroupGuid); + + // + // Find all display class PCI devices (using the handles from the previo= us + // step), and connect them non-recursively. This should produce a number= of + // child handles with GOPs on them. + // + FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect); + + // + // Now add the device path of all handles with GOP on them to ConOut and + // ErrOut. + // + FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput); + + // + // Add the hardcoded short-form USB keyboard device path to ConIn. + // + EfiBootManagerUpdateConsoleVariable ( + ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, + NULL + ); + + // + // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. + // + CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid); + + EfiBootManagerUpdateConsoleVariable ( + ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + EfiBootManagerUpdateConsoleVariable ( + ConOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + EfiBootManagerUpdateConsoleVariable ( + ErrOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + + // + // Set the front page timeout from the QEMU configuration. + // + FrontPageTimeout =3D GetFrontPageTimeoutFromQemu (); + PcdStatus =3D PcdSet16S (PcdPlatformBootTimeOut, FrontPageTimeout= ); + ASSERT_RETURN_ERROR (PcdStatus); + // + // Reflect the PCD in the standard Timeout variable. + // + Status =3D gRT->SetVariable ( + EFI_TIME_OUT_VARIABLE_NAME, + &gEfiGlobalVariableGuid, + (EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS), + sizeof FrontPageTimeout, + &FrontPageTimeout + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, + "%a: SetVariable(%s, %u): %r\n", + __FUNCTION__, + EFI_TIME_OUT_VARIABLE_NAME, + FrontPageTimeout, + Status + )); + + // + // Register platform-specific boot options and keyboard shortcuts. + // + PlatformRegisterOptionsAndKeys (); + + // + // At this point, VIRTIO_DEVICE_PROTOCOL instances exist only for Virtio= MMIO + // transports. Install EFI_RNG_PROTOCOL instances on Virtio MMIO RNG dev= ices. + // + FilterAndProcess (&gVirtioDeviceProtocolGuid, IsVirtioRng, Connect); + + // + // Install both VIRTIO_DEVICE_PROTOCOL and (dependent) EFI_RNG_PROTOCOL + // instances on Virtio PCI RNG devices. + // + FilterAndProcess (&gEfiPciIoProtocolGuid, IsVirtioPciRng, Connect); +} + +/** + Do the platform specific action after the console is ready + Possible things that can be done in PlatformBootManagerAfterConsole: + > Console post action: + > Dynamically switch output mode from 100x31 to 80x25 for certain scen= ario + > Signal console ready platform customized event + > Run diagnostics like memory testing + > Connect certain devices + > Dispatch additional option roms + > Special boot: e.g.: USB boot, enter UI +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + RETURN_STATUS Status; + UINTN FirmwareVerLength; + + FirmwareVerLength =3D StrLen (PcdGetPtr (PcdFirmwareVersionString)); + // + // Show the splash screen. + // + BootLogoEnableLogo (); + + if (FirmwareVerLength > 0) { + Print ( + VERSION_STRING_PREFIX L"%s\n", + PcdGetPtr (PcdFirmwareVersionString) + ); + } + + Print (L"Press ESCAPE within 10 seconds for boot options "); + // + // Process QEMU's -kernel command line option. The kernel booted this way + // will receive ACPI tables: in PlatformBootManagerBeforeConsole(), we + // connected any and all PCI root bridges, and then signaled the ACPI + // platform driver. + // + TryRunningQemuKernel (); + + // + // Connect the purported boot devices. + // + Status =3D ConnectDevicesFromQemu (); + if (RETURN_ERROR (Status)) { + // + // Connect the rest of the devices. + // + EfiBootManagerConnectAll (); + } + + // + // Enumerate all possible boot options, then filter and reorder them bas= ed on + // the QEMU configuration. + // + EfiBootManagerRefreshAllBootOption (); + + // + // Register UEFI Shell + // + PlatformRegisterFvBootOption ( + &gUefiShellFileGuid, + L"EFI Internal Shell", + LOAD_OPTION_ACTIVE + ); + + RemoveStaleFvFileOptions (); + SetBootOrderFromQemu (); + + PlatformBmPrintScRegisterHandler (); +} + +/** + This function is called each second during the boot manager waits the + timeout. + + @param TimeoutRemain The remaining timeout. +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White; + UINT16 TimeoutInitial; + + TimeoutInitial =3D PcdGet16 (PcdPlatformBootTimeOut); + + // + // If PcdPlatformBootTimeOut is set to zero, then we consider + // that no progress update should be enacted. + // + if (TimeoutInitial =3D=3D 0) { + return; + } + + Black.Raw =3D 0x00000000; + White.Raw =3D 0x00FFFFFF; + + BootLogoUpdateProgress ( + White.Pixel, + Black.Pixel, + L"Start boot option", + White.Pixel, + (TimeoutInitial - TimeoutRemain) * 100 / TimeoutInitial, + 0 + ); +} + +/** + The function is called when no boot option could be launched, + including platform recovery options and options pointing to applications + built into firmware volumes. + + If this function returns, BDS attempts to enter an infinite loop. +**/ +VOID +EFIAPI +PlatformBootManagerUnableToBoot ( + VOID + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Key; + EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu; + UINTN Index; + + // + // BootManagerMenu doesn't contain the correct information when return s= tatus + // is EFI_NOT_FOUND. + // + Status =3D EfiBootManagerGetBootManagerMenu (&BootManagerMenu); + if (EFI_ERROR (Status)) { + return; + } + + // + // Normally BdsDxe does not print anything to the system console, but th= is is + // a last resort -- the end-user will likely not see any DEBUG messages + // logged in this situation. + // + // AsciiPrint() will NULL-check gST->ConOut internally. We check gST->Co= nIn + // here to see if it makes sense to request and wait for a keypress. + // + if (gST->ConIn !=3D NULL) { + AsciiPrint ( + "%a: No bootable option or device was found.\n" + "%a: Press any key to enter the Boot Manager Menu.\n", + gEfiCallerBaseName, + gEfiCallerBaseName + ); + Status =3D gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &Index); + ASSERT_EFI_ERROR (Status); + ASSERT (Index =3D=3D 0); + + // + // Drain any queued keys. + // + while (!EFI_ERROR (gST->ConIn->ReadKeyStroke (gST->ConIn, &Key))) { + // + // just throw away Key + // + } + } + + for ( ; ;) { + EfiBootManagerBoot (&BootManagerMenu); + } +} diff --git a/OvmfPkg/Library/PlatformBootManagerLib/RiscV64/QemuKernel.c b/= OvmfPkg/Library/PlatformBootManagerLib/RiscV64/QemuKernel.c new file mode 100644 index 000000000000..736628174f4e --- /dev/null +++ b/OvmfPkg/Library/PlatformBootManagerLib/RiscV64/QemuKernel.c @@ -0,0 +1,77 @@ +/** @file + Try to load an EFI-stubbed RISC-V Linux kernel from QEMU's fw_cfg. + + This implementation differs from OvmfPkg/Library/LoadLinuxLib. An EFI + stub in the subject kernel is a hard requirement here. + + Copyright (C) 2014-2016, Red Hat, Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include "PlatformBm.h" + +// +// The entry point of the feature. +// + +/** + Download the kernel, the initial ramdisk, and the kernel command line fr= om + QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two + image files, and load and start the kernel from it. + + The kernel will be instructed via its command line to load the initrd fr= om + the same Simple FileSystem. + + @retval EFI_NOT_FOUND Kernel image was not found. + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. + @retval EFI_PROTOCOL_ERROR Unterminated kernel command line. + + @return Error codes from any of the underlying + functions. On success, the function doesn't + return. +**/ +EFI_STATUS +EFIAPI +TryRunningQemuKernel ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE KernelImageHandle; + + Status =3D QemuLoadKernelImage (&KernelImageHandle); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Signal the EFI_EVENT_GROUP_READY_TO_BOOT event. + // + EfiSignalEventReadyToBoot (); + + REPORT_STATUS_CODE ( + EFI_PROGRESS_CODE, + (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT) + ); + + // + // Start the image. + // + Status =3D QemuStartKernelImage (&KernelImageHandle); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: QemuStartKernelImage(): %r\n", + __FUNCTION__, + Status + )); + } + + QemuUnloadKernelImage (KernelImageHandle); + + return Status; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97461): https://edk2.groups.io/g/devel/message/97461 Mute This Topic: https://groups.io/mt/95687646/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97462+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97462+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109055; cv=none; d=zohomail.com; s=zohoarc; b=Yfaj5+j/AnpHIEGEFfAv51eiXFjRVR4J8a/WNt1BEasXhsBpQyl6fCR3Q18mutGfH5VmUi4gJKaAsX32vDARQVoFgpSFdv3mL7R2BDrZsdl/B0LtqE7nw7wzxQf316xio1JpnTToq7GryNZ0e5Am0pK/s1jrCSB9LuPNsWtgBJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109055; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jcHqM3xSNGNhzMArih/TdcF5z72aZCPYGW8EBBXq6eU=; b=G8Pc6DWnpjj3HMpmkSwuGA/UBpCQgMsvBM5j4860Hs7lJwoaIrax7UFWwC0QoqjcpIWF1ikNiEGW0Y6dvtmZTbOfspH3j5p6hLJz8BUcuhF5CDtTn8bQQUWfAjtLd7KN+BZiQlEwyTMtieJM3RIDiMppPl+pcJNlTuVcNLzEuxs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97462+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109055233420.76439664803354; Thu, 15 Dec 2022 04:57:35 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Lvs8YY1788612xsjMPwE4O4y; Thu, 15 Dec 2022 04:57:34 -0800 X-Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) by mx.groups.io with SMTP id smtpd.web11.132942.1671109054284419845 for ; Thu, 15 Dec 2022 04:57:34 -0800 X-Received: by mail-pg1-f178.google.com with SMTP id h33so4090029pgm.9 for ; Thu, 15 Dec 2022 04:57:34 -0800 (PST) X-Gm-Message-State: VlC7EJExYeJ1Uao56O8pQQ5Cx1787277AA= X-Google-Smtp-Source: AMrXdXvEWJ/2y0QJhOASN+kSYWduvjv1IXgWMiyRXM3an9d/QgoX+fi+50Ft2U8jHiNc7IWD/5FGTQ== X-Received: by 2002:a62:7b82:0:b0:57d:9b8e:92a7 with SMTP id w124-20020a627b82000000b0057d9b8e92a7mr4165651pfc.7.1671109053313; Thu, 15 Dec 2022 04:57:33 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:32 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 22/23] OvmfPkg: RiscVVirt: Add Qemu Virt platform support Date: Thu, 15 Dec 2022 18:26:25 +0530 Message-Id: <20221215125626.545372-23-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109054; bh=vqK8jgLF7DdwMvEpBH857UTDQGKsUlU9zuuA8AeYvvM=; h=Cc:Date:From:Reply-To:Subject:To; b=KJREU8uspKX7qE6G7/zU9MZSTQg0pD6cTTLcXmkcOITOLoUNY0S37hXrzRaQL63rA8N GZAHGOKy0Mbd/8sMgs2FEe6Ca+z2yaeoEJVpIwixZB9vzKhjDRxPeBpPulQwPM+AmZt7j TCAUVPy2UVE38+uNl/r0FU6bAnGyfKxVg8o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109055686100010 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - Leveraged from ArmVirtQemu Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 338 +++++++++++++ OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 510 ++++++++++++++++++++ OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 306 ++++++++++++ OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 41 ++ OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 +++ 5 files changed, 1274 insertions(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc new file mode 100644 index 000000000000..99741f3d8965 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -0,0 +1,338 @@ +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved. +# Copyright (c) 2011 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. +# Copyright (c) Microsoft Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEFINE DEBUG_PRINT_ERROR_LEVEL =3D 0x80000047 + +[LibraryClasses.common] +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + + # + # Ramdisk Requirements + # + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # Allow dynamic PCDs + # + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # Networking Requirements +!include NetworkPkg/NetworkLibs.dsc.inc +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif + + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + # RISC-V Architectural Libraries + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRis= cV64CpuExceptionHandlerLib.inf + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64= PlatformBootManagerLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitL= ib.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.= inf + + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # PCI Libraries + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf + DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + + # USB Libraries + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # + # CryptoPkg libraries needed by multiple firmware features + # + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf +!else + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf +!endif + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBo= otVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariablePro= visionLib/SecureBootVariableProvisionLib.inf + PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPo= licy/PlatformPKProtectionLibVarPolicy.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitL= ib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobLi= stPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + +[LibraryClasses.common.DXE_CORE] + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + +[LibraryClasses.common.DXE_DRIVER] + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + +[PcdsFeatureFlag] + # + # Activate AcpiSdtProtocol + # + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(DEBUG_ON_SERIAL_PORT) !=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error +!if $(DEBUG_ON_SERIAL_PORT) =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEV= EL) +!endif + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|6000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >=3D 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM an= d OS + # reserved ones, with the exception of LoaderData regions, of which OS l= oaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC0000000= 00007FD5 + +[Components.common] + # + # Ramdisk support + # + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.in= f { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf +!if $(ACPIVIEW_ENABLE) =3D=3D TRUE + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf +!endif + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf +!endif + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVV= irtQemu.dsc new file mode 100644 index 000000000000..270bfdc9eb3b --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -0,0 +1,510 @@ +## @file +# RISC-V EFI on RiscVVirtQem platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D RiscVVirtQemu + PLATFORM_GUID =3D 39DADB39-1B21-4867-838E-830B6149B9E0 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE TTY_TERMINAL =3D FALSE + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE TPM2_ENABLE =3D FALSE + DEFINE TPM2_CONFIG_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!if $(NETWORK_SNP_ENABLE) =3D=3D TRUE + !error "NETWORK_SNP_ENABLE is IA32/X64/EBC only" +!endif + + +!include MdePkg/MdeLibs.dsc.inc + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC: *_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include NetworkPkg/NetworkDefines.dsc.inc + +!include OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses.common] + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf + QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf + QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFw= CfgSimpleParserLib.inf + QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf + + TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf + VirtNorFlashPlatformLib|OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorF= lashStaticLib.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64= PlatformBootManagerLib.inf + PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciHostBridgeLib|OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf + PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostB= ridgeUtilityLib.inf + PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT= cg2PhysicalPresenceLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= b/PeiDxeTpmPlatformHierarchyLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2.inf +!endif + +[LibraryClasses.common.UEFI_DRIVER] + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + +#!include NetworkPkg/NetworkBuildOptions.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag.common] + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + # + # The cumulative and individual VOLATILE variable size limits should be = set + # high enough for accommodating several and/or large CA certificates. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x80000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVolatileVariableSize|0x40000 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"2.7" + + # Serial Port + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|9600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + + # + # Network Pcds + # +!include NetworkPkg/NetworkPcds.dsc.inc + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # + # The maximum physical I/O addressability of the processor, set with + # BuildCpuHob(). + # + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16 + + # + # Enable the non-executable DXE stack. (This gets set up by DxeIpl) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + gEfiShellPkgTokenSpaceGuid.PcdShellFileOperationSize|0x20000 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x02 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + +[PcdsDynamicDefault.common] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + ## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI + # enumeration to complete before installing ACPI tables. + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE + + # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this + # PCD and PcdPciDisableBusEnumeration above have not been assigned yet + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF + + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 + + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 + + # + # SMBIOS entry point version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + + # + # IPv4 and IPv6 PXE Boot support. + # + gEfiNetworkPkgTokenSpaceGuid.PcdIPv4PXESupport|0x01 + gEfiNetworkPkgTokenSpaceGuid.PcdIPv6PXESupport|0x01 + + # + # TPM2 support + # +!if $(TPM2_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0 +!else +[PcdsPatchableInModule] + # make this PCD patchable instead of dynamic when TPM support is not ena= bled + # this permits setting the PCD in unreachable code without pulling in dy= namic PCD support + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 +!endif + +[PcdsDynamicHii] + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS + +!if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2C= onfigFormSetGuid|0x8|3|NV,BS +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] +!if $(TPM2_ENABLE) =3D=3D TRUE + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf +!else + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +!endif + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + OvmfPkg/Sec/SecMainRiscV64.inf { + + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectio= nLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaC= ustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/Library/PrePiHobListPointerLib/PrePiH= obListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/Pre= PiMemoryAllocationLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + # + # Architectural Protocols + # + UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf + # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!if $(TPM2_ENABLE) =3D=3D TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf +!endif + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf + OvmfPkg/EnrollDefaultKeys/EnrollDefaultKeys.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # Status Code Routing + # + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + # + # Platform Driver + # + OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf + EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + OvmfPkg/VirtioScsiDxe/VirtioScsi.inf + OvmfPkg/VirtioNetDxe/VirtioNet.inf + OvmfPkg/VirtioRngDxe/VirtioRng.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + OvmfPkg/VirtioFsDxe/VirtioFsDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf { + + NULL|OvmfPkg/Library/BlobVerifierLibNull/BlobVerifierLibNull.inf + } + + # + # Networking stack + # +!include NetworkPkg/NetworkComponents.dsc.inc + + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf { + + NULL|OvmfPkg/Library/PxeBcPcdProducerLib/PxeBcPcdProducerLib.inf + } + +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf { + + NULL|OvmfPkg/Library/TlsAuthConfigLib/TlsAuthConfigLib.inf + } +!endif + + # + # SCSI Bus and Disk Driver + # + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # NVME Driver + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf { + + NULL|OvmfPkg/Library/SmbiosVersionLib/DetectSmbiosVersionLib.inf + } + OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # + # PCI support + # + OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf + OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf + OvmfPkg/Virtio10Dxe/Virtio10.inf + + # + # Video support + # + OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf + OvmfPkg/VirtioGpuDxe/VirtioGpu.inf + OvmfPkg/PlatformDxe/Platform.inf + + # + # USB Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # TPM2 support + # +!if $(TPM2_ENABLE) =3D=3D TRUE + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { + + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt= oRouterDxe.inf + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf + NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384= .inf + NULL|SecurityPkg/Library/HashInstanceLibSha512/HashInstanceLibSha512= .inf + NULL|SecurityPkg/Library/HashInstanceLibSm3/HashInstanceLibSm3.inf + } +!if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf +!endif +!endif + + # + # ACPI Support + # + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVV= irtQemu.fdf new file mode 100644 index 000000000000..e8be6f88d851 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -0,0 +1,306 @@ +# @file +# Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Platform definitions +# + +!include RiscVVirt.fdf.inc + +##########################################################################= ###### +[FD.RISCV_VIRT] +BaseAddress =3D $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdB= aseAddress +Size =3D $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdS= ize +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +0x00000000|$(CODE_SIZE) +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress|gUefiOvmfPkgTokenSpaceGuid= .PcdOvmfFvSize +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf +INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf +INF OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf + +# +# PI DXE Drivers producing Architectural Protocols (EFI Services) +# +INF UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf +INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + +# +# Multiple Console IO support +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + +# RISC-V Core Drivers +INF UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf +INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# +# FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs +# +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf +INF OvmfPkg/VirtioFsDxe/VirtioFsDxe.inf + +# +# Status Code Routing +# +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf + +# +# Platform Driver +# +INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf +INF OvmfPkg/VirtioNetDxe/VirtioNet.inf +INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf +INF OvmfPkg/VirtioRngDxe/VirtioRng.inf + +INF ShellPkg/Application/Shell/Shell.inf +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf +INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand= .inf + +# +# Bds +# +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.= inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf +INF OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf + +# +# Networking stack +# +!include NetworkPkg/Network.fdf.inc + +# +# SCSI Bus and Disk Driver +# +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + +# +# NVME Driver +# +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + +# +# SMBIOS Support +# +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf +INF OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + +# +# ACPI Support +# +INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphics= ResourceTableDxe.inf +INF OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf + +# +# PCI support +# +INF OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf +INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf +INF OvmfPkg/Virtio10Dxe/Virtio10.inf + +# +# Video support +# +INF OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf +INF OvmfPkg/VirtioGpuDxe/VirtioGpu.inf +INF OvmfPkg/PlatformDxe/Platform.inf + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +# +# TianoCore logo (splash screen) +# +INF MdeModulePkg/Logo/LogoDxe.inf + +# +# Ramdisk support +# +INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + +#INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDx= e.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +INF OvmfPkg/Sec/SecMainRiscV64.inf + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.fdf.inc new file mode 100644 index 000000000000..b0a1c3293f33 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -0,0 +1,41 @@ +## @file +# Definitions of Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE PFLASH1_BASE =3D 0x22000000 + +DEFINE FW_BASE_ADDRESS =3D $(PFLASH1_BASE) +DEFINE FW_SIZE =3D 0x00800000 +DEFINE FW_BLOCKS =3D 0x800 + +DEFINE CODE_BASE_ADDRESS =3D $(FW_BASE_ADDRESS) +DEFINE CODE_SIZE =3D 0x00740000 +DEFINE CODE_BLOCKS =3D 0x740 + +DEFINE VARS_SIZE =3D 0x000C0000 +DEFINE VARS_BLOCK_SIZE =3D 0x40000 +DEFINE VARS_BLOCKS =3D 0x3 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET =3D $(CODE_SIZE) +DEFINE VARS_LIVE_SIZE =3D 0x00040000 +DEFINE VARS_FTW_WORKING_OFFSET =3D $(VARS_OFFSET) + $(VARS_LIVE_SIZE) +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00040000 +DEFINE VARS_FTW_SPARE_OFFSET =3D $(VARS_FTW_WORKING_OFFSET) + $(VA= RS_FTW_WORKING_SIZE) +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00040000 + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency =3D 10000000 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase =3D 0x83FF0000 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize =3D 0x00010000 diff --git a/OvmfPkg/RiscVVirt/VarStore.fdf.inc b/OvmfPkg/RiscVVirt/VarStor= e.fdf.inc new file mode 100644 index 000000000000..30b170d77997 --- /dev/null +++ b/OvmfPkg/RiscVVirt/VarStore.fdf.inc @@ -0,0 +1,79 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_LIVE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3FFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97462): https://edk2.groups.io/g/devel/message/97462 Mute This Topic: https://groups.io/mt/95687649/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 11:59:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97463+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97463+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1671109056; cv=none; d=zohomail.com; s=zohoarc; b=D0Ox+9mycPbYwmOCo2pFHpHTlC3SOi2I3+0YHJP8Xw7ZWXiXJdRdkk4NaHLQj2c2TBtx0vEwj6SnbjF4FM7CNpZVEf4s+QgoRN6SiSnEAQ7hvLuhSLgMfQC5LTEktzgW0PHvcHm45rwhgU+KTwrd22vFpIHXcgg0hbRX+/2Tr/c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671109056; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8ZtIJ9rfdN4IAhLFIu9NRrYyG3mByccTWcISzXeKlJA=; b=cL5XpoKj7lim017/i/TB7+w3SkDHjRrSBsTDosXmlPomiYLaZKjNQd37z0EkSVWzRIofoAY67K5qfZ8R1CQe6eC3UJctQsSO/SOEUzv9Ff9gyYID8NtR/gUpEdB9MIopKtMg7ZkbqKF3dXnZAJfiEssEPnTJqSNQpLWUjlpdOWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97463+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671109056657993.0898251663948; Thu, 15 Dec 2022 04:57:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bZDZYY1788612xprylyb26s9; Thu, 15 Dec 2022 04:57:36 -0800 X-Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web10.132065.1671109016309471170 for ; Thu, 15 Dec 2022 04:57:36 -0800 X-Received: by mail-pf1-f172.google.com with SMTP id g1so6648063pfk.2 for ; Thu, 15 Dec 2022 04:57:35 -0800 (PST) X-Gm-Message-State: UhvG9K3kUDqbQLN2hZOirR6cx1787277AA= X-Google-Smtp-Source: AA0mqf6zPcW7T7gDHV89l0uTemf554xOa3jYxQlOAxI6CX7RUgGESCPwZAaDQAlWMXNCHqXyyEqbcA== X-Received: by 2002:a62:36c7:0:b0:573:38f0:c8f5 with SMTP id d190-20020a6236c7000000b0057338f0c8f5mr28880830pfa.28.1671109055458; Thu, 15 Dec 2022 04:57:35 -0800 (PST) X-Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.57.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:57:35 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Andrew Fish , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 23/23] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt Date: Thu, 15 Dec 2022 18:26:26 +0530 Message-Id: <20221215125626.545372-24-sunilvl@ventanamicro.com> In-Reply-To: <20221215125626.545372-1-sunilvl@ventanamicro.com> References: <20221215125626.545372-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671109056; bh=1PtC/z0JeS3QxjQK/IT83A8zcWZGnicbzjma7koYvY8=; h=Cc:Date:From:Reply-To:Subject:To; b=VhlkLcqfp99jxyE1YvctXttwhKmHLqYKg7NW36UaejXIpLRiLsCK7KrNXd9GPKPdX6I VRbAVCh4Pt/VySQQAY1xxnFxJUmvpEQDcJaF9c4QCGMtKYyh3aRED7kh1GuczmiRP4+aL ybyh6Ed2DWnfvoV+YOPwinUpBQtzrtkbSM0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671109057626100014 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RiscVVirt is created to support EDK2 for RISC-V qemu virt machine platform. Add maintainer entries. Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Signed-off-by: Sunil V L Reviewed-by: Andrei Warkentin --- Maintainers.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 6a92922258e2..74a053624491 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -540,6 +540,10 @@ F: OvmfPkg/XenResetVector/ R: Anthony Perard [tperard] R: Julien Grall [jgrall] =20 +OvmfPkg: RISC-V Qemu Virt Platform +F: OvmfPkg/RiscVVirt +R: Sunil V L [vlsunil] + PcAtChipsetPkg F: PcAtChipsetPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97463): https://edk2.groups.io/g/devel/message/97463 Mute This Topic: https://groups.io/mt/95687650/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-