From nobody Mon Feb 9 06:00:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+97430+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97430+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1671093937; cv=none; d=zohomail.com; s=zohoarc; b=YZU0RZqo024zVb8PxDPxDtucJbCCFVTisLBJrXiIy88kQIzusLqyy21gr6lwOjC38gBd0YDQMXrh2cfN/MC36211Ak7c9wepWUFnLHbsrfEa4JkWgO7VrxLWwn9SQ571f0jh5jzuljkO9onXV3uNgDJyxD3rLMXfZHodw5FuCf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671093937; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rRfCro3fMRa3Wi9OPBbUdBJso5wsUBjYup4CW8+MGy4=; b=Ei7mR4igvbN5s9EQ/UM8Si27p8+Em5fmHaLfVNBk8QOnYBrBg/3EW/gAJtdmR/sJikhpza2EGlpkEPNOACDxQeYXCf/ia+2njwlGsnfJ0ZcP+l4ZIK7FEOVbLnqBMdVwo/tdcfEqm6JN/ZrK/MYvzkB/eQO3gS87KVCzL0ERsV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+97430+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1671093937258272.4300227171327; Thu, 15 Dec 2022 00:45:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id CeOlYY1788612xFMoJ0Q9GtS; Thu, 15 Dec 2022 00:45:36 -0800 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.128326.1671093936329116914 for ; Thu, 15 Dec 2022 00:45:36 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10561"; a="298967911" X-IronPort-AV: E=Sophos;i="5.96,246,1665471600"; d="scan'208";a="298967911" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2022 00:45:17 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10561"; a="651464910" X-IronPort-AV: E=Sophos;i="5.96,246,1665471600"; d="scan'208";a="651464910" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.170.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2022 00:45:04 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min M Xu , Erdem Aktas , Gerd Hoffmann , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V1 4/6] OvmfPkg/Sec: Move TDX APs related nasm code to IntelTdxAPs.nasm Date: Thu, 15 Dec 2022 16:44:38 +0800 Message-Id: <20221215084440.481-5-min.m.xu@intel.com> In-Reply-To: <20221215084440.481-1-min.m.xu@intel.com> References: <20221215084440.481-1-min.m.xu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: ATj3fkxwInSc7qo87cXeldsox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1671093936; bh=kno0q00flupiZvOmCqMtZXqMGFvSllbzEucJ/i/pURs=; h=Cc:Date:From:Reply-To:Subject:To; b=DCi+6cbdEkH+TG1Qxqc97x3AcvsKK4bRVa+RQwvJ6zWZBUGSzuTf7cf6VjyIEPSPCv9 Zg8VXwIeGZP/cOaYQUf46vNo1DSOGUE6+5uu/l871HUhWaCaCk4xCADrUkiQ383arNzQR 99itlwtD0YuhW8bugLYbjdkxGYR+8JDIzKk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1671093937657100001 Content-Type: text/plain; charset="utf-8" From: Min M Xu BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4172 This patch moves the TDX APs nasm code from SecEntry.nasm to IntelTdxAPs.nasm. IntelTdxX64 and OvmfPkgX64 use the same nasm so that it can be easier to be managed. In the following patch there will be AcceptMemory related changes in IntelTdxAPs.nasm. Cc: Erdem Aktas Cc: Gerd Hoffmann Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm | 58 +++++++++++++++++++++++ OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm | 58 ++--------------------- OvmfPkg/Sec/X64/SecEntry.nasm | 58 ++--------------------- 3 files changed, 68 insertions(+), 106 deletions(-) create mode 100644 OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm diff --git a/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm b/OvmfPkg/IntelTdx/S= ec/X64/IntelTdxAPs.nasm new file mode 100644 index 000000000000..034ac0ee9421 --- /dev/null +++ b/OvmfPkg/IntelTdx/Sec/X64/IntelTdxAPs.nasm @@ -0,0 +1,58 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Intel TDX APs +; +; Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%include "TdxCommondefs.inc" + + ; + ; Note: BSP never gets here. APs will be unblocked by DXE + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; +ParkAp: + +do_wait_loop: + ; + ; register itself in [rsp + CpuArrivalOffset] + ; + mov rax, 1 + lock xadd dword [rsp + CpuArrivalOffset], eax + inc eax + +.check_arrival_cnt: + cmp eax, r8d + je .check_command + mov eax, dword[rsp + CpuArrivalOffset] + jmp .check_arrival_cnt + +.check_command: + mov eax, dword[rsp + CommandOffset] + cmp eax, MpProtectedModeWakeupCommandNoop + je .check_command + + cmp eax, MpProtectedModeWakeupCommandWakeup + je .do_wakeup + + ; Don't support this command, so ignore + jmp .check_command + +.do_wakeup: + ; + ; BSP sets these variables before unblocking APs + ; RAX: WakeupVectorOffset + ; RBX: Relocated mailbox address + ; RBP: vCpuId + ; + mov rax, 0 + mov eax, dword[rsp + WakeupVectorOffset] + mov rbx, [rsp + WakeupArgsRelocatedMailBox] + nop + jmp rax + jmp $ diff --git a/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm b/OvmfPkg/IntelTdx/Sec/= X64/SecEntry.nasm index 4528fec309a0..5a38c4213916 100644 --- a/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/IntelTdx/Sec/X64/SecEntry.nasm @@ -10,7 +10,6 @@ ;-------------------------------------------------------------------------= ----- =20 #include -%include "TdxCommondefs.inc" =20 DEFAULT REL SECTION .text @@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint): cmp byte[eax], VM_GUEST_TYPE_TDX jne InitStack =20 + %define TDCALL_TDINFO 1 mov rax, TDCALL_TDINFO tdcall =20 @@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint): mov rax, r9 and rax, 0xffff test rax, rax - jne ParkAp + jz InitStack + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + jmp ParkAp =20 InitStack: =20 @@ -98,54 +100,4 @@ InitStack: sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) =20 - ; - ; Note: BSP never gets here. APs will be unblocked by DXE - ; - ; R8 [31:0] NUM_VCPUS - ; [63:32] MAX_VCPUS - ; R9 [31:0] VCPU_INDEX - ; -ParkAp: - - mov rbp, r9 - -.do_wait_loop: - mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) - - ; - ; register itself in [rsp + CpuArrivalOffset] - ; - mov rax, 1 - lock xadd dword [rsp + CpuArrivalOffset], eax - inc eax - -.check_arrival_cnt: - cmp eax, r8d - je .check_command - mov eax, dword[rsp + CpuArrivalOffset] - jmp .check_arrival_cnt - -.check_command: - mov eax, dword[rsp + CommandOffset] - cmp eax, MpProtectedModeWakeupCommandNoop - je .check_command - - cmp eax, MpProtectedModeWakeupCommandWakeup - je .do_wakeup - - ; Don't support this command, so ignore - jmp .check_command - -.do_wakeup: - ; - ; BSP sets these variables before unblocking APs - ; RAX: WakeupVectorOffset - ; RBX: Relocated mailbox address - ; RBP: vCpuId - ; - mov rax, 0 - mov eax, dword[rsp + WakeupVectorOffset] - mov rbx, [rsp + WakeupArgsRelocatedMailBox] - nop - jmp rax - jmp $ +%include "IntelTdxAPs.nasm" diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index 4528fec309a0..0f82051720da 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -10,7 +10,6 @@ ;-------------------------------------------------------------------------= ----- =20 #include -%include "TdxCommondefs.inc" =20 DEFAULT REL SECTION .text @@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint): cmp byte[eax], VM_GUEST_TYPE_TDX jne InitStack =20 + %define TDCALL_TDINFO 1 mov rax, TDCALL_TDINFO tdcall =20 @@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint): mov rax, r9 and rax, 0xffff test rax, rax - jne ParkAp + jz InitStack + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + jmp ParkAp =20 InitStack: =20 @@ -98,54 +100,4 @@ InitStack: sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) =20 - ; - ; Note: BSP never gets here. APs will be unblocked by DXE - ; - ; R8 [31:0] NUM_VCPUS - ; [63:32] MAX_VCPUS - ; R9 [31:0] VCPU_INDEX - ; -ParkAp: - - mov rbp, r9 - -.do_wait_loop: - mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) - - ; - ; register itself in [rsp + CpuArrivalOffset] - ; - mov rax, 1 - lock xadd dword [rsp + CpuArrivalOffset], eax - inc eax - -.check_arrival_cnt: - cmp eax, r8d - je .check_command - mov eax, dword[rsp + CpuArrivalOffset] - jmp .check_arrival_cnt - -.check_command: - mov eax, dword[rsp + CommandOffset] - cmp eax, MpProtectedModeWakeupCommandNoop - je .check_command - - cmp eax, MpProtectedModeWakeupCommandWakeup - je .do_wakeup - - ; Don't support this command, so ignore - jmp .check_command - -.do_wakeup: - ; - ; BSP sets these variables before unblocking APs - ; RAX: WakeupVectorOffset - ; RBX: Relocated mailbox address - ; RBP: vCpuId - ; - mov rax, 0 - mov eax, dword[rsp + WakeupVectorOffset] - mov rbx, [rsp + WakeupArgsRelocatedMailBox] - nop - jmp rax - jmp $ +%include "../../IntelTdx/Sec/X64/IntelTdxAPs.nasm" --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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