From nobody Tue Apr 30 00:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95854+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95854+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1667368038; cv=none; d=zohomail.com; s=zohoarc; b=LLhrU3zBf/1ys0amDAI2nxbaZsjSadUyMobqKqDxBv/m+NndshDcMupBCtHyO1AthdI6Ma8JVenWudttWAfu2MMlKY3MUrYZXb0BMmdiFigVIT3lNP5zLrtl3MFlsbFypRgFJV2pC8dqO+W+qL9CUgalRwh96wOQPPJQUouoXHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667368038; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=KJcD88JkTXbI9Od68R7fpEaIQ5DWaB8xPC6zU1ySFlA=; b=h+JXWIJdQ67FcJc1YFbmnCc3fG21bPlRTzcsmN8kdi7ISSRMdPiFPuzUCqYrxpCBqfJmwlr05GjXubFSFLRbGAChdejPwVEFcHkxJOqZs0fW71XxA2+pwZKQsIGLuzAoC/MpyT5xponamDcBohs/nJLg34SDF6U5OQYklcT8nRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95854+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667368038189987.5707734810751; Tue, 1 Nov 2022 22:47:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XGyIYY1788612xX6IqVBsXzf; Tue, 01 Nov 2022 22:47:16 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.3084.1667368035767473787 for ; Tue, 01 Nov 2022 22:47:16 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="310423455" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="310423455" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 22:47:15 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="879349602" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="879349602" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.209.113.8]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 22:47:14 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL. Date: Tue, 1 Nov 2022 22:46:27 -0700 Message-Id: <20221102054627.1496-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: FN3eDzYcZlIXG6t7YafiFGnhx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667368036; bh=TjMwhzmYR+ubDGrIqgdjE63yWv5+ox+rolYyBrWD54k=; h=Cc:Date:From:Reply-To:Subject:To; b=MTVMCbssP2AyXiCJNTuMzEKI1mU+e3iexc8ptpS3DW/kwo6MHMlgBYBzN0hg5phSP2e iq8J3m83h2ehE4GKJA+5exS3Wvagq16aLYzCGTASESgY09gwMMMt3iStFGY9FkqdlNsaP 9fAEGS2R/zUDE5vooGpFqa6qrCxrcGFjyAk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667368038809100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4114 FSP specification supports input UPD as NULL cases which FSP will use built-in UPD region instead. FSP should not return INVALID_PARAMETER in such cases. In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed to platform FSP code to consume. In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating corresponding pointer field in FspGlobalData. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 12 ++++++++++-- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++------------------ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 40 ++++++++++++++++++++++= ++++-------------- 3 files changed, 91 insertions(+), 34 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index a44fbf2a50..5f59938518 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -44,6 +44,8 @@ FspApiCallingCheck ( // if (((UINTN)FspData !=3D MAX_ADDRESS) && ((UINTN)FspData !=3D MAX_UINT= 32)) { Status =3D EFI_UNSUPPORTED; + } else if (ApiParam =3D=3D NULL) { + Status =3D EFI_SUCCESS; } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { Status =3D EFI_INVALID_PARAMETER; } @@ -67,9 +69,13 @@ FspApiCallingCheck ( } else { if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { Status =3D EFI_UNSUPPORTED; - } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, = ApiParam))) { - Status =3D EFI_INVALID_PARAMETER; } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { + if (ApiParam =3D=3D NULL) { + Status =3D EFI_SUCCESS; + } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex= , ApiParam))) { + Status =3D EFI_INVALID_PARAMETER; + } + // // Reset MultiPhase NumberOfPhases to zero // @@ -89,6 +95,8 @@ FspApiCallingCheck ( } else { if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { Status =3D EFI_UNSUPPORTED; + } else if (ApiParam =3D=3D NULL) { + Status =3D EFI_SUCCESS; } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiP= aram))) { Status =3D EFI_INVALID_PARAMETER; } diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 61030a843b..73821ad22a 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -21,7 +21,7 @@ extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) ; Following functions will be provided in PlatformSecLib ; extern ASM_PFX(AsmGetFspBaseAddress) -extern ASM_PFX(AsmGetFspInfoHeader) +extern ASM_PFX(AsmGetFspInfoHeaderNoStack) ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation extern ASM_PFX(SecCarInit) @@ -160,6 +160,47 @@ endstruc RET_ESI_EXT mm7 %endmacro =20 +%macro CALL_EDI 1 + + mov edi, %%ReturnAddress + jmp %1 +%%ReturnAddress: + +%endmacro + +%macro CALL_EBP 1 + mov ebp, %%ReturnAddress + jmp %1 +%%ReturnAddress: +%endmacro + +%macro RET_EBP 0 + jmp ebp ; restore EIP from EBP +%endmacro + +; +; Load UPD region pointer in ECX +; +global ASM_PFX(LoadUpdPointerToECX) +ASM_PFX(LoadUpdPointerToECX): + ; + ; esp + 4 is input UPD parameter + ; If esp + 4 is NULL the default UPD should be used + ; ecx will be the UPD region that should be used + ; + mov ecx, dword [esp + 4] + cmp ecx, 0 + jnz ParamValid + + ; + ; Fall back to default UPD region + ; + CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack) + mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress + add ecx, DWORD [eax + 024h] ; Get Cfg Region base address =3D= FsptImageBaseAddress + CfgRegionOffset +ParamValid: + RET_EBP + ; ; @todo: The strong/weak implementation does not work. ; This needs to be reviewed later. @@ -187,10 +228,9 @@ endstruc global ASM_PFX(LoadMicrocodeDefault) ASM_PFX(LoadMicrocodeDefault): ; Inputs: - ; esp -> LoadMicrocodeParams pointer + ; ecx -> UPD region contains LoadMicrocodeParams pointer ; Register Usage: - ; esp Preserved - ; All others destroyed + ; All are destroyed ; Assumptions: ; No memory available, stack is hard-coded and used for return address ; Executed by SBSP and NBSP @@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault): ; movd ebp, mm7 =20 + mov esp, ecx ; ECX has been assigned to UPD region cmp esp, 0 jz ParamError - mov eax, dword [esp + 4] ; Parameter pointer - cmp eax, 0 - jz ParamError - mov esp, eax =20 ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k @@ -444,13 +481,15 @@ Done: Exit2: jmp ebp =20 - +; +; EstablishStackFsp: EDI should be preserved cross this function +; global ASM_PFX(EstablishStackFsp) ASM_PFX(EstablishStackFsp): ; ; Save parameter pointer in edx ; - mov edx, dword [esp + 4] + mov edx, ecx ; ECX has been assigned to UPD region =20 ; ; Enable FSP STACK @@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi): SAVE_EAX SAVE_EDX =20 - ; - ; Check Parameter - ; - mov eax, dword [esp + 4] - cmp eax, 0 - mov eax, 80000002h - jz TempRamInitExit - ; ; Sec Platform Init ; + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param CALL_MMX ASM_PFX(SecPlatformInit) cmp eax, 0 jnz TempRamInitExit =20 ; Load microcode LOAD_ESP + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param CALL_MMX ASM_PFX(LoadMicrocodeDefault) SXMMN xmm6, 3, eax ;Save microcode return status in ECX-S= LOT 3 in xmm6. ;@note If return value eax is not 0, microcode did not load, but continu= e and attempt to boot. =20 ; Call Sec CAR Init LOAD_ESP + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param CALL_MMX ASM_PFX(SecCarInit) cmp eax, 0 jnz TempRamInitExit =20 LOAD_ESP + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + mov edi, ecx ; Save UPD param to EDI for later= code use CALL_MMX ASM_PFX(EstablishStackFsp) cmp eax, 0 jnz TempRamInitExit =20 LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error f= rom ECX-SLOT 3 in xmm6. + SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 = in xmm6. =20 TempRamInitExit: mov bl, al ; save al data in bl diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index 7dd89c531a..cdebe90fab 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -21,7 +21,7 @@ extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) ; Following functions will be provided in PlatformSecLib ; extern ASM_PFX(AsmGetFspBaseAddress) -extern ASM_PFX(AsmGetFspInfoHeader) +extern ASM_PFX(AsmGetFspInfoHeaderNoStack) ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation extern ASM_PFX(SecCarInit) @@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24 .size: endstruc =20 +%macro CALL_RDI 1 + + mov rdi, %%ReturnAddress + jmp %1 +%%ReturnAddress: + +%endmacro + ; ; @todo: The strong/weak implementation does not work. ; This needs to be reviewed later. @@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault): ; Inputs: ; rcx -> LoadMicrocodeParams pointer ; Register Usage: - ; rsp Preserved - ; All others destroyed + ; All are destroyed ; Assumptions: ; No memory available, stack is hard-coded and used for return address ; Executed by SBSP and NBSP @@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi): ENABLE_SSE ENABLE_AVX ; - ; Save Input Parameter in YMM10 - ; - SAVE_RCX - ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6 ; SAVE_REGS @@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi): ; SAVE_BFV rbp =20 + ; + ; Save Input Parameter in YMM10 + ; + cmp rcx, 0 + jnz ParamValid + + ; + ; Fall back to default UPD + ; + CALL_RDI ASM_PFX(AsmGetFspInfoHeaderNoStack) + xor rcx, rcx + mov ecx, DWORD [rax + 01Ch] ; Read FsptImageBaseAddress + add ecx, DWORD [rax + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset +ParamValid: + SAVE_RCX + ; ; Save timestamp into YMM6 ; @@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi): or rax, rdx SAVE_TS rax =20 - ; - ; Check Parameter - ; - cmp rcx, 0 - mov rcx, 08000000000000002h - jz TempRamInitExit - ; ; Sec Platform Init ; --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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