From nobody Sun Feb 8 12:39:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95729+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95729+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136540; cv=none; d=zohomail.com; s=zohoarc; b=nUXDgUCQOw4Q+m1juDNDSXGQc9oCs2CG3l7MtVCrQFkpRjI8sgnlnZzDZcQbIHTpaxuezWwPfqNnVC4jHpixeiEKGyZ5sr22qNHkFzBvngw/dAxJo5ZCvcKp7DoYPFy74PN1Lvw9rP6M0sJh3tzbeEQHWUYHMLAFUC7hWGNaCdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136540; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RP62DD4KODIjODbFyjOnQv6XKj/1vqsdJ/SKG2Jtmas=; b=FFyUTzCr7URFmWezSHdJhpZfhAnYalszSe7HsQBR9J+mmirSNQDXva4eiFRT3yfPOinfTR492Vm9f3EC8HAH2X9GdVycqj70m8Xr/6F2etV7wjQPflkf+QoFKqK+gr+WcNIl+FIDcIfbwqfzqTZsNoKE/s0l43fkzQvAX6rwEjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95729+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136540268536.7266928080135; Sun, 30 Oct 2022 06:29:00 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JhItYY1788612xQqizLDaPHc; Sun, 30 Oct 2022 06:28:59 -0700 X-Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) by mx.groups.io with SMTP id smtpd.web11.8320.1667136539256879824 for ; Sun, 30 Oct 2022 06:28:59 -0700 X-Received: by mail-pg1-f173.google.com with SMTP id 128so8652903pga.1 for ; Sun, 30 Oct 2022 06:28:59 -0700 (PDT) X-Gm-Message-State: EsIT5iqu05jjbum8tZB6EnW9x1787277AA= X-Google-Smtp-Source: AMsMyM6o/4f9LzmbMUtR/2PL8tO6N8RHF8nF99eGPcN1qr+ya+RhEJd5iBqGu2ac9XylRYNHDh326g== X-Received: by 2002:a63:4517:0:b0:464:4f06:a0f1 with SMTP id s23-20020a634517000000b004644f06a0f1mr7888320pga.509.1667136538507; Sun, 30 Oct 2022 06:28:58 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:28:58 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 03/30] MdePkg/BaseLib: RISC-V: Add few more helper functions Date: Sun, 30 Oct 2022 18:58:15 +0530 Message-Id: <20221030132842.54077-4-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136539; bh=steDiE40rATpWpXSRccqewpiJOx5uIcBWAwxGvdNHok=; h=Cc:Date:From:Reply-To:Subject:To; b=DgAHl2qdvgd75ncD784neMlHsPHWQ1sfpaa9poazq69OwEdVnjpHpwBrTT1/rkPOUvI i8ERaOSuPrPtd0tmgJy+mCILBK9cdkq2c4MRhqlOVVVZzUoDa+5TzNTxbjSBSyt6PQCeG xx/uce5dWhMm8cnsAOEjH3t9HkuPFFb/SrM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136541984100013 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Daniel Schaefer Signed-off-by: Sunil V L --- MdePkg/Library/BaseLib/BaseLib.inf | 2 + MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++ MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++-- 5 files changed, 155 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 9ed46a584a14..babbee1ca08b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,8 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuScratch.S | GCC + RiscV64/ReadTimer.S | GCC =20 [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index f3f59f21c2ea..b4f4e45a1486 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -151,6 +151,56 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID + RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID + RiscVSetSupervisorStvec ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +UINT64 +RiscVGetSupervisorTrapCause ( + VOID + ); + +VOID + RiscVSetSupervisorAddressTranslationRegister ( + UINT64 + ); + +UINT64 +RiscVReadTimer ( + VOID + ); + +VOID +RiscVEnableTimerInterrupt ( + VOID + ); + +VOID +RiscVDisableTimerInterrupt ( + VOID + ); + +VOID +RiscVClearPendingTimerInterrupt ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/B= aseLib/RiscV64/CpuScratch.S new file mode 100644 index 000000000000..dd7adc21eb07 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/Ba= seLib/RiscV64/ReadTimer.S new file mode 100644 index 000000000000..39a06efa51ef --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// Read CPU timer +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Read TIME CSR. +// @retval a0 : 64-bit timer. +// +ASM_FUNC (RiscVReadTimer) + csrr a0, CSR_TIME + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S index 87b3468fc7fd..6a1b90a7e45c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -8,13 +8,13 @@ // //------------------------------------------------------------------------= ------ =20 +#include + ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) =20 -#define SSTATUS_SIE 0x00000002 -#define CSR_SSTATUS 0x100 - #define SSTATUS_SPP_BIT_POSITION 8 +#define SSTATUS_SPP_BIT_POSITION 8 =20 // // This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap: ret =20 // +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, CSR_STVEC, a0 + ret + +// +// Get Supervisor mode trap vector. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, CSR_STVEC + ret + +// +// Get Supervisor trap cause CSR. +// +ASM_FUNC (RiscVGetSupervisorTrapCause) + csrrs a0, CSR_SCAUSE, 0 + ret +// // This routine returns supervisor mode interrupt // status. // -ASM_PFX(RiscVGetSupervisorModeInterrupts): +ASM_FUNC (RiscVGetSupervisorModeInterrupts) csrr a0, CSR_SSTATUS andi a0, a0, SSTATUS_SIE ret =20 +// +// This routine disables supervisor mode timer interrupt +// +ASM_FUNC (RiscVDisableTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIE, a0 + ret + +// +// This routine enables supervisor mode timer interrupt +// +ASM_FUNC (RiscVEnableTimerInterrupt) + li a0, SIP_STIP + csrs CSR_SIE, a0 + ret + +// +// This routine clears pending supervisor mode timer interrupt +// +ASM_FUNC (RiscVClearPendingTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIP, a0 + ret --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95729): https://edk2.groups.io/g/devel/message/95729 Mute This Topic: https://groups.io/mt/94664294/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-