From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95727+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95727+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136535; cv=none; d=zohomail.com; s=zohoarc; b=C0I9eesMRdXSW0N0aoZI7bEyp4MgP2idWPKzZ0txfRK95qzhxeom6tcOsT+LJLGrPd7HZ787Qm7Yyvc2pV0y1Rf1Oc1zRXAvhmzp4QitVgwc7LGdo95iEcgMboARcP/KdELIhC5CqmSpeDiEMLpzxNqeloR8Nu+OyT3YfD/xLSs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136535; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QOW/OmL3oYfr0Ngm4c11dVzd8LBS/BcqyUQZbGykAOo=; b=eerH6zOjnrymHMK97WZRLcUbRrAZUCdrTHH2/wdOofDS3I6Xqmm3Z9v21cSFO6i0egRV2jSsk5jtqoXOZcTNDoXR5i83npkvhZJVViRW2MZoXrXkXcHxAnKrdzmw8W8Q9mOYleNwV2S/blsC+LCcSkqJJYFufUHF04/F2tGBkeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95727+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136535864876.4196130030584; Sun, 30 Oct 2022 06:28:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FZj6YY1788612xA4GOsFCeSc; Sun, 30 Oct 2022 06:28:55 -0700 X-Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web11.8318.1667136534610489128 for ; Sun, 30 Oct 2022 06:28:54 -0700 X-Received: by mail-pj1-f53.google.com with SMTP id u8-20020a17090a5e4800b002106dcdd4a0so13778239pji.1 for ; Sun, 30 Oct 2022 06:28:54 -0700 (PDT) X-Gm-Message-State: nOAIaenP8Pz3oC3P9JZuVAbQx1787277AA= X-Google-Smtp-Source: AMsMyM5khPr4iH3cIZgy1PW52Fu9WQVd+rqkpqN0C4sSiTPUHdtbNcREphtUUchPTiC/3py/NEwnXA== X-Received: by 2002:a17:902:d490:b0:186:c544:8ac7 with SMTP id c16-20020a170902d49000b00186c5448ac7mr9309930plg.158.1667136533863; Sun, 30 Oct 2022 06:28:53 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:28:53 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 01/30] MdePkg/Register: Add register definition header files for RISC-V Date: Sun, 30 Oct 2022 18:58:13 +0530 Message-Id: <20221030132842.54077-2-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136535; bh=AinpblINJO70HrGGl+oY8Bm2AFd0uO2a6aI7T9VuG1I=; h=Cc:Date:From:Reply-To:Subject:To; b=n5xBW+0zvtrh5zzSBLKM0pwejRGWxUS5hsn1tqqXX3vraHEQ5wJkZPDbh+nK3UP0ZM2 olY5vqBGaUC8yY3+OrM/dKUCDowG8FPKR69v2kYhyIllhC1kJA9l/3dskqrn7zpN/dSbv J4MAQvyfMBpGj6KE5aAZYCCsweQ/eV1TICI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136537944100007 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 ++++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ 2 files changed, 144 insertions(+) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..5c2989b797bf --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,119 @@ +/** @file + RISC-V CSR encodings + + Copyright (c) 2019, Western Digital Corporation or its affiliates. All r= ights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_ENCODING_H_ +#define RISCV_ENCODING_H_ + +#define MSTATUS_SIE 0x00000002UL +#define MSTATUS_MIE 0x00000008UL +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE 0x00000040UL +#define MSTATUS_MPIE 0x00000080UL +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (1UL << IRQ_S_SOFT) +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) +#define MIP_MSIP (1UL << IRQ_M_SOFT) +#define MIP_STIP (1UL << IRQ_S_TIMER) +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) +#define MIP_MTIP (1UL << IRQ_M_TIMER) +#define MIP_SEIP (1UL << IRQ_S_EXT) +#define MIP_VSEIP (1UL << IRQ_VS_EXT) +#define MIP_MEIP (1UL << IRQ_M_EXT) +#define MIP_SGEIP (1UL << IRQ_S_GEXT) +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0UL +#define PRV_S 1UL +#define PRV_M 3UL + +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL + +#define SATP_MODE_OFF 0UL +#define SATP_MODE_SV32 1UL +#define SATP_MODE_SV39 8UL +#define SATP_MODE_SV48 9UL +#define SATP_MODE_SV57 10UL +#define SATP_MODE_SV64 11UL + +#define SATP_MODE SATP64_MODE + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* Trap/Exception Causes */ +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..ee5c2ba60377 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,25 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_IMPL_H_ +#define RISCV_IMPL_H_ + +#include + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95727): https://edk2.groups.io/g/devel/message/95727 Mute This Topic: https://groups.io/mt/94664292/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95728+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95728+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136537; cv=none; d=zohomail.com; s=zohoarc; b=ikd/syMJw7MvtESdO89e3b4bLRVxLryIhFRpZfFk2jJKM1WwlUQGKUPg/hkqZEH7rn2cw9rkzUslhNejzLKMCr6aHSkdUtr/5Ge7ajoMInZ5wIUJLv2H1deErWkru0hraUvIKB8GwjV46XSwuemTttY0e/WnE2VlrbboRx84t+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136537; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OTXGJ56V/5IehWGN83oU0ZYttHDd7j8dL6QV8d21vPY=; b=QJKaY1nUBO59PjT79j76iUJwqZvdGdXX4NoKTFgp66OjG++wam0EoHJXJyjMPYj1ykiLD//pGFzG/olSXNwdyk9RVU4Lc4QXH1iiA7HRdTZKwFWISMjhU+8uiJ1/ufNWbjoCExGyBY24XkhcWXk2Eh/AIuz2GTuJ7TF7C/j097A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95728+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136537805214.1616677219739; Sun, 30 Oct 2022 06:28:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id txiFYY1788612xRBtF1wlfWX; Sun, 30 Oct 2022 06:28:57 -0700 X-Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) by mx.groups.io with SMTP id smtpd.web11.8319.1667136536816924537 for ; Sun, 30 Oct 2022 06:28:56 -0700 X-Received: by mail-pf1-f171.google.com with SMTP id b29so8538037pfp.13 for ; Sun, 30 Oct 2022 06:28:56 -0700 (PDT) X-Gm-Message-State: tVoIH8FJjvplA0w4wluvhu0lx1787277AA= X-Google-Smtp-Source: AMsMyM5Mt369aib2ocD6C7g4bB7RUHg7JaWmiqEEpTYuPOxHoecE7rbHvmQhWRBy5JdZsX6ZP2GNHQ== X-Received: by 2002:a05:6a00:158d:b0:56d:59f0:d273 with SMTP id u13-20020a056a00158d00b0056d59f0d273mr1880601pfk.51.1667136536142; Sun, 30 Oct 2022 06:28:56 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:28:55 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 02/30] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Date: Sun, 30 Oct 2022 18:58:14 +0530 Message-Id: <20221030132842.54077-3-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136537; bh=py3jtKwTcP7cuilLKXPHm3+xb5oVedFRRreP/fwXTO4=; h=Cc:Date:From:Reply-To:Subject:To; b=OHSkJ/tzZnqrzbFDghrSrlUNy896ZUdlarmvqRfQEL4nBN1vDJkdWxgHvq1lNXYjVWG y2/BQu4NlKOAxqawp7MlM9IDNsrVi3Jtp64rd8eyvR7EagIWDFq746l2NG7Kid8hUnfMU t4KskgQREn6qWCHJb5g4U/wST460GBQfOvs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136539961100011 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- MdePkg/MdePkg.dec | 5 +++ MdePkg/Include/Protocol/RiscVBootProtocol.h | 34 ++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 4c81cbd75ab2..dda1d5e15b9f 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -1918,6 +1918,11 @@ [Protocols] # ## Include/Protocol/ShellDynamicCommand.h gEfiShellDynamicCommandProtocolGuid =3D { 0x3c7200e9, 0x005f, 0x4ea4, {= 0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }} + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid =3D { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x9= 5, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }} =20 # # [Error.gEfiMdePkgTokenSpaceGuid] diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h b/MdePkg/Include/P= rotocol/RiscVBootProtocol.h new file mode 100644 index 000000000000..ed223b852d34 --- /dev/null +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,34 @@ +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + @par Revision Reference: + The protocol specification can be found at + https://github.com/riscv-non-isa/riscv-uefi + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_BOOT_PROTOCOL_H_ +#define RISCV_BOOT_PROTOCOL_H_ + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 +#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID)( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95728): https://edk2.groups.io/g/devel/message/95728 Mute This Topic: https://groups.io/mt/94664293/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95729+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95729+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136540; cv=none; d=zohomail.com; s=zohoarc; b=nUXDgUCQOw4Q+m1juDNDSXGQc9oCs2CG3l7MtVCrQFkpRjI8sgnlnZzDZcQbIHTpaxuezWwPfqNnVC4jHpixeiEKGyZ5sr22qNHkFzBvngw/dAxJo5ZCvcKp7DoYPFy74PN1Lvw9rP6M0sJh3tzbeEQHWUYHMLAFUC7hWGNaCdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136540; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RP62DD4KODIjODbFyjOnQv6XKj/1vqsdJ/SKG2Jtmas=; b=FFyUTzCr7URFmWezSHdJhpZfhAnYalszSe7HsQBR9J+mmirSNQDXva4eiFRT3yfPOinfTR492Vm9f3EC8HAH2X9GdVycqj70m8Xr/6F2etV7wjQPflkf+QoFKqK+gr+WcNIl+FIDcIfbwqfzqTZsNoKE/s0l43fkzQvAX6rwEjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95729+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136540268536.7266928080135; Sun, 30 Oct 2022 06:29:00 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JhItYY1788612xQqizLDaPHc; Sun, 30 Oct 2022 06:28:59 -0700 X-Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) by mx.groups.io with SMTP id smtpd.web11.8320.1667136539256879824 for ; Sun, 30 Oct 2022 06:28:59 -0700 X-Received: by mail-pg1-f173.google.com with SMTP id 128so8652903pga.1 for ; Sun, 30 Oct 2022 06:28:59 -0700 (PDT) X-Gm-Message-State: EsIT5iqu05jjbum8tZB6EnW9x1787277AA= X-Google-Smtp-Source: AMsMyM6o/4f9LzmbMUtR/2PL8tO6N8RHF8nF99eGPcN1qr+ya+RhEJd5iBqGu2ac9XylRYNHDh326g== X-Received: by 2002:a63:4517:0:b0:464:4f06:a0f1 with SMTP id s23-20020a634517000000b004644f06a0f1mr7888320pga.509.1667136538507; Sun, 30 Oct 2022 06:28:58 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:28:58 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 03/30] MdePkg/BaseLib: RISC-V: Add few more helper functions Date: Sun, 30 Oct 2022 18:58:15 +0530 Message-Id: <20221030132842.54077-4-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136539; bh=steDiE40rATpWpXSRccqewpiJOx5uIcBWAwxGvdNHok=; h=Cc:Date:From:Reply-To:Subject:To; b=DgAHl2qdvgd75ncD784neMlHsPHWQ1sfpaa9poazq69OwEdVnjpHpwBrTT1/rkPOUvI i8ERaOSuPrPtd0tmgJy+mCILBK9cdkq2c4MRhqlOVVVZzUoDa+5TzNTxbjSBSyt6PQCeG xx/uce5dWhMm8cnsAOEjH3t9HkuPFFb/SrM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136541984100013 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Daniel Schaefer Signed-off-by: Sunil V L --- MdePkg/Library/BaseLib/BaseLib.inf | 2 + MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++ MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++-- 5 files changed, 155 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 9ed46a584a14..babbee1ca08b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,8 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuScratch.S | GCC + RiscV64/ReadTimer.S | GCC =20 [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index f3f59f21c2ea..b4f4e45a1486 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -151,6 +151,56 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID + RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID + RiscVSetSupervisorStvec ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +UINT64 +RiscVGetSupervisorTrapCause ( + VOID + ); + +VOID + RiscVSetSupervisorAddressTranslationRegister ( + UINT64 + ); + +UINT64 +RiscVReadTimer ( + VOID + ); + +VOID +RiscVEnableTimerInterrupt ( + VOID + ); + +VOID +RiscVDisableTimerInterrupt ( + VOID + ); + +VOID +RiscVClearPendingTimerInterrupt ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/B= aseLib/RiscV64/CpuScratch.S new file mode 100644 index 000000000000..dd7adc21eb07 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------= ------ +// +// CPU scratch register related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/Ba= seLib/RiscV64/ReadTimer.S new file mode 100644 index 000000000000..39a06efa51ef --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------ +// +// Read CPU timer +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include + +.data +.align 3 +.section .text + +// +// Read TIME CSR. +// @retval a0 : 64-bit timer. +// +ASM_FUNC (RiscVReadTimer) + csrr a0, CSR_TIME + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S index 87b3468fc7fd..6a1b90a7e45c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -8,13 +8,13 @@ // //------------------------------------------------------------------------= ------ =20 +#include + ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) =20 -#define SSTATUS_SIE 0x00000002 -#define CSR_SSTATUS 0x100 - #define SSTATUS_SPP_BIT_POSITION 8 +#define SSTATUS_SPP_BIT_POSITION 8 =20 // // This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap: ret =20 // +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, CSR_STVEC, a0 + ret + +// +// Get Supervisor mode trap vector. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, CSR_STVEC + ret + +// +// Get Supervisor trap cause CSR. +// +ASM_FUNC (RiscVGetSupervisorTrapCause) + csrrs a0, CSR_SCAUSE, 0 + ret +// // This routine returns supervisor mode interrupt // status. // -ASM_PFX(RiscVGetSupervisorModeInterrupts): +ASM_FUNC (RiscVGetSupervisorModeInterrupts) csrr a0, CSR_SSTATUS andi a0, a0, SSTATUS_SIE ret =20 +// +// This routine disables supervisor mode timer interrupt +// +ASM_FUNC (RiscVDisableTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIE, a0 + ret + +// +// This routine enables supervisor mode timer interrupt +// +ASM_FUNC (RiscVEnableTimerInterrupt) + li a0, SIP_STIP + csrs CSR_SIE, a0 + ret + +// +// This routine clears pending supervisor mode timer interrupt +// +ASM_FUNC (RiscVClearPendingTimerInterrupt) + li a0, SIP_STIP + csrc CSR_SIP, a0 + ret --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95729): https://edk2.groups.io/g/devel/message/95729 Mute This Topic: https://groups.io/mt/94664294/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95730+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95730+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136542; cv=none; d=zohomail.com; s=zohoarc; b=Y89D4vpUUmXBk0wU2slntXNRFxvOFDhRbijGtxvaoa+DHlzQ+RXLxP1lbj7RfeiLZELh5ZkpCWbB8/XpaNqH4McaT3wkSvBMzjycy49RSIhldlaES7IWsS+ZVzqgwxN/6kyvM4EUPvwg8dVD5HFkPe+ymUkWhrVX3ltTPCp4RyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136542; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xINH9sIfBEbvGLBy/sTFhNsetTKndUUJAjt6ql7Y/SE=; b=UPncfo7SBqB88JVuN1wAoHT3qEZD/JXEIKBVS/4PYjquiL5B/TdmPjrrm2a1CUMaZCs+SyWWCMyB5EFzqvWKjquxaI1N1bUKLFCOS5ubEPI6m+CkK+pYE94/FMEFunNmU44ONfFjB9EO4INPr7ykQxOpuRakd0dDKdV0+7vDrg8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95730+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136542502714.331940968686; Sun, 30 Oct 2022 06:29:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id z2I3YY1788612xUDJDRAr30s; Sun, 30 Oct 2022 06:29:02 -0700 X-Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mx.groups.io with SMTP id smtpd.web09.8111.1667136541534586800 for ; Sun, 30 Oct 2022 06:29:01 -0700 X-Received: by mail-pj1-f44.google.com with SMTP id o7so5153621pjj.1 for ; Sun, 30 Oct 2022 06:29:01 -0700 (PDT) X-Gm-Message-State: Gw8Q0Y5rol9baLvs1WIfx9i4x1787277AA= X-Google-Smtp-Source: AMsMyM5mvofBBL1hx2IjtLcMHDZVzZ5xUh7DML8UVn2gloUh7lQLsxqE1xVd6vgQKSJuxop7TL9gGw== X-Received: by 2002:a17:902:cf03:b0:17e:c7a:678e with SMTP id i3-20020a170902cf0300b0017e0c7a678emr9081577plg.10.1667136540812; Sun, 30 Oct 2022 06:29:00 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:00 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 04/30] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Date: Sun, 30 Oct 2022 18:58:16 +0530 Message-Id: <20221030132842.54077-5-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136542; bh=GVsHlDmfvMOvIOnFEo27VyA1UH1+xde7j/ZyFzGrZR0=; h=Cc:Date:From:Reply-To:Subject:To; b=GlMGXfPG4GEt0MIMRfVdW2Uc7zXy65h3WOwhFomZKRvkBhMuIdNfpN7tabO80KYoViR cF4D+nji1ojv12A7/6QSL4ZpfBpqatXoXMiM9GWdrFgsxpSV2svK3/BAkMQZsiD6GqQfm li0I1tpRarA4DFnuHezdJ8+dwUIm7IUp2V0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136544034100017 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This library is required to make SBI ecalls from the S-mode EDK2. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang --- MdePkg/MdePkg.dec | 4 + MdePkg/MdePkg.dsc | 3 + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf | 25 +++ MdePkg/Include/Library/BaseRiscVSbiLib.h | 127 +++++++++++ MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 227 +++++++++++++++++= +++ 5 files changed, 386 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index dda1d5e15b9f..df681b2b99a5 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -311,6 +311,10 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides function to support TDX processing. TdxLib|Include/Library/TdxLib.h =20 +[LibraryClasses.RISCV64] + ## @libraryclass Provides function to make ecalls to SBI + BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h + [Guids] # # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 493a13ec9197..c7961a9b03f1 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -189,4 +189,7 @@ [Components.ARM, Components.AARCH64] MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf =20 +[Components.RISCV64] + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + [BuildOptions] diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf b/MdePkg/Li= brary/BaseRiscVSbiLib/BaseRiscVSbiLib.inf new file mode 100644 index 000000000000..d03132bf01c1 --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf @@ -0,0 +1,25 @@ +## @file +# RISC-V Library to call SBI ecalls +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D BaseRiscVSbiLib + FILE_GUID =3D D742CF3D-E600-4009-8FB5-318073008508 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSbiLib + +[Sources] + BaseRiscVSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib diff --git a/MdePkg/Include/Library/BaseRiscVSbiLib.h b/MdePkg/Include/Libr= ary/BaseRiscVSbiLib.h new file mode 100644 index 000000000000..e9886187526a --- /dev/null +++ b/MdePkg/Include/Library/BaseRiscVSbiLib.h @@ -0,0 +1,127 @@ +/** @file + Library to call the RISC-V SBI ecalls + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Hart - Hardware Thread, similar to a CPU core + + Currently, EDK2 needs to call SBI only to set the time and to do system = reset. + +**/ + +#ifndef RISCV_SBI_LIB_H_ +#define RISCV_SBI_LIB_H_ + +#include + +/* SBI Extension IDs */ +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 + +/* SBI function IDs for TIME extension*/ +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for SRST extension */ +#define SBI_EXT_SRST_RESET 0x0 + +#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0 +#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1 +#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2 +#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT + +#define SBI_SRST_RESET_REASON_NONE 0x0 +#define SBI_SRST_RESET_REASON_SYSFAIL 0x1 + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree +} EFI_RISCV_FIRMWARE_CONTEXT; + +// +// EDK2 OpenSBI firmware extension return status. +// +typedef struct { + UINTN Error; ///< SBI status code + UINTN Value; ///< Value returned +} SBI_RET; + +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ); + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ); + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ); + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ); + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ); + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ); + +#endif diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c b/MdePkg/Libr= ary/BaseRiscVSbiLib/BaseRiscVSbiLib.c new file mode 100644 index 000000000000..5db95a008069 --- /dev/null +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c @@ -0,0 +1,227 @@ +/** @file + Instance of the SBI ecall library. + + It allows calling an SBI function via an ecall from S-Mode. + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +// +// Maximum arguments for SBI ecall +// It's possible to pass more but no SBI call uses more as of SBI 0.2. +// The additional arguments would have to be passed on the stack instead o= f as +// registers, like it's done now. +// +#define SBI_CALL_MAX_ARGS 6 + +/** + Call SBI call using ecall instruction. + + Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS. + + @param[in] ExtId SBI extension ID. + @param[in] FuncId SBI function ID. + @param[in] NumArgs Number of arguments to pass to the ecall. + @param[in] ... Argument list for the ecall. + + @retval Returns SBI_RET structure with value and error code. + +**/ +STATIC +SBI_RET +EFIAPI +SbiCall ( + IN UINTN ExtId, + IN UINTN FuncId, + IN UINTN NumArgs, + ... + ) +{ + UINTN I; + SBI_RET Ret; + UINTN Args[SBI_CALL_MAX_ARGS]; + VA_LIST ArgList; + + VA_START (ArgList, NumArgs); + + ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS); + + for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) { + if (I < NumArgs) { + Args[I] =3D VA_ARG (ArgList, UINTN); + } else { + // Default to 0 for all arguments that are not given + Args[I] =3D 0; + } + } + + VA_END (ArgList); + + register UINTN a0 asm ("a0") =3D Args[0]; + register UINTN a1 asm ("a1") =3D Args[1]; + register UINTN a2 asm ("a2") =3D Args[2]; + register UINTN a3 asm ("a3") =3D Args[3]; + register UINTN a4 asm ("a4") =3D Args[4]; + register UINTN a5 asm ("a5") =3D Args[5]; + register UINTN a6 asm ("a6") =3D (UINTN)(FuncId); + register UINTN a7 asm ("a7") =3D (UINTN)(ExtId); + + asm volatile ("ecall" \ + : "+r" (a0), "+r" (a1) \ + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \ + : "memory"); \ + Ret.Error =3D a0; + Ret.Value =3D a1; + return Ret; +} + +/** + Translate SBI error code to EFI status. + + @param[in] SbiError SBI error code + @retval EFI_STATUS +**/ +STATIC +EFI_STATUS +EFIAPI +TranslateError ( + IN UINTN SbiError + ) +{ + switch (SbiError) { + case SBI_SUCCESS: + return EFI_SUCCESS; + case SBI_ERR_FAILED: + return EFI_DEVICE_ERROR; + break; + case SBI_ERR_NOT_SUPPORTED: + return EFI_UNSUPPORTED; + break; + case SBI_ERR_INVALID_PARAM: + return EFI_INVALID_PARAMETER; + break; + case SBI_ERR_DENIED: + return EFI_ACCESS_DENIED; + break; + case SBI_ERR_INVALID_ADDRESS: + return EFI_LOAD_ERROR; + break; + case SBI_ERR_ALREADY_AVAILABLE: + return EFI_ALREADY_STARTED; + break; + default: + // + // Reaches here only if SBI has defined a new error type + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + break; + } +} + +/** + Clear pending timer interrupt bit and set timer for next event after Tim= e. + + To clear the timer without scheduling a timer event, set Time to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] Time The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ) +{ + SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time); +} + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ) +{ + SBI_RET Ret; + + Ret =3D SbiCall ( + SBI_EXT_SRST, + SBI_EXT_SRST_RESET, + 2, + ResetType, + ResetReason + ); + + return TranslateError (Ret.Error); +} + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ) +{ + *FirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT *)RiscVGetSupervisorScr= atch (); +} + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + RiscVSetSupervisorScratch ((UINT64)FirmwareContext); +} + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + GetFirmwareContext (FirmwareContextPtr); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + SetFirmwareContext (FirmwareContextPtr); +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95730): https://edk2.groups.io/g/devel/message/95730 Mute This Topic: https://groups.io/mt/94664296/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95731+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95731+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136544; cv=none; d=zohomail.com; s=zohoarc; b=Rv/5VodbxaBdSMhP5rR+7Owk90fKTT207QRJ7bcgxj8tMf70usoGOW4EwTMa8NWSxP3Mn/XB74TzzDPVmSYHX6cePnfn1XApczq/Dh1VV4fZP9Wnh/sosSn5DOaeNbAfLRxHaroyctJPwpQGP4j4utonmd+8oUY9f+ZFPh+54TE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136544; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=lW4esnh50cfw7vdIiFG15c60m7wX0P5YwoWhdCxm6Os=; b=MlBT/xN8LE4mYPTnulpc0v+0fQnb82EL4V4jVLpgqob/surgwXDmhtq00rwj2E9kGMQvN/EKR33VTgEQXe3cxmpTqjLuhzRBUf2Y08PXcTNBp3J1cjy321m7cgNK7VpP/vgYsA4yuJU2Sc5FrPhBS538ykjSoBz20uzir05ZnoE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95731+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136544818541.6655771380161; Sun, 30 Oct 2022 06:29:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cVv2YY1788612xrFzUbegMzT; Sun, 30 Oct 2022 06:29:04 -0700 X-Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mx.groups.io with SMTP id smtpd.web08.8057.1667136543893761731 for ; Sun, 30 Oct 2022 06:29:04 -0700 X-Received: by mail-pj1-f44.google.com with SMTP id z5-20020a17090a8b8500b00210a3a2364fso11096340pjn.0 for ; Sun, 30 Oct 2022 06:29:03 -0700 (PDT) X-Gm-Message-State: U9VyZea64Stf6lK8pSjhdIAvx1787277AA= X-Google-Smtp-Source: AMsMyM4oYHzlGKFbdgIVcnjMdxNZVRy54wswLI0d6SuQANa3Fi4UkJI3PTkIWt4jlb7wAW+VONmkTA== X-Received: by 2002:a17:90a:3ee5:b0:213:8550:72e3 with SMTP id k92-20020a17090a3ee500b00213855072e3mr16276316pjc.49.1667136543190; Sun, 30 Oct 2022 06:29:03 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:02 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 05/30] OvmfPkg/PlatformInitLib: Refactor to allow other architectures Date: Sun, 30 Oct 2022 18:58:17 +0530 Message-Id: <20221030132842.54077-6-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136544; bh=3cFLmP0freXrXEN5JLCf7xyLoKSWggxmCYdC/E36jSA=; h=Cc:Date:From:Reply-To:Subject:To; b=ePqzcIWD2F1nKRrJ0H5+LhsSLOq8mqjC7XT7Dv6hfzht5JCu0qoQfCw8LjaTDe58Kbl p8qWwwdXDjO+eUkILMygAqZmjNQrivvguFop44Le9wVjBuI8gxZh3DlGBF+2nUt+IO2gO hZsSJPRmpQHmZoRrLUoY3b+VUi2YSVL2QQU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136546020100021 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, PlatformInitLib supports only X86 architecture. So, refactor to allow adding other architectures like RISC-V. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L --- OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf | 22 ++++++++= +++--------- OvmfPkg/Library/PlatformInitLib/{ =3D> Ia32X64}/Cmos.c | 0 OvmfPkg/Library/PlatformInitLib/{ =3D> Ia32X64}/IntelTdx.c | 0 OvmfPkg/Library/PlatformInitLib/{ =3D> Ia32X64}/IntelTdxNull.c | 0 OvmfPkg/Library/PlatformInitLib/{ =3D> Ia32X64}/MemDetect.c | 0 OvmfPkg/Library/PlatformInitLib/{ =3D> Ia32X64}/Platform.c | 0 6 files changed, 12 insertions(+), 10 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf index 86a82ad3e084..5d31cad1b670 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -22,16 +22,16 @@ [Defines] # VALID_ARCHITECTURES =3D IA32 X64 EBC # =20 -[Sources] - Cmos.c - MemDetect.c - Platform.c +[Sources.IA32, Sources.X64] + Ia32X64/Cmos.c + Ia32X64/MemDetect.c + Ia32X64/Platform.c =20 [Sources.IA32] - IntelTdxNull.c + Ia32X64/IntelTdxNull.c =20 [Sources.X64] - IntelTdx.c + Ia32X64/IntelTdx.c =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -45,12 +45,14 @@ [LibraryClasses] DebugLib IoLib HobLib + PcdLib + PciLib + +[LibraryClasses.IA32, LibraryClasses.X64] + MtrrLib QemuFwCfgLib QemuFwCfgSimpleParserLib MemoryAllocationLib - MtrrLib - PcdLib - PciLib PeiHardwareInfoLib =20 [LibraryClasses.X64] @@ -100,5 +102,5 @@ [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize =20 -[FeaturePcd] +[FeaturePcd.IA32, FeaturePcd.X64] gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode diff --git a/OvmfPkg/Library/PlatformInitLib/Cmos.c b/OvmfPkg/Library/Platf= ormInitLib/Ia32X64/Cmos.c similarity index 100% rename from OvmfPkg/Library/PlatformInitLib/Cmos.c rename to OvmfPkg/Library/PlatformInitLib/Ia32X64/Cmos.c diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c b/OvmfPkg/Library/P= latformInitLib/Ia32X64/IntelTdx.c similarity index 100% rename from OvmfPkg/Library/PlatformInitLib/IntelTdx.c rename to OvmfPkg/Library/PlatformInitLib/Ia32X64/IntelTdx.c diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c b/OvmfPkg/Libra= ry/PlatformInitLib/Ia32X64/IntelTdxNull.c similarity index 100% rename from OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c rename to OvmfPkg/Library/PlatformInitLib/Ia32X64/IntelTdxNull.c diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/= PlatformInitLib/Ia32X64/MemDetect.c similarity index 100% rename from OvmfPkg/Library/PlatformInitLib/MemDetect.c rename to OvmfPkg/Library/PlatformInitLib/Ia32X64/MemDetect.c diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Ia32X64/Platform.c similarity index 100% rename from OvmfPkg/Library/PlatformInitLib/Platform.c rename to OvmfPkg/Library/PlatformInitLib/Ia32X64/Platform.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95731): https://edk2.groups.io/g/devel/message/95731 Mute This Topic: https://groups.io/mt/94664297/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95732+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95732+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136548; cv=none; d=zohomail.com; s=zohoarc; b=F6jl018GViV7D9y/Kz1nvtT01zAShxGF2JB8ho9Mlpa0fFNnLWu3DHFBsxHBhrpYtPBoZOLd78qWP9EqghOGP8SUuWlwOkuIE6L4qoRuc+AdY38a07f8mhFwOWvsfwS5GloVU2S26dsOOTeb05v7IFXlUOsfshxybJDT42R35/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136548; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8OimATJYS9WB9f2uRueYa2aDJkJS85lmO6jtZX/qKYw=; b=OCD59BnaWAUO7a8J2KD3vW6hRJSMCVq/ZGPg2Xj1I1t+YefMAFYugGx8uBazdZ20UNNfPFY2GymJhOYf5h1tuVgVjUXvtLrbJUGDNeByOyvzmlkIL2FSWmk706njuWt3AeLDdsqoALLqesjtZzQZs2OlnNq1oQ5clgZHB5at0g4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95732+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136548627154.31941589824578; Sun, 30 Oct 2022 06:29:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id exPvYY1788612xrBkLtqJ9x1; Sun, 30 Oct 2022 06:29:07 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web09.8113.1667136546457351476 for ; Sun, 30 Oct 2022 06:29:06 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id f23so8655559plr.6 for ; Sun, 30 Oct 2022 06:29:06 -0700 (PDT) X-Gm-Message-State: akveRyEogfVaILjiC0TQljndx1787277AA= X-Google-Smtp-Source: AMsMyM6dAvVgg35nmuccG+7mPv8W5ATnGfdaN7ZkS9glBnxmFeB3Vq3JIhhTZfVfmsZ1LEgcW432Ag== X-Received: by 2002:a17:90a:d50e:b0:213:7a2e:8991 with SMTP id t14-20020a17090ad50e00b002137a2e8991mr9720281pju.113.1667136545816; Sun, 30 Oct 2022 06:29:05 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:05 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 06/30] OvmfPkg/PlatformInitLib: Add support for RISC-V Date: Sun, 30 Oct 2022 18:58:18 +0530 Message-Id: <20221030132842.54077-7-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136547; bh=KG5pQPCxoQa7tQt5K6AzGih07LOaeDl123yuZ14EeOc=; h=Cc:Date:From:Reply-To:Subject:To; b=RtEHcvB5gc9QpuRO9l+KQZiD/hEDs7RBSIulzgH0noZ19YWbYztXjsYnoXL1qOd+JUA KBW7osqVw+s2+qT+T9uWu3T4P/OBggxjruaBU80gk2UhXLw3fwIGwtsChGZQixan0pX9/ lUMsg1mq8lfD83vj/6RjBXrKYq5zqOhm798= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136550002100027 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is copied from edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/FdtPeim but added as part of library instead of a separate module. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Signed-off-by: Sunil V L --- OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf | 9 ++- OvmfPkg/Include/Library/PlatformInitLib.h | 6 ++ OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c | 72 ++++++++++++= ++++++++ 3 files changed, 86 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf index 5d31cad1b670..b3a69bf9582c 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -19,7 +19,7 @@ [Defines] # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC +# VALID_ARCHITECTURES =3D IA32 X64 EBC RISCV64 # =20 [Sources.IA32, Sources.X64] @@ -33,6 +33,9 @@ [Sources.IA32] [Sources.X64] Ia32X64/IntelTdx.c =20 +[Sources.RISCV64] + RiscV64/PlatformPeiLib.c + [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec @@ -58,6 +61,10 @@ [LibraryClasses.IA32, LibraryClasses.X64] [LibraryClasses.X64] TdxLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + FdtLib + [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress =20 diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index c5234bf26d45..1b8d1fad3b49 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -285,4 +285,10 @@ PlatformInitEmuVariableNvStore ( IN VOID *EmuVariableNvStore ); =20 +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c b/Ovm= fPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c new file mode 100644 index 000000000000..266d5ddff58e --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c @@ -0,0 +1,72 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +//// The package level header files this module uses +//// +#include + +#include +#include +#include +#include + +#include + +#include + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUN= CTION__, FdtPointer)); + Base =3D FdtPointer; + ASSERT (Base !=3D NULL); + ASSERT (fdt_check_header (Base) =3D=3D 0); + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + ASSERT (NewBase !=3D NULL); + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + ASSERT (FdtHobData !=3D NULL); + *FdtHobData =3D (UINTN)NewBase; + + return EFI_SUCCESS; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95732): https://edk2.groups.io/g/devel/message/95732 Mute This Topic: https://groups.io/mt/94664299/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95733+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95733+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136551; cv=none; d=zohomail.com; s=zohoarc; b=FDUvIbxp0H2ombAVtcLdZEX2V6yZO5YoZ6bc8Vq8IR3cc5YBGxxQkWYp2UVcqpFV2QAyQS7daKYU+yYoSZRt1XWH/9qDPlwn0hMijrVMBjwl69i8XwO6WkIZh/qmeApps0bzDE1v//0S5aAeHRSV2ASb5KBYCGqcHDAQTial2VA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136551; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cg6sTnXidJEQg9NnXdQCsCF/Lt1P3eNgrd+YUgIoH/o=; b=fdny/DQAQ8dIq0O4ImJ0XlqInFuh1Dg4BfRJvOgnptN6WtvpTbODQxiG3VzYGWFEHOafEnK4Hlvpq68Mnirhq4wFW6vUTeIdJdZrre0VH1SjJKPaLiXz6CqVJsaEM+nrbTGTP2l+kkvZAfPnKZmkg5uMnrLtoUuDuojM1JY90+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95733+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166713655122875.6084286703665; Sun, 30 Oct 2022 06:29:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Gr5nYY1788612xfQGq7KNCqV; Sun, 30 Oct 2022 06:29:10 -0700 X-Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) by mx.groups.io with SMTP id smtpd.web09.8114.1667136549299319147 for ; Sun, 30 Oct 2022 06:29:09 -0700 X-Received: by mail-pl1-f171.google.com with SMTP id u6so8640165plq.12 for ; Sun, 30 Oct 2022 06:29:09 -0700 (PDT) X-Gm-Message-State: m8AzpVshQXGtqTyPXoTcAxFzx1787277AA= X-Google-Smtp-Source: AMsMyM7jil9Ha3pYhsfz8TRW6o5z/Op44fr7xkTfcxEb033F1JeLjxZn3n+V9HQcsWk2Idl15Czhgg== X-Received: by 2002:a17:90b:254e:b0:20b:7e26:f0a0 with SMTP id nw14-20020a17090b254e00b0020b7e26f0a0mr26254336pjb.203.1667136548468; Sun, 30 Oct 2022 06:29:08 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:08 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Rebecca Cran , Peter Grehan Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 07/30] OvmfPkg/ResetSystemLib: Refactor to allow other architectures. Date: Sun, 30 Oct 2022 18:58:19 +0530 Message-Id: <20221030132842.54077-8-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136550; bh=Qfc8s9s38U0GIQu8k6zUfZTtHHYSE06ysJ682WYjIZk=; h=Cc:Date:From:Reply-To:Subject:To; b=wrcNq2BM1VnitnjPZ/6r6F/7hgaepSXHIzaSkwFEpKfyzWKdcRaLI3l5U+yNkf+gSF6 xT2liw9XWwmD7q3lYbvyJLwn4ckMITAA+dAtYWey/heoPMb68NWjvM2cLfVsPuMlb5b2z /mLYCg6hssp4txL5XU8+Us4IUl37D1Fu5SU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136552006100029 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, the ResetSystemLib library supports only X86 architecture. Refactor it to allow adding other CPU architectures like RISC-V. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Rebecca Cran Cc: Peter Grehan Signed-off-by: Sunil V L --- OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf | = 6 +++--- OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf | = 4 ++-- OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf | = 2 +- OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf | = 6 +++--- OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf | = 4 ++-- OvmfPkg/Library/ResetSystemLib/{ =3D> Ia32X64}/BaseResetShutdown.c = | 0 OvmfPkg/Library/ResetSystemLib/{ =3D> Ia32X64}/BaseResetShutdownBhyve.c = | 0 OvmfPkg/Library/ResetSystemLib/{ =3D> Ia32X64}/DxeResetShutdown.c = | 0 OvmfPkg/Library/ResetSystemLib/{ =3D> Ia32X64}/DxeResetSystemLibMicrovm.c = | 0 OvmfPkg/Library/ResetSystemLib/{ =3D> Ia32X64}/ResetSystemLib.c = | 0 OvmfPkg/Library/ResetSystemLib/{ =3D> Ia32X64}/ResetSystemLibMicrovm.c = | 0 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf b/OvmfPk= g/Library/ResetSystemLib/BaseResetSystemLib.inf index 35d317f1e0b3..a554c6b68cfe 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf @@ -21,9 +21,9 @@ [Defines] # VALID_ARCHITECTURES =3D IA32 X64 # =20 -[Sources] - BaseResetShutdown.c - ResetSystemLib.c +[Sources.IA32, Sources.X64] + Ia32X64/BaseResetShutdown.c + Ia32X64/ResetSystemLib.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf b/O= vmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf index 74124aed38e8..882a8767cfa5 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf @@ -25,8 +25,8 @@ [Defines] # =20 [Sources] - BaseResetShutdownBhyve.c - ResetSystemLib.c + Ia32X64/BaseResetShutdownBhyve.c + Ia32X64/ResetSystemLib.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf b= /OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf index 564b1d3022a6..8e73ac256bc7 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf @@ -23,7 +23,7 @@ [Defines] # =20 [Sources] - ResetSystemLibMicrovm.c + Ia32X64/ResetSystemLibMicrovm.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf b/OvmfPkg= /Library/ResetSystemLib/DxeResetSystemLib.inf index a9b4ce90000a..acf9c6a93552 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf @@ -23,9 +23,9 @@ [Defines] # VALID_ARCHITECTURES =3D IA32 X64 # =20 -[Sources] - DxeResetShutdown.c - ResetSystemLib.c +[Sources.IA32, Sources.X64] + Ia32X64/DxeResetShutdown.c + Ia32X64/ResetSystemLib.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf b/= OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf index ac9c2599642c..918c8262fac7 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf @@ -24,8 +24,8 @@ [Defines] # =20 [Sources] - ResetSystemLibMicrovm.c - DxeResetSystemLibMicrovm.c + Ia32X64/ResetSystemLibMicrovm.c + Ia32X64/DxeResetSystemLibMicrovm.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/L= ibrary/ResetSystemLib/Ia32X64/BaseResetShutdown.c similarity index 100% rename from OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c rename to OvmfPkg/Library/ResetSystemLib/Ia32X64/BaseResetShutdown.c diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdownBhyve.c b/Ovmf= Pkg/Library/ResetSystemLib/Ia32X64/BaseResetShutdownBhyve.c similarity index 100% rename from OvmfPkg/Library/ResetSystemLib/BaseResetShutdownBhyve.c rename to OvmfPkg/Library/ResetSystemLib/Ia32X64/BaseResetShutdownBhyve.c diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Li= brary/ResetSystemLib/Ia32X64/DxeResetShutdown.c similarity index 100% rename from OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c rename to OvmfPkg/Library/ResetSystemLib/Ia32X64/DxeResetShutdown.c diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.c b/Ov= mfPkg/Library/ResetSystemLib/Ia32X64/DxeResetSystemLibMicrovm.c similarity index 100% rename from OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.c rename to OvmfPkg/Library/ResetSystemLib/Ia32X64/DxeResetSystemLibMicrovm.c diff --git a/OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c b/OvmfPkg/Libr= ary/ResetSystemLib/Ia32X64/ResetSystemLib.c similarity index 100% rename from OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c rename to OvmfPkg/Library/ResetSystemLib/Ia32X64/ResetSystemLib.c diff --git a/OvmfPkg/Library/ResetSystemLib/ResetSystemLibMicrovm.c b/OvmfP= kg/Library/ResetSystemLib/Ia32X64/ResetSystemLibMicrovm.c similarity index 100% rename from OvmfPkg/Library/ResetSystemLib/ResetSystemLibMicrovm.c rename to OvmfPkg/Library/ResetSystemLib/Ia32X64/ResetSystemLibMicrovm.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95733): https://edk2.groups.io/g/devel/message/95733 Mute This Topic: https://groups.io/mt/94664300/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95734+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95734+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136553; cv=none; d=zohomail.com; s=zohoarc; b=LSsswPQ6fkx9d1xcUt6wfV9ZbhSTcmqj4vWpXfYaIzoakpQdH8anvVhliNXub7BpA2nER5qyzGpGSZjGps6TmAxGHvhbMnrMIf9Q2V1ZGFa/Nl/vSK20XgYVKMeJlnuQsjdYm6fXQIc5qNOLv+J03INoVh2VXPqas6GEjONKTFU= ARC-Message-Signature: i=1; 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Sun, 30 Oct 2022 06:29:12 -0700 X-Received: by mail-pl1-f181.google.com with SMTP id 4so8697311pli.0 for ; Sun, 30 Oct 2022 06:29:12 -0700 (PDT) X-Gm-Message-State: n1r6AXi9FfN2KbZHWwtSZ8LJx1787277AA= X-Google-Smtp-Source: AMsMyM4xZKb+zU9AO9hNK75jFJvtIOrwxXZVMPyl20HBXjHwctEGJ8AfPVJmCTMgFZ8ck6WEljDdgg== X-Received: by 2002:a17:902:848c:b0:17a:b4c0:a02b with SMTP id c12-20020a170902848c00b0017ab4c0a02bmr9276925plo.122.1667136551399; Sun, 30 Oct 2022 06:29:11 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:11 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Rebecca Cran , Peter Grehan , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 08/30] OvmfPkg/ResetSystemLib: Add support for RISC-V Date: Sun, 30 Oct 2022 18:58:20 +0530 Message-Id: <20221030132842.54077-9-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136552; bh=J26nky2FGefp4bdoIu25D8/04vJz/+/cCb4rdO2nvcs=; h=Cc:Date:From:Reply-To:Subject:To; b=FCLCii7PteImGJuECRbnVn8RkBhnnYv6Ue9oxcuLw5v/jYJgyagb0rHjqbluNyg8hoA Zi+UMjtx5tyzya1vhkEBhycIrBUVsRvphEu7HcAhWsZ1YV+o3ijTdsF4QlfYOOIkWY7I+ R+0rbEbzt9UkT5RbdUEEd0Jl+M2PbjAhLYg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136554032100033 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is mostly copied from edk2-platforms/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Rebecca Cran Cc: Peter Grehan Cc: Daniel Schaefer Signed-off-by: Sunil V L --- OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf | 6 + OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf | 9 +- OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c | 20 +++ OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c | 128 ++++++++++= ++++++++++ 4 files changed, 162 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf b/OvmfPk= g/Library/ResetSystemLib/BaseResetSystemLib.inf index a554c6b68cfe..9b2afc36dd95 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf @@ -25,6 +25,9 @@ [Sources.IA32, Sources.X64] Ia32X64/BaseResetShutdown.c Ia32X64/ResetSystemLib.c =20 +[Sources.RISCV64] + RiscV64/ResetSystemLib.c + [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -36,3 +39,6 @@ [LibraryClasses] IoLib PciLib TimerLib + +[LibraryClasses.RISCV64] + RiscVSbiLib diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf b/OvmfPkg= /Library/ResetSystemLib/DxeResetSystemLib.inf index acf9c6a93552..c012a163c61a 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf @@ -20,13 +20,17 @@ [Defines] # The following information is for reference only and not required by the = build # tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.IA32, Sources.X64] Ia32X64/DxeResetShutdown.c Ia32X64/ResetSystemLib.c =20 +[Sources.RISCV64] + RiscV64/ResetSystemLib.c + RiscV64/DxeResetShutdown.c + [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -39,5 +43,8 @@ [LibraryClasses] PcdLib TimerLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId ## CONSUMES diff --git a/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c b/Ov= mfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c new file mode 100644 index 000000000000..027e235cad11 --- /dev/null +++ b/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c @@ -0,0 +1,20 @@ +/** @file + DXE Reset System Library Shutdown API implementation for OVMF. + + Copyright (C) 2020, Red Hat, Inc. + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include // CpuDeadLoop() +#include // ResetShutdown() + +EFI_STATUS +EFIAPI +DxeResetInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c b/Ovmf= Pkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c new file mode 100644 index 000000000000..14f7653aa8de --- /dev/null +++ b/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c @@ -0,0 +1,128 @@ +/** @file + Reset System Library functions for RISC-V + + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + // Shut down via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE= ); +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform. The platform m= ay + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + // + // Can map to OpenSBI vendor or platform specific reset type. + // + return; +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,= or EfiResetShutdown + the data buffer starts with a Null-terminated = string, optionally + followed by additional binary data. The string= is a description + that the caller may use to further indicate th= e reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95734): https://edk2.groups.io/g/devel/message/95734 Mute This Topic: https://groups.io/mt/94664309/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95735+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95735+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136556; cv=none; d=zohomail.com; s=zohoarc; b=c3Eo65zLnsjbSmoIaywNn8coCC7gfRAC9TMKCjUxbmwOlh+d+mzKKhixDKjdMDvDh0DJ/V3NwUNXcmc/mnFeXNByvfLr/njvJry2gVd/rTJwgsXZtKKNYzar1Ws6ijgNSDQGWm02Ecmeyz+4zolyB0tvONC2jhEJ97sVrTWLHyo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136556; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7v9FPQz/qQIEQ/V/WU7q0MXj6ahNdWfrBFa40GHPGho=; b=FDifRhUb6O8TjNWa6LJrt2uvsn1AbzeoFKPwCFtS2Z7hubX+9AmWsSjLV1Lsj4S11D+VL7+qOSc2tmbxWRdxR2z0m8i3mMjuUrscGve4gShGh68ascFKzA1hKIBZVkJ+iGiOE31vCxHP/iuseGPx77bCqMNkSUUb4Ld3vgJUcbA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95735+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136556496318.4499293345058; Sun, 30 Oct 2022 06:29:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MfUsYY1788612xmN3zw0VjMC; Sun, 30 Oct 2022 06:29:16 -0700 X-Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mx.groups.io with SMTP id smtpd.web12.8280.1667136555495542832 for ; Sun, 30 Oct 2022 06:29:15 -0700 X-Received: by mail-pj1-f48.google.com with SMTP id k5so785286pjo.5 for ; Sun, 30 Oct 2022 06:29:15 -0700 (PDT) X-Gm-Message-State: Nlh9FqNpvRfiUNIRLUbUeaDIx1787277AA= X-Google-Smtp-Source: AMsMyM7UYuBVPUyH1Zhe8dPrfRO9PIVlaQoBP1i7/or1Nf2ZwEc0GWMq4o7w9TdWHAyC96yOGArSRg== X-Received: by 2002:a17:902:9048:b0:17f:93a5:4638 with SMTP id w8-20020a170902904800b0017f93a54638mr9180575plz.108.1667136554720; Sun, 30 Oct 2022 06:29:14 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:14 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Brijesh Singh , Erdem Aktas , James Bottomley , Min Xu , Tom Lendacky Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 09/30] OvmfPkg/Sec: Refactor to allow other architectures Date: Sun, 30 Oct 2022 18:58:21 +0530 Message-Id: <20221030132842.54077-10-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136556; bh=mHCToPvz4mM26By1RrkVwbdeXeiBaqqqIXI3Gu2qInY=; h=Cc:Date:From:Reply-To:Subject:To; b=mNbV4VnEvUUQdq3lOde3b1lqJXx9w6FWTNmglzfGFA5vsSC5U3MUgGz/GuiymZrcRxJ 64R9Kw+q0GspGK/ToptDrbklYoY0TBX4go2NeYON6qipZHFNkzXc6+lLArOkyyphZedCI iHP37Lvnf38u3x6UffD5RdgMBFH16sZoETg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136558085100037 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, the Sec module supports only X86 architecture. Refactor the module to allow other CPU architectures. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Min Xu Cc: Tom Lendacky Signed-off-by: Sunil V L --- OvmfPkg/Sec/SecMain.inf | 18 +- OvmfPkg/Sec/{ =3D> Ia32X64}/AmdSev.h | 0 OvmfPkg/Sec/SecMainCommon.h | 73 ++++++ OvmfPkg/Sec/{ =3D> Ia32X64}/AmdSev.c | 0 OvmfPkg/Sec/{ =3D> Ia32X64}/SecMain.c | 227 +------------------ OvmfPkg/Sec/SecMainCommon.c | 238 ++++++++++++++++++++ 6 files changed, 323 insertions(+), 233 deletions(-) diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 561a840f29c5..a014bcb4cf1a 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -21,10 +21,12 @@ [Defines] # VALID_ARCHITECTURES =3D IA32 X64 EBC # =20 -[Sources] - SecMain.c - AmdSev.c - AmdSev.h +[Sources.IA32, Sources.X64] + SecMainCommon.c + SecMainCommon.h + Ia32X64/SecMain.c + Ia32X64/AmdSev.c + Ia32X64/AmdSev.h =20 [Sources.IA32] Ia32/SecEntry.nasm @@ -42,19 +44,21 @@ [LibraryClasses] BaseLib DebugLib BaseMemoryLib - PeiServicesLib PcdLib CpuLib - UefiCpuLib DebugAgentLib IoLib PeCoffLib PeCoffGetEntryPointLib PeCoffExtraActionLib ExtractGuidedSectionLib + CpuExceptionHandlerLib + +[LibraryClasses.IA32, LibraryClasses.X64] + UefiCpuLib LocalApicLib MemEncryptSevLib - CpuExceptionHandlerLib + PeiServicesLib CcProbeLib =20 [Ppis] diff --git a/OvmfPkg/Sec/AmdSev.h b/OvmfPkg/Sec/Ia32X64/AmdSev.h similarity index 100% rename from OvmfPkg/Sec/AmdSev.h rename to OvmfPkg/Sec/Ia32X64/AmdSev.h diff --git a/OvmfPkg/Sec/SecMainCommon.h b/OvmfPkg/Sec/SecMainCommon.h new file mode 100644 index 000000000000..c3cc16e2c8cf --- /dev/null +++ b/OvmfPkg/Sec/SecMainCommon.h @@ -0,0 +1,73 @@ +/** @file + Header file for common functions of Sec. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Locates a section within a series of sections + with the specified section type. + + The Instance parameter indicates which instance of the section + type to return. (0 is first instance, 1 is second...) + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[in] Instance The section instance number + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInstance ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + IN UINTN Instance, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ); + +/** + Locates a FFS file with the specified file type and a section + within that file with the specified section type. + + @param[in] Fv The firmware volume to search + @param[in] FileType The file type to locate + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsFileAndSection ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + IN EFI_FV_FILETYPE FileType, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ); + +/** + Locates the PEI Core entry point address + + @param[in] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindPeiCoreImageBaseInFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ); diff --git a/OvmfPkg/Sec/AmdSev.c b/OvmfPkg/Sec/Ia32X64/AmdSev.c similarity index 100% rename from OvmfPkg/Sec/AmdSev.c rename to OvmfPkg/Sec/Ia32X64/AmdSev.c diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/Ia32X64/SecMain.c similarity index 75% rename from OvmfPkg/Sec/SecMain.c rename to OvmfPkg/Sec/Ia32X64/SecMain.c index 1167d22a68cc..096bab074f35 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/Ia32X64/SecMain.c @@ -32,6 +32,7 @@ #include #include #include "AmdSev.h" +#include "SecMainCommon.h" =20 #define SEC_IDT_ENTRY_COUNT 34 =20 @@ -143,189 +144,6 @@ FindMainFv ( } while (TRUE); } =20 -/** - Locates a section within a series of sections - with the specified section type. - - The Instance parameter indicates which instance of the section - type to return. (0 is first instance, 1 is second...) - - @param[in] Sections The sections to search - @param[in] SizeOfSections Total size of all sections - @param[in] SectionType The section type to locate - @param[in] Instance The section instance number - @param[out] FoundSection The FFS section if found - - @retval EFI_SUCCESS The file and section was found - @retval EFI_NOT_FOUND The file and section was not found - @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted - -**/ -EFI_STATUS -FindFfsSectionInstance ( - IN VOID *Sections, - IN UINTN SizeOfSections, - IN EFI_SECTION_TYPE SectionType, - IN UINTN Instance, - OUT EFI_COMMON_SECTION_HEADER **FoundSection - ) -{ - EFI_PHYSICAL_ADDRESS CurrentAddress; - UINT32 Size; - EFI_PHYSICAL_ADDRESS EndOfSections; - EFI_COMMON_SECTION_HEADER *Section; - EFI_PHYSICAL_ADDRESS EndOfSection; - - // - // Loop through the FFS file sections within the PEI Core FFS file - // - EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Sections; - EndOfSections =3D EndOfSection + SizeOfSections; - for ( ; ;) { - if (EndOfSection =3D=3D EndOfSections) { - break; - } - - CurrentAddress =3D (EndOfSection + 3) & ~(3ULL); - if (CurrentAddress >=3D EndOfSections) { - return EFI_VOLUME_CORRUPTED; - } - - Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress; - - Size =3D SECTION_SIZE (Section); - if (Size < sizeof (*Section)) { - return EFI_VOLUME_CORRUPTED; - } - - EndOfSection =3D CurrentAddress + Size; - if (EndOfSection > EndOfSections) { - return EFI_VOLUME_CORRUPTED; - } - - // - // Look for the requested section type - // - if (Section->Type =3D=3D SectionType) { - if (Instance =3D=3D 0) { - *FoundSection =3D Section; - return EFI_SUCCESS; - } else { - Instance--; - } - } - } - - return EFI_NOT_FOUND; -} - -/** - Locates a section within a series of sections - with the specified section type. - - @param[in] Sections The sections to search - @param[in] SizeOfSections Total size of all sections - @param[in] SectionType The section type to locate - @param[out] FoundSection The FFS section if found - - @retval EFI_SUCCESS The file and section was found - @retval EFI_NOT_FOUND The file and section was not found - @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted - -**/ -EFI_STATUS -FindFfsSectionInSections ( - IN VOID *Sections, - IN UINTN SizeOfSections, - IN EFI_SECTION_TYPE SectionType, - OUT EFI_COMMON_SECTION_HEADER **FoundSection - ) -{ - return FindFfsSectionInstance ( - Sections, - SizeOfSections, - SectionType, - 0, - FoundSection - ); -} - -/** - Locates a FFS file with the specified file type and a section - within that file with the specified section type. - - @param[in] Fv The firmware volume to search - @param[in] FileType The file type to locate - @param[in] SectionType The section type to locate - @param[out] FoundSection The FFS section if found - - @retval EFI_SUCCESS The file and section was found - @retval EFI_NOT_FOUND The file and section was not found - @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted - -**/ -EFI_STATUS -FindFfsFileAndSection ( - IN EFI_FIRMWARE_VOLUME_HEADER *Fv, - IN EFI_FV_FILETYPE FileType, - IN EFI_SECTION_TYPE SectionType, - OUT EFI_COMMON_SECTION_HEADER **FoundSection - ) -{ - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS CurrentAddress; - EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; - EFI_FFS_FILE_HEADER *File; - UINT32 Size; - EFI_PHYSICAL_ADDRESS EndOfFile; - - if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { - DEBUG ((DEBUG_ERROR, "FV at %p does not have FV header signature\n", F= v)); - return EFI_VOLUME_CORRUPTED; - } - - CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Fv; - EndOfFirmwareVolume =3D CurrentAddress + Fv->FvLength; - - // - // Loop through the FFS files in the Boot Firmware Volume - // - for (EndOfFile =3D CurrentAddress + Fv->HeaderLength; ; ) { - CurrentAddress =3D (EndOfFile + 7) & ~(7ULL); - if (CurrentAddress > EndOfFirmwareVolume) { - return EFI_VOLUME_CORRUPTED; - } - - File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; - Size =3D FFS_FILE_SIZE (File); - if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) { - return EFI_VOLUME_CORRUPTED; - } - - EndOfFile =3D CurrentAddress + Size; - if (EndOfFile > EndOfFirmwareVolume) { - return EFI_VOLUME_CORRUPTED; - } - - // - // Look for the request file type - // - if (File->Type !=3D FileType) { - continue; - } - - Status =3D FindFfsSectionInSections ( - (VOID *)(File + 1), - (UINTN)EndOfFile - (UINTN)(File + 1), - SectionType, - FoundSection - ); - if (!EFI_ERROR (Status) || (Status =3D=3D EFI_VOLUME_CORRUPTED)) { - return Status; - } - } -} - /** Locates the compressed main firmware volume and decompresses it. =20 @@ -474,49 +292,6 @@ DecompressMemFvs ( return EFI_SUCCESS; } =20 -/** - Locates the PEI Core entry point address - - @param[in] Fv The firmware volume to search - @param[out] PeiCoreEntryPoint The entry point of the PEI Core image - - @retval EFI_SUCCESS The file and section was found - @retval EFI_NOT_FOUND The file and section was not found - @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted - -**/ -EFI_STATUS -FindPeiCoreImageBaseInFv ( - IN EFI_FIRMWARE_VOLUME_HEADER *Fv, - OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase - ) -{ - EFI_STATUS Status; - EFI_COMMON_SECTION_HEADER *Section; - - Status =3D FindFfsFileAndSection ( - Fv, - EFI_FV_FILETYPE_PEI_CORE, - EFI_SECTION_PE32, - &Section - ); - if (EFI_ERROR (Status)) { - Status =3D FindFfsFileAndSection ( - Fv, - EFI_FV_FILETYPE_PEI_CORE, - EFI_SECTION_TE, - &Section - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Unable to find PEI Core image\n")); - return Status; - } - } - - *PeiCoreImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1); - return EFI_SUCCESS; -} - /** Reads 8-bits of CMOS data. =20 diff --git a/OvmfPkg/Sec/SecMainCommon.c b/OvmfPkg/Sec/SecMainCommon.c new file mode 100644 index 000000000000..f360e63a7c26 --- /dev/null +++ b/OvmfPkg/Sec/SecMainCommon.c @@ -0,0 +1,238 @@ +/** @file + Locate the entry point for the PEI Core + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include + +/** + Locates a section within a series of sections + with the specified section type. + + The Instance parameter indicates which instance of the section + type to return. (0 is first instance, 1 is second...) + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[in] Instance The section instance number + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInstance ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + IN UINTN Instance, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfSections; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + // + // Loop through the FFS file sections within the PEI Core FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Sections; + EndOfSections =3D EndOfSection + SizeOfSections; + for ( ; ;) { + if (EndOfSection =3D=3D EndOfSections) { + break; + } + + CurrentAddress =3D (EndOfSection + 3) & ~(3ULL); + if (CurrentAddress >=3D EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the requested section type + // + if (Section->Type =3D=3D SectionType) { + if (Instance =3D=3D 0) { + *FoundSection =3D Section; + return EFI_SUCCESS; + } else { + Instance--; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Locates a section within a series of sections + with the specified section type. + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInSections ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + return FindFfsSectionInstance ( + Sections, + SizeOfSections, + SectionType, + 0, + FoundSection + ); +} + +/** + Locates a FFS file with the specified file type and a section + within that file with the specified section type. + + @param[in] Fv The firmware volume to search + @param[in] FileType The file type to locate + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsFileAndSection ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + IN EFI_FV_FILETYPE FileType, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "FV at %p does not have FV header signature\n", F= v)); + return EFI_VOLUME_CORRUPTED; + } + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Fv; + EndOfFirmwareVolume =3D CurrentAddress + Fv->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + Fv->HeaderLength; ; ) { + CurrentAddress =3D (EndOfFile + 7) & ~(7ULL); + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; + Size =3D FFS_FILE_SIZE (File); + if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the request file type + // + if (File->Type !=3D FileType) { + continue; + } + + Status =3D FindFfsSectionInSections ( + (VOID *)(File + 1), + (UINTN)EndOfFile - (UINTN)(File + 1), + SectionType, + FoundSection + ); + if (!EFI_ERROR (Status) || (Status =3D=3D EFI_VOLUME_CORRUPTED)) { + return Status; + } + } +} + +/** + Locates the PEI Core entry point address + + @param[in] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindPeiCoreImageBaseInFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + EFI_STATUS Status; + EFI_COMMON_SECTION_HEADER *Section; + + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_PE32, + &Section + ); + if (EFI_ERROR (Status)) { + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_TE, + &Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI Core image\n")); + return Status; + } + } + + *PeiCoreImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1); + return EFI_SUCCESS; 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View/Reply Online (#95735): https://edk2.groups.io/g/devel/message/95735 Mute This Topic: https://groups.io/mt/94664315/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95736+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95736+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136560; cv=none; d=zohomail.com; s=zohoarc; b=jiWGfhmFsFgB18GrQBe3AahiJMIJ6creC0pWtA1LO8D6skscAI+/7CpMfZ4+OJ/9rAq/dU7jHQRltAqjqjXtDlpWbn/veK0dQLmICqY7Fvxh8Yw6nd+PsHNHthmQJAEADZOEtLuKULJFy/xhyeFpW7T8u0YfGAMN08RD6VLuyn0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136560; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RM96JNl6iTYNaH05wopAbuxXBxx6tsAM9GzTj+mBeG4=; b=O6UKaYcis4c+easnFEA2IDcCxqkFzq2/kAqD1TrBMItG9or7xNTsZ4omtokDIqVYT3c4BkkM7KhZeJpc8nNHV+ENnAvMyMJ2o/3+Pvnf5bnV1Q1lHAPAMGx2EawKd8GLgB6IrTF3YR2pl4qBqqTIDFveB5u2bd0Y4yd+WKBPxgQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95736+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136560169897.8537514496737; Sun, 30 Oct 2022 06:29:20 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3FZuYY1788612xTM9gDKhcKQ; Sun, 30 Oct 2022 06:29:19 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web09.8113.1667136546457351476 for ; Sun, 30 Oct 2022 06:29:19 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id f23so8655808plr.6 for ; Sun, 30 Oct 2022 06:29:19 -0700 (PDT) X-Gm-Message-State: p4pji36yi0cRxeJ58RIvAamEx1787277AA= X-Google-Smtp-Source: AMsMyM6I1zae/8/yFoJebPVzTa2L5gia3BNvzXguoUwoerq9ACypo49k8e9KjVVfqGjj9OXp1xAC3A== X-Received: by 2002:a17:902:d409:b0:186:af8d:4029 with SMTP id b9-20020a170902d40900b00186af8d4029mr9162671ple.78.1667136558514; Sun, 30 Oct 2022 06:29:18 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:18 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Brijesh Singh , Erdem Aktas , James Bottomley , Min Xu , Tom Lendacky , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 10/30] OvmfPkg/Sec: Add RISC-V support Date: Sun, 30 Oct 2022 18:58:22 +0530 Message-Id: <20221030132842.54077-11-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136559; bh=gN2V6B0CoR4lPti/O/gawVaYDr/2hkIm0EL3joSc+cQ=; h=Cc:Date:From:Reply-To:Subject:To; b=duj72VMuX1xTtsYHE9DUD76nxqWl5enG09jWo7NfyoKu5cR3AembV79+Pm5e3mMURJD +vYvYLiXkMFjUeZGtDmkWrILa8pMR6w1E7aSLX8gdRf34LbHe5MTDrN07ng5GDJAKN40A mb4Fz/KfWc7XyncFzSUJLNdX1nOOKiKXJkk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136562100100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add the SEC module for RISC-V. EDK2 is launched as the payload for machine mode firmware in RISC-V. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Min Xu Cc: Tom Lendacky Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- OvmfPkg/Sec/SecMain.inf | 16 +- OvmfPkg/Sec/RiscV64/SecMain.h | 64 +++ OvmfPkg/Sec/RiscV64/SecMain.c | 573 ++++++++++++++++++++ OvmfPkg/Sec/RiscV64/SecEntry.S | 21 + 4 files changed, 673 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index a014bcb4cf1a..96fcc464c0d5 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -18,7 +18,7 @@ [Defines] # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC +# VALID_ARCHITECTURES =3D IA32 X64 EBC RISCV64 # =20 [Sources.IA32, Sources.X64] @@ -34,6 +34,13 @@ [Sources.IA32] [Sources.X64] X64/SecEntry.nasm =20 +[Sources.RISCV64] + SecMainCommon.c + SecMainCommon.h + RiscV64/SecEntry.S + RiscV64/SecMain.c + RiscV64/SecMain.h + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -61,11 +68,17 @@ [LibraryClasses.IA32, LibraryClasses.X64] PeiServicesLib CcProbeLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED gEfiPeiMpInitLibMpDepPpiGuid gEfiPeiMpInitLibUpDepPpiGuid =20 +[Ppis.RISCV64] + gEfiTemporaryRamDonePpiGuid ## PRODUCES + [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase @@ -88,6 +101,7 @@ [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/OvmfPkg/Sec/RiscV64/SecMain.h b/OvmfPkg/Sec/RiscV64/SecMain.h new file mode 100644 index 000000000000..6489104a884d --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecMain.h @@ -0,0 +1,64 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SecMainCommon.h" + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +#endif diff --git a/OvmfPkg/Sec/RiscV64/SecMain.c b/OvmfPkg/Sec/RiscV64/SecMain.c new file mode 100644 index 000000000000..3eda37e2976f --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecMain.c @@ -0,0 +1,573 @@ +/** @file + RISC-V SEC phase module for Qemu Virt. + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +EFI_STATUS +EFIAPI +TemporaryRamDone ( + VOID + ); + +STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { + TemporaryRamMigration +}; + +STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { + TemporaryRamDone +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + &mTemporaryRamSupportPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiTemporaryRamDonePpiGuid, + &mTemporaryRamDonePpi + }, +}; + +/** Temporary RAM migration function. + + This function migrates the data from temporary RAM to permanent + memory. + + @param[in] PeiServices PEI service + @param[in] TemporaryMemoryBase Temporary memory base address + @param[in] PermanentMemoryBase Permanent memory base address + @param[in] CopySize Size to copy + +**/ +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + DEBUG (( + DEBUG_INFO, + "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n", + __FUNCTION__, + TemporaryMemoryBase, + PermanentMemoryBase, + (UINT64)CopySize + )); + + OldHeap =3D (VOID *)(UINTN)TemporaryMemoryBase; + NewHeap =3D (VOID *)((UINTN)PermanentMemoryBase + (CopySize >> 1)); + + OldStack =3D (VOID *)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); + NewStack =3D (VOID *)(UINTN)PermanentMemoryBase; + + CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap + CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack + + // + // Reset firmware context pointer + // + GetFirmwareContextPointer (&FirmwareContext); + FirmwareContext =3D (VOID *)FirmwareContext + (unsigned long)((UINTN)New= Stack - (UINTN)OldStack); + SetFirmwareContextPointer (FirmwareContext); + + DEBUG ((DEBUG_INFO, "%a: Firmware Context is relocated to 0x%x\n", __FUN= CTION__, FirmwareContext)); + + register UINTN a0 asm ("a0") =3D (UINTN)((UINTN)NewStack - (UINTN)OldSt= ack); + + asm volatile ("add sp, sp, a0"::"r"(a0):); + return EFI_SUCCESS; +} + +/** Temprary RAM done function. + +**/ +EFI_STATUS EFIAPI +TemporaryRamDone ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FU= NCTION__)); + return EFI_SUCCESS; +} + +/** Return platform SEC PPI before PEI Core + + @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR. + +**/ +STATIC EFI_STATUS +GetPlatformPrePeiCorePpiDescriptor ( + IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList + ) +{ + *ThisPpiList =3D mPrivateDispatchTable; + return EFI_SUCCESS; +} + +/** + Locates the main boot firmware volume. + + @param[in,out] BootFv On input, the base of the BootFv + On output, the decompressed main firmware volume + + @retval EFI_SUCCESS The main firmware volume was located and decompre= ssed + @retval EFI_NOT_FOUND The main firmware volume was not found + +**/ +EFI_STATUS +FindMainFv ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *Fv; + UINTN Distance; + + ASSERT (((UINTN)*BootFv & EFI_PAGE_MASK) =3D=3D 0); + + Fv =3D *BootFv; + Distance =3D (UINTN)(*BootFv)->FvLength; + do { + Fv =3D (EFI_FIRMWARE_VOLUME_HEADER *)((UINT8 *)Fv + EFI_PAGE_SI= ZE); + Distance +=3D EFI_PAGE_SIZE; + if (Distance > SIZE_32MB) { + return EFI_NOT_FOUND; + } + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + continue; + } + + if ((UINTN)Fv->FvLength < Distance) { + continue; + } + + *BootFv =3D Fv; + return EFI_SUCCESS; + } while (TRUE); +} + +/** + Locates the compressed main firmware volume and decompresses it. + + @param[in,out] Fv On input, the firmware volume to search + On output, the decompressed BOOT/PEI FV + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +DecompressMemFvs ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **Fv + ) +{ + EFI_STATUS Status; + EFI_GUID_DEFINED_SECTION *Section; + UINT32 OutputBufferSize; + UINT32 ScratchBufferSize; + UINT16 SectionAttribute; + UINT32 AuthenticationStatus; + VOID *OutputBuffer; + VOID *ScratchBuffer; + EFI_COMMON_SECTION_HEADER *FvSection; + EFI_FIRMWARE_VOLUME_HEADER *PeiMemFv; + EFI_FIRMWARE_VOLUME_HEADER *DxeMemFv; + UINT32 FvHeaderSize; + UINT32 FvSectionSize; + + FvSection =3D (EFI_COMMON_SECTION_HEADER *)NULL; + + Status =3D FindFfsFileAndSection ( + *Fv, + EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, + EFI_SECTION_GUID_DEFINED, + (EFI_COMMON_SECTION_HEADER **)&Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find GUID defined section\n")); + return Status; + } + + Status =3D ExtractGuidedSectionGetInfo ( + Section, + &OutputBufferSize, + &ScratchBufferSize, + &SectionAttribute + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to GetInfo for GUIDed section\n")); + return Status; + } + + OutputBuffer =3D (VOID *)((UINT8 *)(UINTN)PcdGet32 (PcdOvmfDxeMemFvBase= ) + SIZE_1MB); + ScratchBuffer =3D ALIGN_POINTER ((UINT8 *)OutputBuffer + OutputBufferSiz= e, SIZE_1MB); + + Status =3D ExtractGuidedSectionDecode ( + Section, + &OutputBuffer, + ScratchBuffer, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error during GUID section decode\n")); + return Status; + } + + Status =3D FindFfsSectionInstance ( + OutputBuffer, + OutputBufferSize, + EFI_SECTION_FIRMWARE_VOLUME_IMAGE, + 0, + &FvSection + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI FV section\n")); + return Status; + } + + ASSERT ( + SECTION_SIZE (FvSection) =3D=3D + (PcdGet32 (PcdOvmfPeiMemFvSize) + sizeof (*FvSection)) + ); + ASSERT (FvSection->Type =3D=3D EFI_SECTION_FIRMWARE_VOLUME_IMAGE); + + PeiMemFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdOvmfPeiMe= mFvBase); + CopyMem (PeiMemFv, (VOID *)(FvSection + 1), PcdGet32 (PcdOvmfPeiMemFvSiz= e)); + + if (PeiMemFv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signa= ture\n", PeiMemFv)); + CpuDeadLoop (); + return EFI_VOLUME_CORRUPTED; + } + + Status =3D FindFfsSectionInstance ( + OutputBuffer, + OutputBufferSize, + EFI_SECTION_FIRMWARE_VOLUME_IMAGE, + 1, + &FvSection + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find DXE FV section\n")); + return Status; + } + + ASSERT (FvSection->Type =3D=3D EFI_SECTION_FIRMWARE_VOLUME_IMAGE); + + if (IS_SECTION2 (FvSection)) { + FvSectionSize =3D SECTION2_SIZE (FvSection); + FvHeaderSize =3D sizeof (EFI_COMMON_SECTION_HEADER2); + } else { + FvSectionSize =3D SECTION_SIZE (FvSection); + FvHeaderSize =3D sizeof (EFI_COMMON_SECTION_HEADER); + } + + ASSERT (FvSectionSize =3D=3D (PcdGet32 (PcdOvmfDxeMemFvSize) + FvHeaderS= ize)); + + DxeMemFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdOvmfDxeMe= mFvBase); + CopyMem (DxeMemFv, (VOID *)((UINTN)FvSection + FvHeaderSize), PcdGet32 (= PcdOvmfDxeMemFvSize)); + + if (DxeMemFv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signa= ture\n", DxeMemFv)); + CpuDeadLoop (); + return EFI_VOLUME_CORRUPTED; + } + + *Fv =3D PeiMemFv; + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in,out] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +VOID +FindPeiCoreImageBase ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + *PeiCoreImageBase =3D 0; + + FindMainFv (BootFv); + + DecompressMemFvs (BootFv); + + FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase); +} + +/** + Find core image base. + +**/ +EFI_STATUS +FindImageBase ( + IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr, + OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + *SecCoreImageBase =3D 0; + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)BootFirmwareVolumeP= tr; + EndOfFirmwareVolume =3D CurrentAddress + BootFirmwareVolumePtr->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + BootFirmwareVolumePtr->HeaderLength;= ; ) { + CurrentAddress =3D (EndOfFile + 7) & 0xfffffffffffffff8ULL; + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_NOT_FOUND; + } + + File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; + Size =3D FFS_FILE_SIZE (File); + if (Size < sizeof (*File)) { + return EFI_NOT_FOUND; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_NOT_FOUND; + } + + // + // Look for SEC Core + // + if (File->Type !=3D EFI_FV_FILETYPE_SECURITY_CORE) { + continue; + } + + // + // Loop through the FFS file sections within the FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(File + 1); + for ( ; ;) { + CurrentAddress =3D (EndOfSection + 3) & 0xfffffffffffffffcULL; + Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddres= s; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_NOT_FOUND; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfFile) { + return EFI_NOT_FOUND; + } + + // + // Look for executable sections + // + if ((Section->Type =3D=3D EFI_SECTION_PE32) || (Section->Type =3D=3D= EFI_SECTION_TE)) { + if (File->Type =3D=3D EFI_FV_FILETYPE_SECURITY_CORE) { + *SecCoreImageBase =3D (PHYSICAL_ADDRESS)(UINTN)(Section + 1); + } + + break; + } + } + + // + // SEC Core image found + // + if (*SecCoreImageBase !=3D 0) { + return EFI_SUCCESS; + } + } +} + +/* + Find and return Pei Core entry point. + + It also find SEC and PEI Core file debug information. It will report the= m if + remote debug is enabled. + +**/ +VOID +FindAndReportEntryPoints ( + IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS SecCoreImageBase; + EFI_PHYSICAL_ADDRESS PeiCoreImageBase; + PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; + + // + // Find SEC Core and PEI Core image base + // + Status =3D FindImageBase (*BootFirmwareVolumePtr, &SecCoreImageBase); + ASSERT_EFI_ERROR (Status); + + FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase); + + ZeroMem ((VOID *)&ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT)); + // + // Report SEC Core debug information when remote debug is enabled + // + ImageContext.ImageAddress =3D SecCoreImageBase; + ImageContext.PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)= ImageContext.ImageAddress); + PeCoffLoaderRelocateImageExtraAction (&ImageContext); + + // + // Report PEI Core debug information when remote debug is enabled + // + ImageContext.ImageAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)PeiCoreImageB= ase; + ImageContext.PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)= ImageContext.ImageAddress); + PeCoffLoaderRelocateImageExtraAction (&ImageContext); + + // + // Find PEI Core entry point + // + Status =3D PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (= VOID **)PeiCoreEntryPoint); + if (EFI_ERROR (Status)) { + *PeiCoreEntryPoint =3D 0; + } + + return; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_FIRMWARE_VOLUME_HEADER *BootFv; + EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_STATUS Status; + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __FUNCTION__, + BootHartId, + DeviceTreeAddress + )); + + // + // Process all libraries constructor function linked to SecCore. + // + ProcessLibraryConstructorList (); + + BootFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdOvmfFdBaseAdd= ress); + + ASSERT (BootFv !=3D NULL); + SecCoreData.DataSize =3D (UINT16)sizeof (EFI_SEC_PEI_HAND_= OFF); + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN)BootFv->FvLength; + SecCoreData.TemporaryRamBase =3D (VOID *)(UINT64)FixedPcdGet32 (Pc= dOvmfSecPeiTempRamBase); + SecCoreData.TemporaryRamSize =3D (UINTN)FixedPcdGet32 (PcdOvmfSecP= eiTempRamSize); + SecCoreData.PeiTemporaryRamBase =3D SecCoreData.TemporaryRamBase; + SecCoreData.PeiTemporaryRamSize =3D SecCoreData.TemporaryRamSize >> 1; + SecCoreData.StackBase =3D (UINT8 *)SecCoreData.TemporaryRam= Base + (SecCoreData.TemporaryRamSize >> 1); + SecCoreData.StackSize =3D SecCoreData.TemporaryRamSize >> 1; + + DEBUG (( + DEBUG_INFO, + "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size= : 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackS= ize: 0x%x\n", + __FUNCTION__, + SecCoreData.BootFirmwareVolumeBase, + SecCoreData.BootFirmwareVolumeSize, + SecCoreData.TemporaryRamBase, + SecCoreData.TemporaryRamSize, + SecCoreData.PeiTemporaryRamBase, + SecCoreData.PeiTemporaryRamSize, + SecCoreData.StackBase, + SecCoreData.StackSize + )); + + FindAndReportEntryPoints ( + &BootFv, + &PeiCoreEntryPoint + ); + if (PeiCoreEntryPoint =3D=3D NULL) { + CpuDeadLoop (); + } + + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN)BootFv->FvLength; + + Status =3D GetPlatformPrePeiCorePpiDescriptor (&PpiList); + if (EFI_ERROR (Status)) { + PpiList =3D NULL; + } + + FirmwareContext.BootHartId =3D BootHartId; + FirmwareContext.FlattenedDeviceTree =3D (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + // + // Transfer the control to the PEI core + // + ASSERT (PeiCoreEntryPoint !=3D NULL); + (*PeiCoreEntryPoint)(&SecCoreData, PpiList); + + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/OvmfPkg/Sec/RiscV64/SecEntry.S b/OvmfPkg/Sec/RiscV64/SecEntry.S new file mode 100644 index 000000000000..e919a3cb0e80 --- /dev/null +++ b/OvmfPkg/Sec/RiscV64/SecEntry.S @@ -0,0 +1,21 @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +.text +.align 3 + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + li a5, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95736): https://edk2.groups.io/g/devel/message/95736 Mute This Topic: https://groups.io/mt/94664316/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95737+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95737+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136563; cv=none; d=zohomail.com; s=zohoarc; b=MGIliNjC/gypubllkLWmfiz0nHrYrVvIdnhAj4AEMdc0YUP1KqOZ/5j4/YOhLkLxcuNmPJDaqmkoFAkkQB9KjeJ0dtREs9zkqNZ+nw/VRthl5GZ8glfTDhnDuK0XLB0mPEpbVuv0xpbYBVudojcIWmW3mnoFhJv2QEHHxlabnBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3gMGlk/Zh+hW5J982euB1qZPMxLMMm6B8DasVRF0L3Q=; b=Zty65Q3xwSEzdko76GiVu3pjf3bx15hYCFl+VUKrg1xuiO4MJmS1RLbLZSegZpsb1FxfzRSS84pEHGpA1aoXUdddeByfVWaO0W/fH3veW+zDv8WyO+mrwzTXXJaHAR5yW8Z4tYuhryfHUj45msz8qzmZcZF2WfqQS8vchK+xnOk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95737+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136563319656.0537449434995; Sun, 30 Oct 2022 06:29:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KAr3YY1788612xcl6htkHro0; Sun, 30 Oct 2022 06:29:22 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web09.8115.1667136561521405714 for ; Sun, 30 Oct 2022 06:29:21 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id d24so8666434pls.4 for ; Sun, 30 Oct 2022 06:29:21 -0700 (PDT) X-Gm-Message-State: abIcIzAgunhLD4lnMhP2AaM3x1787277AA= X-Google-Smtp-Source: AMsMyM7WcxYCYo8lDXfFjW/KaHS3fvNCPsabJl0qm+kDbDCk/QNBlpmqOfXTkq6GRYK7sfnI0u5ePQ== X-Received: by 2002:a17:902:bd47:b0:17f:685b:27ee with SMTP id b7-20020a170902bd4700b0017f685b27eemr8890130plx.22.1667136560849; Sun, 30 Oct 2022 06:29:20 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:20 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 11/30] OvmfPkg/PlatformPei: Refactor to allow other architectures Date: Sun, 30 Oct 2022 18:58:23 +0530 Message-Id: <20221030132842.54077-12-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136562; bh=woXEUx1OtcU+JqYkhRK4GH1WGbu/BH1y6kmKGjrelEc=; h=Cc:Date:From:Reply-To:Subject:To; b=Dnm9J5SBiH9sZ97ocmXQo51EaxBYalsXy+02NZxlWrAbruRhGlebCtmYnoRWl6UE+0X ZdmU5z86ag5AxbgTstToOg+jLt8reoHwgQsotvB7dQ3FliEhrQbPW3LsZ3XdFBMcNfw35 UOR49ZhtQ6XqFzqh0tTPrpyeEvbTPxLLw0c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136564061100006 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, PlatformPei supports only X86 architecture. So, refactor it to allow other CPU architectures. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L --- OvmfPkg/PlatformPei/PlatformPei.inf | 34 +++++++++++-------= -- OvmfPkg/PlatformPei/{ =3D> Ia32X64}/Platform.h | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/AmdSev.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/ClearCache.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/FeatureControl.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/Fv.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/IntelTdx.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/MemDetect.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/MemTypeInfo.c | 0 OvmfPkg/PlatformPei/{ =3D> Ia32X64}/Platform.c | 0 10 files changed, 19 insertions(+), 15 deletions(-) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 3cd83e6ec3e5..c637f621cb1f 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -22,16 +22,16 @@ [Defines] # VALID_ARCHITECTURES =3D IA32 X64 EBC # =20 -[Sources] - AmdSev.c - ClearCache.c - FeatureControl.c - Fv.c - MemDetect.c - MemTypeInfo.c - Platform.c - Platform.h - IntelTdx.c +[Sources.IA32, Sources.X64] + Ia32X64/AmdSev.c + Ia32X64/ClearCache.c + Ia32X64/FeatureControl.c + Ia32X64/Fv.c + Ia32X64/MemDetect.c + Ia32X64/MemTypeInfo.c + Ia32X64/Platform.c + Ia32X64/Platform.h + Ia32X64/IntelTdx.c =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -57,14 +57,16 @@ [LibraryClasses] PeiServicesLib PeiServicesTablePointerLib PeimEntryPoint + PcdLib + PlatformInitLib + +[LibraryClasses.IA32, LibraryClasses.X64] + MtrrLib + VmgExitLib QemuFwCfgLib QemuFwCfgS3Lib QemuFwCfgSimpleParserLib - MtrrLib MemEncryptSevLib - PcdLib - VmgExitLib - PlatformInitLib =20 [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase @@ -99,7 +101,6 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable @@ -116,6 +117,9 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask =20 +[Pcd.IA32, Pcd.X64] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode + [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Ia32X64/P= latform.h similarity index 100% rename from OvmfPkg/PlatformPei/Platform.h rename to OvmfPkg/PlatformPei/Ia32X64/Platform.h diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/Ia32X64/Amd= Sev.c similarity index 100% rename from OvmfPkg/PlatformPei/AmdSev.c rename to OvmfPkg/PlatformPei/Ia32X64/AmdSev.c diff --git a/OvmfPkg/PlatformPei/ClearCache.c b/OvmfPkg/PlatformPei/Ia32X64= /ClearCache.c similarity index 100% rename from OvmfPkg/PlatformPei/ClearCache.c rename to OvmfPkg/PlatformPei/Ia32X64/ClearCache.c diff --git a/OvmfPkg/PlatformPei/FeatureControl.c b/OvmfPkg/PlatformPei/Ia3= 2X64/FeatureControl.c similarity index 100% rename from OvmfPkg/PlatformPei/FeatureControl.c rename to OvmfPkg/PlatformPei/Ia32X64/FeatureControl.c diff --git a/OvmfPkg/PlatformPei/Fv.c b/OvmfPkg/PlatformPei/Ia32X64/Fv.c similarity index 100% rename from OvmfPkg/PlatformPei/Fv.c rename to OvmfPkg/PlatformPei/Ia32X64/Fv.c diff --git a/OvmfPkg/PlatformPei/IntelTdx.c b/OvmfPkg/PlatformPei/Ia32X64/I= ntelTdx.c similarity index 100% rename from OvmfPkg/PlatformPei/IntelTdx.c rename to OvmfPkg/PlatformPei/Ia32X64/IntelTdx.c diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/Ia32X64/= MemDetect.c similarity index 100% rename from OvmfPkg/PlatformPei/MemDetect.c rename to OvmfPkg/PlatformPei/Ia32X64/MemDetect.c diff --git a/OvmfPkg/PlatformPei/MemTypeInfo.c b/OvmfPkg/PlatformPei/Ia32X6= 4/MemTypeInfo.c similarity index 100% rename from OvmfPkg/PlatformPei/MemTypeInfo.c rename to OvmfPkg/PlatformPei/Ia32X64/MemTypeInfo.c diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Ia32X64/P= latform.c similarity index 100% rename from OvmfPkg/PlatformPei/Platform.c rename to OvmfPkg/PlatformPei/Ia32X64/Platform.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Sun, 30 Oct 2022 06:29:24 -0700 X-Received: by mail-pg1-f175.google.com with SMTP id 78so8611056pgb.13 for ; Sun, 30 Oct 2022 06:29:24 -0700 (PDT) X-Gm-Message-State: paW45z8Z01x505arRb59Yasax1787277AA= X-Google-Smtp-Source: AMsMyM7TecsXr2mdAp7/W84lbVhzYH9FFZdoITiLQdNVAJFkbOPwfYn5LEQoSgJd9jqQCeDkFeUANQ== X-Received: by 2002:a63:91:0:b0:461:f509:2a31 with SMTP id 139-20020a630091000000b00461f5092a31mr8064794pga.108.1667136563597; Sun, 30 Oct 2022 06:29:23 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:23 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 12/30] OvmfPkg/PlatformPei: Add support for RISC-V Date: Sun, 30 Oct 2022 18:58:24 +0530 Message-Id: <20221030132842.54077-13-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136565; bh=XgNPRp8QSKl0EZw8/P1vysphmirX+tbHEaczwGbscgI=; h=Cc:Date:From:Reply-To:Subject:To; b=qJzHTyPowUK7AecaNJGpfmFU+AE5aE6iqkJnWRVDRcqtCdHdMBxTNu+04rFteYVCBDr UNooGyIIKNv283l09fms0z3CHUFXtQg+HbDEm36X1qSrXyVrYVebsMlkh2nFMjQVcD83x K9aBRkwK1CMvSAbM64Cptxx7g837WW+lQ/Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136568090100004 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is mostly copied from edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- OvmfPkg/PlatformPei/PlatformPei.inf | 9 + OvmfPkg/PlatformPei/RiscV64/Platform.h | 97 +++++ OvmfPkg/PlatformPei/RiscV64/Fv.c | 81 +++++ OvmfPkg/PlatformPei/RiscV64/MemDetect.c | 212 +++++++++++ OvmfPkg/PlatformPei/RiscV64/Platform.c | 372 ++++++++++++++++++++ 5 files changed, 771 insertions(+) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index c637f621cb1f..5d873c34ca67 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -33,6 +33,12 @@ [Sources.IA32, Sources.X64] Ia32X64/Platform.h Ia32X64/IntelTdx.c =20 +[Sources.RISCV64] + RiscV64/Fv.c + RiscV64/MemDetect.c + RiscV64/Platform.c + RiscV64/Platform.h + [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec @@ -68,6 +74,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] QemuFwCfgSimpleParserLib MemEncryptSevLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize diff --git a/OvmfPkg/PlatformPei/RiscV64/Platform.h b/OvmfPkg/PlatformPei/R= iscV64/Platform.h new file mode 100644 index 000000000000..6c23c722a360 --- /dev/null +++ b/OvmfPkg/PlatformPei/RiscV64/Platform.h @@ -0,0 +1,97 @@ +/** @file + Platform PEI module include file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_PEI_H_INCLUDED_ +#define PLATFORM_PEI_H_INCLUDED_ + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddressWidthInitialization ( + VOID + ); + +EFI_STATUS +PublishPeiMemory ( + VOID + ); + +UINT32 +GetSystemMemorySizeBelow4gb ( + VOID + ); + +VOID +InitializeRamRegions ( + VOID + ); + +EFI_STATUS +PeiFvInitialization ( + VOID + ); + +EFI_STATUS +InitializeXen ( + VOID + ); + +/** + Build processor and platform information for the U5 platform + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildRiscVSmbiosHobs ( + VOID + ); + +#endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/OvmfPkg/PlatformPei/RiscV64/Fv.c b/OvmfPkg/PlatformPei/RiscV64= /Fv.c new file mode 100644 index 000000000000..ff99c1432935 --- /dev/null +++ b/OvmfPkg/PlatformPei/RiscV64/Fv.c @@ -0,0 +1,81 @@ +/** @file + Build FV related hobs for platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PiPei.h" +#include "Platform.h" +#include +#include +#include +#include + +/** + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI + and DXE know about them. + + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully. + +**/ +EFI_STATUS +PeiFvInitialization ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n")); + + // Create a memory allocation HOB for the DXE FV. + // + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE + // firmware volumes at S3 resume too, hence we need to keep away the OS = from + // DXEFV as well. Otherwise we only need to keep away DXE itself from the + // DXEFV area. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdOvmfPeiMemFvBase), + PcdGet32 (PcdOvmfPeiMemFvSize), + EfiBootServicesData + ); + + // + // Let DXE know about the DXE FV + // + BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSiz= e)); + DEBUG (( + DEBUG_INFO, + "Platform builds DXE FV at %x, size %x.\n", + PcdGet32 (PcdOvmfDxeMemFvBase), + PcdGet32 (PcdOvmfDxeMemFvSize) + )); + + // Create a memory allocation HOB for the DXE FV. + // + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE + // firmware volumes at S3 resume too, hence we need to keep away the OS = from + // DXEFV as well. Otherwise we only need to keep away DXE itself from the + // DXEFV area. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdOvmfDxeMemFvBase), + PcdGet32 (PcdOvmfDxeMemFvSize), + EfiBootServicesData + ); + + // + // Let PEI know about the DXE FV so it can find the DXE Core + // + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *)(UINTN)PcdGet32 (PcdOvmfDxeMemFvBase), + PcdGet32 (PcdOvmfDxeMemFvSize), + NULL, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/PlatformPei/RiscV64/MemDetect.c b/OvmfPkg/PlatformPei/= RiscV64/MemDetect.c new file mode 100644 index 000000000000..eb9d24581f8d --- /dev/null +++ b/OvmfPkg/PlatformPei/RiscV64/MemDetect.c @@ -0,0 +1,212 @@ +/** @file + Memory Detection for Virtual Machines. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "Platform.h" + +STATIC EFI_PHYSICAL_ADDRESS SystemMemoryBase; +STATIC UINT64 SystemMemorySize; +STATIC EFI_PHYSICAL_ADDRESS MmodeResvBase; +STATIC UINT64 MmodeResvSize; + +/** + Publish PEI core memory. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +PublishPeiMemory ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + EFI_PHYSICAL_ADDRESS MemoryBase; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + EFI_STATUS Status; + UINT64 CurBase, CurSize; + UINT64 NewBase =3D 0, NewSize =3D 0; + UINT64 MemorySize; + INT32 Node, Prev; + INT32 Len; + VOID *FdtPointer; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + // Look for the lowest memory node + for (Prev =3D 0; ; Prev =3D Node) { + Node =3D fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + + // Check for memory node + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG (( + DEBUG_INFO, + "%a: System RAM @ 0x%lx - 0x%lx\n", + __FUNCTION__, + CurBase, + CurBase + CurSize - 1 + )); + + if ((NewBase > CurBase) || (NewBase =3D=3D 0)) { + NewBase =3D CurBase; + NewSize =3D CurSize; + } + } else { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to parse FDT memory node\n", + __FUNCTION__ + )); + } + } + } + + SystemMemoryBase =3D NewBase; + SystemMemorySize =3D NewSize; + + /* try to locate the reserved memory opensbi node */ + Node =3D fdt_path_offset (FdtPointer, "/reserved-memory/mmode_resv0"); + if (Node >=3D 0) { + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + NewBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + NewSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + DEBUG (( + DEBUG_INFO, + "%a: M-mode Base =3D 0x%lx, M-mode Size =3D 0x%lx\n", + __FUNCTION__, + NewBase, + NewSize + )); + MmodeResvBase =3D NewBase; + MmodeResvSize =3D NewSize; + } + } + + DEBUG (( + DEBUG_INFO, + "%a: SystemMemoryBase:0x%x SystemMemorySize:%x\n", + __FUNCTION__, + SystemMemoryBase, + SystemMemorySize + )); + + // + // Initial 16MB needs to be reserved + // + MemoryBase =3D SystemMemoryBase + SIZE_16MB; + MemorySize =3D SystemMemorySize - SIZE_16MB; + + // + // Publish this memory to the PEI Core + // + Status =3D PublishSystemMemory (MemoryBase, MemorySize); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Publish system RAM and reserve memory regions. + +**/ +VOID +InitializeRamRegions ( + VOID + ) +{ + /* + * M-mode FW can be loaded anywhere in memory but should not overlap + * with the EDK2. This can happen if some other boot code loads the + * M-mode firmware. + * + * The M-mode firmware memory should be marked as reserved memory + * so that OS doesn't use it. + */ + DEBUG (( + DEBUG_INFO, + "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, + MmodeResvBase, + MmodeResvBase + MmodeResvSize + )); + AddReservedMemoryBaseSizeHob (MmodeResvBase, MmodeResvSize); + + if (MmodeResvBase > SystemMemoryBase) { + DEBUG (( + DEBUG_INFO, + "%a: Free Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, + SystemMemoryBase, + MmodeResvBase + )); + AddMemoryRangeHob (SystemMemoryBase, MmodeResvBase); + } + + DEBUG (( + DEBUG_INFO, + "%a: Free Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, + MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize + )); + AddMemoryRangeHob ( + MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize + ); +} diff --git a/OvmfPkg/PlatformPei/RiscV64/Platform.c b/OvmfPkg/PlatformPei/R= iscV64/Platform.c new file mode 100644 index 000000000000..45a2f44d9cca --- /dev/null +++ b/OvmfPkg/PlatformPei/RiscV64/Platform.c @@ -0,0 +1,372 @@ +/** @file + Platform PEI driver + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Platform.h" + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D { + { EfiACPIMemoryNVS, 0x004 }, + { EfiACPIReclaimMemory, 0x008 }, + { EfiReservedMemoryType, 0x004 }, + { EfiRuntimeServicesData, 0x024 }, + { EfiRuntimeServicesCode, 0x030 }, + { EfiBootServicesCode, 0x180 }, + { EfiBootServicesData, 0xF00 }, + { EfiMaxMemoryType, 0x000 } +}; + +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiMasterBootModePpiGuid, + NULL + } +}; + +STATIC EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION; + +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Build reserved memory range resource HOB. + + @param MemoryBase Reserved memory range base address. + @param MemorySize Reserved memory range size. + +**/ +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Build memory map I/O resource using the base address + and the top address of memory range. + + @param MemoryBase Memory map I/O range base address. + @param MemoryLimit The top address of memory map I/O range + +**/ +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Create untested memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE, + MemoryBase, + MemorySize + ); +} + +/** + Create untested memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} + +/** + Add PCI resource. + +**/ +VOID +AddPciResource ( + VOID + ) +{ + // + // Platform-specific + // +} + +/** + Platform memory map initialization. + +**/ +VOID +MemMapInitialization ( + VOID + ) +{ + // + // Create Memory Type Information HOB + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof (mDefaultMemoryTypeInformation) + ); + + // + // Add PCI IO Port space available for PCI resource allocations. + // + AddPciResource (); +} + +/** + Platform misc initialization. + +**/ +VOID +MiscInitialization ( + VOID + ) +{ + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + // TODO: Determine this dynamically from the platform + // setting or the HART configuration. + // + BuildCpuHob (56, 32); +} + +/** + Check if system returns from S3. + + @return BOOLEAN TRUE, system returned from S3 + FALSE, system is not returned from S3 + +**/ +BOOLEAN +CheckResumeFromS3 ( + VOID + ) +{ + // + // Platform implementation-specific + // + return FALSE; +} + +/** + Platform boot mode initialization. + +**/ +VOID +BootModeInitialization ( + VOID + ) +{ + EFI_STATUS Status; + + if (CheckResumeFromS3 ()) { + DEBUG ((DEBUG_INFO, "This is wake from S3\n")); + } else { + DEBUG ((DEBUG_INFO, "This is normal boot\n")); + } + + Status =3D PeiServicesSetBootMode (mBootMode); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesInstallPpi (mPpiBootMode); + ASSERT_EFI_ERROR (Status); +} + +/** + Build processor information for U54 Coreplex processor. + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildCoreInformationHob ( + VOID + ) +{ + // return BuildRiscVSmbiosHobs (); + return EFI_SUCCESS; +} + +/** + Perform Platform PEI initialization. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +InitializePlatform ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); + Status =3D PlatformPeim (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PlatformPeim failed\n")); + ASSERT (FALSE); + } + + BootModeInitialization (); + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n")); + PublishPeiMemory (); + DEBUG ((DEBUG_INFO, "PEI memory published.\n")); + InitializeRamRegions (); + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n")); + + if (mBootMode !=3D BOOT_ON_S3_RESUME) { + PeiFvInitialization (); + MemMapInitialization (); + } + + MiscInitialization (); + Status =3D BuildCoreInformationHob (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n")); + ASSERT (FALSE); + } + + return EFI_SUCCESS; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95738): https://edk2.groups.io/g/devel/message/95738 Mute This Topic: https://groups.io/mt/94664320/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95739+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95739+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136567; cv=none; d=zohomail.com; s=zohoarc; b=Fq5cHeingN/uTn0HmDeD70m9d0Msqv8IQXb4iE4YdDnWK1q2bhIt0jBs+janTGsnrWavBQou2fOxC1bW0qVfgi+TytmMMRhzMy3IHWJHaku5bzZ7QGrIX3RalWsn57w7md0iRKpdvOgH1SzIsVaG5powIlVUlwQAGKvm+ss7AFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136567; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=izQTybzhaIqhyQCUCU1xr+7dwR0n3BhO+inLmobvW4o=; b=nG7/KNRD4DlhwACpQ0hgeceyXfg1CV8fePg50kV7GN0x3fEuV1ubaitlqa4lgFckLWU32vxf3JoshoBSwH/ztoRCXOHAq35qCxQxTx1cHz3BdT4FvalOYxsj+8h6mEnm37jPfRcnWyIOo9vzGhLtvNXE7UZHpFcuNB69ad4emi0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95739+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136567660133.10852347556556; Sun, 30 Oct 2022 06:29:27 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QmrmYY1788612xmbzMDiOOwh; Sun, 30 Oct 2022 06:29:27 -0700 X-Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) by mx.groups.io with SMTP id smtpd.web11.8325.1667136566627080989 for ; Sun, 30 Oct 2022 06:29:26 -0700 X-Received: by mail-pj1-f47.google.com with SMTP id d59-20020a17090a6f4100b00213202d77e1so13779493pjk.2 for ; Sun, 30 Oct 2022 06:29:26 -0700 (PDT) X-Gm-Message-State: y7OnWM2KohK0N701wRhNOuLpx1787277AA= X-Google-Smtp-Source: AMsMyM4ys5pY+cuN0rA5orJoUtz8jwclSIIFOJWFKwmgDKqQDLyqQTWw2tja73ORVoIRqgIMvU6BrA== X-Received: by 2002:a17:903:26ce:b0:186:9029:fa22 with SMTP id jg14-20020a17090326ce00b001869029fa22mr8995924plb.140.1667136565718; Sun, 30 Oct 2022 06:29:25 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:25 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 13/30] UefiCpuPkg/CpuTimerLib: Refactor to allow other architectures Date: Sun, 30 Oct 2022 18:58:25 +0530 Message-Id: <20221030132842.54077-14-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136567; bh=3bRKflQQnWY55gtfTMPAxZsRrXtwPS/IpbiuVS77sWM=; h=Cc:Date:From:Reply-To:Subject:To; b=ilvrkL3KFy06pkvVwGNmLO8w8a8mHS9aXVh9miPEGUcvlPneCb+ipH4VWZPqWsPpyMS 4dbDA+JcLR0V5+3lEf2MuOodlcoBK4n+ddMqT1knurXxkSBQAeylMQtYevcSNejvvn12o YDuuYmTbb0oMbcFRO7HCpVdUTIqmp/hiV/M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136568058100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, CpuTimerLib library supports only X86 architecture. Refactor to allow other CPU architectures. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 6 +++--- UefiCpuPkg/Library/CpuTimerLib/{ =3D> Ia32X64}/BaseCpuTimerLib.c | 0 UefiCpuPkg/Library/CpuTimerLib/{ =3D> Ia32X64}/CpuTimerLib.c | 0 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf b/UefiCpuPk= g/Library/CpuTimerLib/BaseCpuTimerLib.inf index de0648de91b5..4b263965ed90 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf @@ -18,9 +18,9 @@ [Defines] LIBRARY_CLASS =3D TimerLib MODULE_UNI_FILE =3D BaseCpuTimerLib.uni =20 -[Sources] - CpuTimerLib.c - BaseCpuTimerLib.c +[Sources.IA32, Sources.X64] + Ia32X64/CpuTimerLib.c + Ia32X64/BaseCpuTimerLib.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c b/UefiCpuPkg/= Library/CpuTimerLib/Ia32X64/BaseCpuTimerLib.c similarity index 100% rename from UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c rename to UefiCpuPkg/Library/CpuTimerLib/Ia32X64/BaseCpuTimerLib.c diff --git a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c b/UefiCpuPkg/Libr= ary/CpuTimerLib/Ia32X64/CpuTimerLib.c similarity index 100% rename from UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c rename to UefiCpuPkg/Library/CpuTimerLib/Ia32X64/CpuTimerLib.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95739): https://edk2.groups.io/g/devel/message/95739 Mute This Topic: https://groups.io/mt/94664321/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95740+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95740+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136570; cv=none; d=zohomail.com; s=zohoarc; b=izCTnXXoRySf0DzZyeg921VnCV5zoGXaj6/wT+S6bOyr4NTTGj7hJRtZIBiEaO2uu/QiVkiQKfrd99z0YQikUezAeB2xuL9VaU1SWYkdpMd0KreLr/4QHCmAC/kvJfnzsMO7FWaxr11PGyaG4qzI3e//PloCYi6gwaNUKKmXr5k= ARC-Message-Signature: i=1; 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Sun, 30 Oct 2022 06:29:29 -0700 X-Received: by mail-pf1-f178.google.com with SMTP id 130so8574207pfu.8 for ; Sun, 30 Oct 2022 06:29:28 -0700 (PDT) X-Gm-Message-State: pRQpSTB54mKZhc7FbmxpxYWVx1787277AA= X-Google-Smtp-Source: AMsMyM7chftN27foiJBI2oAyKmu3tqufz/MJ1h3cY9qFUah0DtSfturVBofeFkXdcBSyhEhPbDwlPA== X-Received: by 2002:a05:6a00:23cc:b0:56c:12c0:aaf7 with SMTP id g12-20020a056a0023cc00b0056c12c0aaf7mr9425354pfc.0.1667136568196; Sun, 30 Oct 2022 06:29:28 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:27 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 14/30] UefiCpuPkg/CpuTimerLib: Add support for RISC-V Date: Sun, 30 Oct 2022 18:58:26 +0530 Message-Id: <20221030132842.54077-15-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136569; bh=oUfBPBEConCsC3Xhn5kG6cM3Ng9qKkTw2CKFaucluxo=; h=Cc:Date:From:Reply-To:Subject:To; b=VUsnnn6Rf/3Ehbzkf2INFGPYco/3vIoBHOIboxc0+wsESvUs/6A09RMkY/aACk6U0uf b24HdB5NvNwvpwFDclk2zHVdiGG+yLRaWQiODoh1jcqVlE/lXJqw500AQjhbHBplrRls1 FYuNr27CR24RM7havj4GDiID13Rx+RKx1oY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136572102100003 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 3 + UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 +++++++++++++++= +++++ 2 files changed, 202 insertions(+) diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf b/UefiCpuPk= g/Library/CpuTimerLib/BaseCpuTimerLib.inf index 4b263965ed90..4492ee26caae 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf @@ -22,6 +22,9 @@ [Sources.IA32, Sources.X64] Ia32X64/CpuTimerLib.c Ia32X64/BaseCpuTimerLib.c =20 +[Sources.RISCV64] + RiscV64/CpuTimerLib.c + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c b/UefiCpu= Pkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 000000000000..9c8efc0f3530 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,199 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D RiscVReadTimer () + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS = - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuC= oreCrystalClockFrequency), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= PcdGet64 (PcdCpuCoreCrystalClockFrequency)); + + return NanoSeconds; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95740): https://edk2.groups.io/g/devel/message/95740 Mute This Topic: https://groups.io/mt/94664322/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95741+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95741+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136572; cv=none; d=zohomail.com; s=zohoarc; b=GQfwlnMzy/i4Qe6ZWmG1dWz+t3IhDjtUDdOM3R1yYtAcMBWiVMut3FNLUEMGunbLer84U3vkUDE/mnu0ojaAFnQ+oVwXqVnooyvZem0juuwPVtTd3J+zBHbuYmP2F320dFWbJXYwCJOGb6FTvdUcTc0OXtO2zDS1XBS8dOSMWt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136572; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AKEZ0RR0IJlAvqDMpUy2BftByybX+puV2wPgP7btmxA=; b=aRRvciEijeknYDhwJRc/06msMC2SRa+u/dgb1E2L4x3kPiRnUWmJ2HLn66v73dHhHtryHbuVRA7lYGYYp4jGd4sq/I2Re0zScNAlGP7OekCjeVCkBfPb8/cJEeJYbloxsWJm6p2qNOA8rpPYwHVuf7EEPMv6UEEFwhUUXdD+/ew= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95741+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136572358428.61345835750194; Sun, 30 Oct 2022 06:29:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3MhKYY1788612xJ2P4fM0aBz; Sun, 30 Oct 2022 06:29:32 -0700 X-Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by mx.groups.io with SMTP id smtpd.web08.8059.1667136571356207926 for ; Sun, 30 Oct 2022 06:29:31 -0700 X-Received: by mail-pf1-f175.google.com with SMTP id d10so8568065pfh.6 for ; Sun, 30 Oct 2022 06:29:31 -0700 (PDT) X-Gm-Message-State: PHw3GpIAlyBxRhyvfrNWxe4ex1787277AA= X-Google-Smtp-Source: AMsMyM4YGRk+4DkV2dF7i7FgX/6BpqwFOJs1rVT3x5ITEsoJKtIJskpDreM2i4Z6esoiC2XQwHlPlQ== X-Received: by 2002:a63:5d5b:0:b0:46e:f010:d0f7 with SMTP id o27-20020a635d5b000000b0046ef010d0f7mr7998986pgm.585.1667136570589; Sun, 30 Oct 2022 06:29:30 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:29 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 15/30] UefiCpuPkg/CpuExceptionHandlerLib: Refactor to allow other architectures Date: Sun, 30 Oct 2022 18:58:27 +0530 Message-Id: <20221030132842.54077-16-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136572; bh=UmROKUuNT/ENSKpzacEKqKyJs0RAK5kEWCYuOnjNTDg=; h=Cc:Date:From:Reply-To:Subject:To; b=brrgYqCshXlO9POim7uAz/2N6SFHeKSseMOpdnj/aYg4LIAy13oMLiKzndEIonR565q CpfP4LmuL+PpWGse0Rq16/+IiQvyRznNRVZyeL+CrakzCxDcyuG4wodBFBDCz4UOicQIO SufGAr/OGpRO9JQtxhoKGfhpKy8dBTmebLc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136574111100006 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, the CpuExceptionHandlerLib library supports only X86. Refactor the library to allow adding other CPU architectures. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 14 ++++++++------ UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf = | 8 ++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf= | 12 +++++++----- UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf = | 8 ++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerL= ib.inf | 6 +++--- UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/CpuExceptionComm= on.h | 0 UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/CpuExceptionComm= on.c | 0 UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/DxeException.c = | 0 UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/PeiCpuException.= c | 0 UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/PeiDxeSmmCpuExce= ption.c | 0 UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/SecPeiCpuExcepti= on.c | 0 UefiCpuPkg/Library/CpuExceptionHandlerLib/{ =3D> Ia32X64}/SmmException.c = | 0 12 files changed, 26 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index e7a81bebdb13..8fdf2b756c2c 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -32,11 +32,11 @@ [Sources.X64] X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h =20 -[Sources.common] - CpuExceptionCommon.h - CpuExceptionCommon.c - PeiDxeSmmCpuException.c - DxeException.c +[Sources.IA32, Sources.X64] + Ia32X64/CpuExceptionCommon.h + Ia32X64/CpuExceptionCommon.c + Ia32X64/PeiDxeSmmCpuException.c + Ia32X64/DxeException.c =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard @@ -56,8 +56,10 @@ [LibraryClasses] SerialPortLib PrintLib SynchronizationLib - LocalApicLib PeCoffGetEntryPointLib MemoryAllocationLib DebugLib + +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib VmgExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index 7c2ec3b2db4c..af4899e6885e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -33,10 +33,10 @@ [Sources.X64] X64/ArchInterruptDefs.h =20 [Sources.common] - CpuExceptionCommon.h - CpuExceptionCommon.c - PeiCpuException.c - PeiDxeSmmCpuException.c + Ia32X64/CpuExceptionCommon.h + Ia32X64/CpuExceptionCommon.c + Ia32X64/PeiCpuException.c + Ia32X64/PeiDxeSmmCpuException.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index 6a170286c8fc..79911b21f62d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -32,10 +32,10 @@ [Sources.X64] X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h =20 -[Sources.common] - CpuExceptionCommon.h - CpuExceptionCommon.c - SecPeiCpuException.c +[Sources.IA32, Sources.X64] + Ia32X64/CpuExceptionCommon.h + Ia32X64/CpuExceptionCommon.c + Ia32X64/SecPeiCpuException.c =20 [Packages] MdePkg/MdePkg.dec @@ -46,8 +46,10 @@ [LibraryClasses] BaseLib SerialPortLib PrintLib - LocalApicLib PeCoffGetEntryPointLib + +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib VmgExitLib =20 [Pcd] diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 9dde07612a04..249446588bfa 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -33,10 +33,10 @@ [Sources.X64] X64/ArchInterruptDefs.h =20 [Sources.common] - CpuExceptionCommon.h - CpuExceptionCommon.c - PeiDxeSmmCpuException.c - SmmException.c + Ia32X64/CpuExceptionCommon.h + Ia32X64/CpuExceptionCommon.c + Ia32X64/PeiDxeSmmCpuException.c + Ia32X64/SmmException.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index 6d2f66504a5b..23200437eb8b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -38,9 +38,9 @@ [Sources.X64] X64/ArchInterruptDefs.h =20 [Sources.common] - CpuExceptionCommon.h - CpuExceptionCommon.c - SecPeiCpuException.c + Ia32X64/CpuExceptionCommon.h + Ia32X64/CpuExceptionCommon.c + Ia32X64/SecPeiCpuException.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/CpuExceptionCommon.h similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/CpuExceptionCom= mon.h diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/CpuExceptionCommon.c similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/CpuExceptionCom= mon.c diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/DxeException.c similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/DxeException.c diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/PeiCpuException.c similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/PeiCpuException= .c diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuExceptio= n.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/PeiDxeSmmCpuExcepti= on.c similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException= .c rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/PeiDxeSmmCpuExc= eption.c diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/SecPeiCpuException.c similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/SecPeiCpuExcept= ion.c diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/SmmException.c similarity index 100% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32X64/SmmException.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95741): https://edk2.groups.io/g/devel/message/95741 Mute This Topic: https://groups.io/mt/94664323/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95742+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95742+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136575; cv=none; d=zohomail.com; s=zohoarc; b=KK5VORmOK1m9TRU2d6E99Q7uvaATYOnzmLgTbIWKlFpvhiIjp6tMCLb/HfjSNjmH8kDpmVfEuZFvCyfrxyC2NOifJZ18jLehtIjXU24+P7oO0CBvO0WVZ5g5QhOWyb7Wmto7OEYptVsr09absNSP4Kq4iZ6s9Wjrj6W03Dbwe60= ARC-Message-Signature: i=1; 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Sun, 30 Oct 2022 06:29:34 -0700 X-Received: by mail-pg1-f178.google.com with SMTP id q1so8607363pgl.11 for ; Sun, 30 Oct 2022 06:29:33 -0700 (PDT) X-Gm-Message-State: qnLbKTtlXhBU33KlhfMspSyTx1787277AA= X-Google-Smtp-Source: AMsMyM6opBHdyhLM003rTNzR1ehiGwFK12YJNRkxPmVVe5oojCH4FuCJqFF9JLGlsFLh9+VEiNU/+A== X-Received: by 2002:a05:6a00:c8d:b0:56d:370f:2003 with SMTP id a13-20020a056a000c8d00b0056d370f2003mr5101473pfv.76.1667136573148; Sun, 30 Oct 2022 06:29:33 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:32 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 16/30] UefiCpuPkg/CpuExceptionHandlerLib: Add support for RISC-V Date: Sun, 30 Oct 2022 18:58:28 +0530 Message-Id: <20221030132842.54077-17-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136574; bh=t/cSgSs6Q7/aHVKAjLLlApxwUcff7KtHFY9nzq4YBBw=; h=Cc:Date:From:Reply-To:Subject:To; b=LO+cGE2C+4PK2xLLJrtwfP/jfI8jfqluDR6e9+w6sEMiwr8fE3OnDqtF5GpHa6gKzvz DSA3rWCRroeaa/5694Tp4aukEDk6g4wQMhemqHXyZVuf5mHx+y8eut8vqLNLAoAzVWg8C Y+UTgfMBNYeC3WZTTGJpKgOSNrQu/o4ogQ0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136576134100010 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 7 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf= | 7 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h= | 116 +++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c= | 133 ++++++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S = | 105 ++++++++++++++++ 5 files changed, 366 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index 8fdf2b756c2c..b24140d1f26b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -18,7 +18,7 @@ [Defines] # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.Ia32] @@ -38,6 +38,11 @@ [Sources.IA32, Sources.X64] Ia32X64/PeiDxeSmmCpuException.c Ia32X64/DxeException.c =20 +[Sources.RISCV64] + RiscV64/SupervisorTrapHandler.S + RiscV64/CpuExceptionHandlerLib.c + RiscV64/CpuExceptionHandlerLib.h + [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index 79911b21f62d..60c92ecf65bf 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -18,7 +18,7 @@ [Defines] # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.Ia32] @@ -37,6 +37,11 @@ [Sources.IA32, Sources.X64] Ia32X64/CpuExceptionCommon.c Ia32X64/SecPeiCpuException.c =20 +[Sources.RISCV64] + RiscV64/SupervisorTrapHandler.S + RiscV64/CpuExceptionHandlerLib.c + RiscV64/CpuExceptionHandlerLib.h + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.h new file mode 100644 index 000000000000..30f47e87552b --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.h @@ -0,0 +1,116 @@ +/** @file + + RISC-V Exception Handler library definition file. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_ +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_ + +#include + +/** + Trap Handler for S-mode + +**/ +VOID +SupervisorModeTrap ( + VOID + ); + +// +// Index of SMode trap register +// +#define SMODE_TRAP_REGS_zero 0 +#define SMODE_TRAP_REGS_ra 1 +#define SMODE_TRAP_REGS_sp 2 +#define SMODE_TRAP_REGS_gp 3 +#define SMODE_TRAP_REGS_tp 4 +#define SMODE_TRAP_REGS_t0 5 +#define SMODE_TRAP_REGS_t1 6 +#define SMODE_TRAP_REGS_t2 7 +#define SMODE_TRAP_REGS_s0 8 +#define SMODE_TRAP_REGS_s1 9 +#define SMODE_TRAP_REGS_a0 10 +#define SMODE_TRAP_REGS_a1 11 +#define SMODE_TRAP_REGS_a2 12 +#define SMODE_TRAP_REGS_a3 13 +#define SMODE_TRAP_REGS_a4 14 +#define SMODE_TRAP_REGS_a5 15 +#define SMODE_TRAP_REGS_a6 16 +#define SMODE_TRAP_REGS_a7 17 +#define SMODE_TRAP_REGS_s2 18 +#define SMODE_TRAP_REGS_s3 19 +#define SMODE_TRAP_REGS_s4 20 +#define SMODE_TRAP_REGS_s5 21 +#define SMODE_TRAP_REGS_s6 22 +#define SMODE_TRAP_REGS_s7 23 +#define SMODE_TRAP_REGS_s8 24 +#define SMODE_TRAP_REGS_s9 25 +#define SMODE_TRAP_REGS_s10 26 +#define SMODE_TRAP_REGS_s11 27 +#define SMODE_TRAP_REGS_t3 28 +#define SMODE_TRAP_REGS_t4 29 +#define SMODE_TRAP_REGS_t5 30 +#define SMODE_TRAP_REGS_t6 31 +#define SMODE_TRAP_REGS_sepc 32 +#define SMODE_TRAP_REGS_sstatus 33 +#define SMODE_TRAP_REGS_sie 34 +#define SMODE_TRAP_REGS_last 35 + +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__) +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last) + +#pragma pack(1) +typedef struct { + // + // Below are follow the format of EFI_SYSTEM_CONTEXT + // + UINT64 zero; + UINT64 ra; + UINT64 sp; + UINT64 gp; + UINT64 tp; + UINT64 t0; + UINT64 t1; + UINT64 t2; + UINT64 s0; + UINT64 s1; + UINT64 a0; + UINT64 a1; + UINT64 a2; + UINT64 a3; + UINT64 a4; + UINT64 a5; + UINT64 a6; + UINT64 a7; + UINT64 s2; + UINT64 s3; + UINT64 s4; + UINT64 s5; + UINT64 s6; + UINT64 s7; + UINT64 s8; + UINT64 s9; + UINT64 s10; + UINT64 s11; + UINT64 t3; + UINT64 t4; + UINT64 t5; + UINT64 t6; + // + // Below are the additional information to + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap + // and not public to EFI environment. + // + UINT64 sepc; + UINT64 sstatus; + UINT64 sie; +} SMODE_TRAP_REGISTERS; +#pragma pack() + +#endif diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.c new file mode 100644 index 000000000000..f1ee7d236aec --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.c @@ -0,0 +1,133 @@ +/** @file + RISC-V Exception Handler library implementation. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "CpuExceptionHandlerLib.h" + +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; + +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + RiscVSetSupervisorStvec ((UINT64)SupervisorModeTrap); + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler)); + mInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} + +/** + Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. + + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. + + @retval EFI_SUCCESS The stacks are assigned successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. +**/ +EFI_STATUS +EFIAPI +InitializeSeparateExceptionStacks ( + IN VOID *Buffer, + IN OUT UINTN *BufferSize + ) +{ + return EFI_SUCCESS; +} + +/** + Supervisor mode trap handler. + + @param[in] SmodeTrapReg Registers before trap occurred. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + SMODE_TRAP_REGISTERS *SmodeTrapReg + ) +{ + UINTN SCause; + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg; + // + // Check scasue register. + // + SCause =3D (UINTN)RiscVGetSupervisorTrapCause (); + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) { + // + // This is interrupt event. + // + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1)); + if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) { + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext); + } + } +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTr= apHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorT= rapHandler.S new file mode 100644 index 000000000000..649c4c5becf4 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandl= er.S @@ -0,0 +1,105 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuExceptionHandlerLib.h" + + .align 3 + .section .entry, "ax", %progbits + .globl SupervisorModeTrap +SupervisorModeTrap: + addi sp, sp, -SMODE_TRAP_REGS_SIZE + + /* Save all general regisers except SP */ + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + csrr t0, CSR_SSTATUS + and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE) + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + csrr t0, CSR_SEPC + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrr t0, CSR_SIE + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP */ + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrw CSR_SEPC, t0 + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + csrw CSR_SIE, t0 + csrr t0, CSR_SSTATUS + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + or t0, t0, t1 + csrw CSR_SSTATUS, t0 + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + addi sp, sp, SMODE_TRAP_REGS_SIZE + sret --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95742): https://edk2.groups.io/g/devel/message/95742 Mute This Topic: https://groups.io/mt/94664325/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95743+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95743+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136578; cv=none; d=zohomail.com; s=zohoarc; b=ZoqT9HIi+dI76iAZUfK66EQ5C8pPns/x5JDuwlOfMibVGD/sh04x+35JZPYfQN+sohFkpqeZdHpJDuINTVecOtq7sKadVQ68jdnBnw8feH4LtP8OEk8mvsWQQcnyDAd0Hp7/En4BiyqYjE4zh9Q2cfJN82/LE7KJ0eg3mKiyGQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136578; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FU+hS4QiCi+FJ8y8wMZIX4DwZgQyF3X8LonmT1Ly+RI=; b=hJ8kUB63rVXr+t+80+SxqfaMY7jWk8SgAcqkBhYke9N0Ic74bAOf6mSGUcbohTYg6BHxP9d1eJA9jKhe4d0LAwlyWTvQsos3MIPUbM5QU2vpc4KLNyOMbue1pLF+DVsh3Y/f+beemLMEeFxIBFsJRmiq1i/JE7i4GDQi2lV188w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95743+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136578285827.1958377559665; Sun, 30 Oct 2022 06:29:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id zTgoYY1788612xwqL2NqSNxr; Sun, 30 Oct 2022 06:29:37 -0700 X-Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web08.8061.1667136576355143813 for ; Sun, 30 Oct 2022 06:29:36 -0700 X-Received: by mail-pf1-f172.google.com with SMTP id g62so8556792pfb.10 for ; Sun, 30 Oct 2022 06:29:36 -0700 (PDT) X-Gm-Message-State: 2AReZTcCjPqOuEAamvanxZZDx1787277AA= X-Google-Smtp-Source: AMsMyM5KiDHAMW9Z55d0ZD+NwnbEN0XD1Y2W5HjnOKepv1e/4Uyiws7w/7WLwfGEbZfVsp8oC7ueZw== X-Received: by 2002:a05:6a00:15c8:b0:565:bc96:1c5b with SMTP id o8-20020a056a0015c800b00565bc961c5bmr9218968pfu.52.1667136575699; Sun, 30 Oct 2022 06:29:35 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:34 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 17/30] UefiCpuPkg/CpuDxe: Refactor to allow other architectures Date: Sun, 30 Oct 2022 18:58:29 +0530 Message-Id: <20221030132842.54077-18-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136577; bh=I+6imPOaFpPoEYTiWDJR0azfmmrnNxtRxJ2FqISSBHM=; h=Cc:Date:From:Reply-To:Subject:To; b=kwIlUnyOzLmomNiVKRVh7IRnDDrcW3ffVxiNA/qDEp283nUerSc5H2ADFAnuLW00vOM XoB9kX6ZiwfTyORhBcfQGBmcZ3seSITPtuOCCREQQ71osRJXIwTBEw7E6Br9A3HyKlws+ xWWbFfn8JiMDG+fjj4XopPLt5S16ptlG7q0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136580109100015 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Currently, CpuDxe supports only X86 architecture. To add support for other architectures like RISC-V, this need to be refactored. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 28 +++++++++++--------- UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuDxe.h | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuGdt.h | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuMp.h | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuPageTable.h | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuDxe.c | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuGdt.c | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuMp.c | 0 UefiCpuPkg/CpuDxe/{ =3D> Ia32X64}/CpuPageTable.c | 0 9 files changed, 15 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 235241899222..65961813f74b 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -29,28 +29,30 @@ [LibraryClasses] DebugLib DxeServicesTableLib MemoryAllocationLib - MtrrLib UefiBootServicesTableLib UefiDriverEntryPoint - LocalApicLib - UefiCpuLib UefiLib CpuExceptionHandlerLib HobLib ReportStatusCodeLib - MpInitLib TimerLib PeCoffGetEntryPointLib =20 -[Sources] - CpuDxe.c - CpuDxe.h - CpuGdt.c - CpuGdt.h - CpuMp.c - CpuMp.h - CpuPageTable.h - CpuPageTable.c +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib + MpInitLib + MtrrLib + UefiCpuLib + +[Sources.IA32, Sources.X64] + Ia32X64/CpuDxe.c + Ia32X64/CpuDxe.h + Ia32X64/CpuGdt.c + Ia32X64/CpuGdt.h + Ia32X64/CpuMp.c + Ia32X64/CpuMp.h + Ia32X64/CpuPageTable.h + Ia32X64/CpuPageTable.c =20 [Sources.IA32] Ia32/CpuAsm.nasm diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/Ia32X64/CpuDxe.h similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuDxe.h rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuDxe.h diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/Ia32X64/CpuGdt.h similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuGdt.h rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuGdt.h diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/Ia32X64/CpuMp.h similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuMp.h rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuMp.h diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/Ia32X64/C= puPageTable.h similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuPageTable.h rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuPageTable.h diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/Ia32X64/CpuDxe.c similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuDxe.c rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuDxe.c diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/Ia32X64/CpuGdt.c similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuGdt.c rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuGdt.c diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/Ia32X64/CpuMp.c similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuMp.c rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuMp.c diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/Ia32X64/C= puPageTable.c similarity index 100% rename from UefiCpuPkg/CpuDxe/CpuPageTable.c rename to UefiCpuPkg/CpuDxe/Ia32X64/CpuPageTable.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95743): https://edk2.groups.io/g/devel/message/95743 Mute This Topic: https://groups.io/mt/94664326/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95744+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95744+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136579; cv=none; d=zohomail.com; s=zohoarc; b=SxFqvzbM+6kwu+rK5RDkHABhSTOJln/S8NjPVyqAhBjxy9rLtvFaQAgYyB/HJicPv3KCtJxpTo1y11KpnCdT04ujLx9TaRbnEdZDxwcSR08+35Ku+hL55ResrZIafGNuEitLTzFSuM0zcu+GaC0jooAvKV5s1WWk5ZGX2RwWd6U= ARC-Message-Signature: i=1; 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Sun, 30 Oct 2022 06:29:38 -0700 X-Received: by mail-pl1-f172.google.com with SMTP id p21so4791811plr.7 for ; Sun, 30 Oct 2022 06:29:38 -0700 (PDT) X-Gm-Message-State: MeQKP6KllZOE7q7UPBf5ih2Tx1787277AA= X-Google-Smtp-Source: AMsMyM4A3v5sr+BSGKmN+P26H8huB0iSaul63P8H0Pe8NfxoC/2k0IjQF3TuqbIbpw2X41YgaI6UVg== X-Received: by 2002:a17:902:f551:b0:186:be04:6670 with SMTP id h17-20020a170902f55100b00186be046670mr9185425plf.159.1667136578016; Sun, 30 Oct 2022 06:29:38 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:37 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 18/30] UefiCpuPkg/CpuDxe: Add support for RISC-V Date: Sun, 30 Oct 2022 18:58:30 +0530 Message-Id: <20221030132842.54077-19-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136579; bh=px+MdFTpIt44B4zBdIHDzwVzZMiv2EeTcxYXjnm+Sp0=; h=Cc:Date:From:Reply-To:Subject:To; b=wOqTnnz7paRz1pv0413lO/knJ8KmnW9r6gQM3SCrxRDGHDZrJ7l+PQzCsSt8cioh/sv I4jIzWz7oFNUXKMAEMHPUmUm9DJyG770twrkqtts1bfGQhJSEqc9/PbyAnHLK4049UZ2H 7CF//JwxGNx568O6IsETBqccH4wCjOso1Eg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136580145100016 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 10 + UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 199 +++++++++++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 307 ++++++++++++++++++++ 3 files changed, 516 insertions(+) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 65961813f74b..eddc86a38965 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -44,6 +44,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] MtrrLib UefiCpuLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + [Sources.IA32, Sources.X64] Ia32X64/CpuDxe.c Ia32X64/CpuDxe.h @@ -62,6 +65,10 @@ [Sources.X64] X64/CpuAsm.nasm X64/PagingAttribute.c =20 +[Sources.RISCV64] + RiscV64/CpuDxe.c + RiscV64/CpuDxe.h + [Protocols] gEfiCpuArchProtocolGuid ## PRODUCES gEfiMpServiceProtocolGuid ## PRODUCES @@ -84,6 +91,9 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask ##= CONSUMES =20 +[Pcd.RISCV64] + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##= CONSUMES + [Depex] TRUE =20 diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.h new file mode 100644 index 000000000000..49f4e119665a --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h @@ -0,0 +1,199 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef CPU_DXE_H_ +#define CPU_DXE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c new file mode 100644 index 000000000000..9f557b776a09 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -0,0 +1,307 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuDxe.h" + +// +// Global Variables +// +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + mInterruptState =3D TRUE; + return EFI_SUCCESS; +} + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + mInterruptState =3D FALSE; + return EFI_SUCCESS; +} + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D mInterruptState; + return EFI_SUCCESS; +} + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + if (TimerValue =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (TimerIndex !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + *TimerValue =3D (UINT64)RiscVReadTimer (); + if (TimerPeriod !=3D NULL) { + *TimerPeriod =3D DivU64x32 ( + 1000000000000000u, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ); + } + + return EFI_SUCCESS; +} + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__)); + return EFI_SUCCESS; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + InitializeCpuExceptionHandlers(NULL); + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, + &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95744): https://edk2.groups.io/g/devel/message/95744 Mute This Topic: https://groups.io/mt/94664329/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95745+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95745+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136582; cv=none; d=zohomail.com; s=zohoarc; b=kFxBd+XbqwIdGxoIyndQj1fg6M2aP+xofobbeJJ8HkIePd6EDTQTgBTTPck8k9E19A8TifBJE6sXEncWbjIKgUBCgXnWDQhfbfHggIa9Qsa+ut00eCdaUnqwM6OrIcJr6gWx45X8RMVJ3BgHRzCk08TIyPrtrTWujwlE7O8scJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136582; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1Zy1OKu+NwvPR5y7wg9M6jki1ngyeC56AAbvMtzwa40=; b=ipHq/i3iMd2VnDvmm7+uJbK8GebPh03UBoz22zvXA3RIljdVuxQFEtIiwn4/DYA5aKx13FdIULOPKo2HuwekYyOFLxzOA0EleFSkoLZW1JmUJF09U/UeYRhbP1nYziWhgye9YREqywruUd//DMTOQfEW3W8FR1Ovnved2JP0LO4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95745+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136582191127.59936997434056; Sun, 30 Oct 2022 06:29:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id a8aQYY1788612xWwhlpJrHfh; Sun, 30 Oct 2022 06:29:41 -0700 X-Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) by mx.groups.io with SMTP id smtpd.web11.8328.1667136581208830893 for ; Sun, 30 Oct 2022 06:29:41 -0700 X-Received: by mail-pg1-f176.google.com with SMTP id f193so8671903pgc.0 for ; Sun, 30 Oct 2022 06:29:41 -0700 (PDT) X-Gm-Message-State: nk4LDLtkqHYAJIz7Y1akxRc8x1787277AA= X-Google-Smtp-Source: AMsMyM6eOoIp6NbteoSsDECMUKV3o5B1EGPJm0fg1B8a9ycCg7LRVSZ0uSHgEDTCvLHPNmfXHZlc2A== X-Received: by 2002:a63:de0e:0:b0:46f:23c6:e7d9 with SMTP id f14-20020a63de0e000000b0046f23c6e7d9mr8197840pgg.68.1667136580510; Sun, 30 Oct 2022 06:29:40 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:40 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 19/30] UefiCpuPkg/CpuDxe: Add RISCV_EFI_BOOT_PROTOCOL support Date: Sun, 30 Oct 2022 18:58:31 +0530 Message-Id: <20221030132842.54077-20-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136581; bh=li8XQ3Ua9pissZezlVqY4SLuILT+IM6uRqkErExrdK8=; h=Cc:Date:From:Reply-To:Subject:To; b=cIa2wVtV5ytdSnp7uUnd/n+f9SjZo7ZfpGLBwmZx+/tAJHcyGOtmCatYqsACcQedF6U zmMZ3kWog394PgRhkCgjpH25M1cdxlBEiUVF4difVRLuhIfL2xh2lvY+FsjgOJgOl1jqS 07KsGnaG50xMk9LzoMTX3Mk23ZrNASl5N/0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136584153100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_U= EFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.dsc | 12 ++-- UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++-- 3 files changed, 71 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 0e1a99ddc09f..aaf761fdcf48 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -125,9 +125,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i= nf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -144,10 +148,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i= nf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandle= rLib.inf diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index eddc86a38965..857b84ac3122 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -74,6 +74,9 @@ [Protocols] gEfiMpServiceProtocolGuid ## PRODUCES gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES =20 +[Protocols.RISCV64] + gRiscVEfiBootProtocolGuid ## PRODUCES + [Guids] gIdleLoopEventGuid ## CONSUMES ## E= vent gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## S= ystemTable diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. =20 Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -12,8 +13,41 @@ // // Global Variables // -STATIC BOOLEAN mInterruptState =3D FALSE; -STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is = not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; =20 EFI_CPU_ARCH_PROTOCOL gCpu =3D { CpuFlushCpuDataCache, @@ -284,15 +318,39 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; =20 - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + InitializeCpuExceptionHandlers (NULL); =20 // // Make sure interrupts are disabled // DisableInterrupts (); =20 + // + // Install Boot protocol + // + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95745): https://edk2.groups.io/g/devel/message/95745 Mute This Topic: https://groups.io/mt/94664331/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95746+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95746+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136584; cv=none; d=zohomail.com; s=zohoarc; b=AlBGon8YwwZgMzdjkdlVuPHRWPvhI/eERA9s5wmy28a1szT/a0I8nCAyX4ZfXRYG5f7ooOmUZjDorGqx085GAcRejGYPlSVAXhsH1PnvNsOeoHdbfyqdAX1OMqc/uzVbPHiet44mnGdnnqBJi3Uit4YVCqST1VO3pA/X71IDF2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=F1T9zJPS7MgvIwPNL+/RarkT6dD9o5rdhOSl8oD3OTA=; b=lCwR2Xgg0Qr3tfmqZoW2cYhlvLjq/yAVtLKbsjuv/lSxOyCLMdG3JnO+RJJNplvBLvELxwqRXnGGbIjAKt+ZPJYNxF0gCL/mrhYgtnDjwez9ZQPVpzw0VRNF6t2bCK1YFGtE5VbfI/K3X2BV+3XbtKaWoIsxrqtdz9OJFK8zWTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95746+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136584761583.8567124891578; Sun, 30 Oct 2022 06:29:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CjNMYY1788612xNu69IeoIKA; Sun, 30 Oct 2022 06:29:44 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web11.8332.1667136583793692175 for ; Sun, 30 Oct 2022 06:29:43 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id io19so8650586plb.8 for ; Sun, 30 Oct 2022 06:29:43 -0700 (PDT) X-Gm-Message-State: FFgeXD6TD3sm7tMlmccxjj6Sx1787277AA= X-Google-Smtp-Source: AMsMyM4XApKLWIUdZeM7iUU9C/CFjY0WvCA7B2+ZBqskZH13SZm0p9V1zYViPDEIUlYfzSIB2Z7TJg== X-Received: by 2002:a17:90b:11d4:b0:212:ee83:481 with SMTP id gv20-20020a17090b11d400b00212ee830481mr9471389pjb.36.1667136583021; Sun, 30 Oct 2022 06:29:43 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:42 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 20/30] UefiCpuPkg: Add CpuTimerDxe module Date: Sun, 30 Oct 2022 18:58:32 +0530 Message-Id: <20221030132842.54077-21-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136584; bh=FkIM8TFW+qwtjLI1ytw5n8VWYNWB5xT3oVBzwZuY7BI=; h=Cc:Date:From:Reply-To:Subject:To; b=jNjdDkbIQejYWnc5LNeoK28/zgUfPB96disFaD2dSED1ul/iCy+SvGRVwTGUGrewIiu 7zvvqxGSEfB/mbq7BYciubKoypfqST5NuaYl9DITM6IPSQgktzvkAmcl1Zm/eDUZchZkw vxSWnCIfHWCSMq4bQzrcDD55fSoGYEZUGrc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136586175100006 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.dsc | 3 + UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf | 51 ++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h | 177 ++++++++++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c | 294 ++++++++++++++++++++ UefiCpuPkg/CpuTimerDxe/CpuTimer.uni | 14 + UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni | 12 + 6 files changed, 551 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index aaf761fdcf48..a783e261e604 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -187,5 +187,8 @@ [Components.IA32, Components.X64] [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandle= rLibUnitTest.inf =20 +[Components.RISCV64] + UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf + [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf b/UefiCpuPkg/CpuTimerDx= e/CpuTimerDxe.inf new file mode 100644 index 000000000000..d7706328b591 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf @@ -0,0 +1,51 @@ +## @file +# Timer Arch protocol module +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D CpuTimerDxe + MODULE_UNI_FILE =3D CpuTimer.uni + FILE_GUID =3D 055DDAC6-9142-4013-BF20-FC2E5BC325C9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D TimerDriverInitialize +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + CpuLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Sources.RISCV64] + RiscV64/Timer.h + RiscV64/Timer.c + +[Protocols] + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiTimerArchProtocolGuid ## PRODUCES + +[Depex] + gEfiCpuArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + CpuTimerExtra.uni diff --git a/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h b/UefiCpuPkg/CpuTimerDx= e/RiscV64/Timer.h new file mode 100644 index 000000000000..586eb0cfadb4 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h @@ -0,0 +1,177 @@ +/** @file + RISC-V Timer Architectural Protocol definitions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TIMER_H_ +#define TIMER_H_ + +#include + +#include +#include + +#include +#include +#include +#include + +// +// RISC-V use 100us timer. +// The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units +// +#define DEFAULT_TIMER_TICK_DURATION 100000 + +extern VOID +RiscvSetTimerPeriod ( + UINT32 TimerPeriod + ); + +// +// Function Prototypes +// + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +; + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +; + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +; + +#endif diff --git a/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c b/UefiCpuPkg/CpuTimerDx= e/RiscV64/Timer.c new file mode 100644 index 000000000000..db153f715e60 --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c @@ -0,0 +1,294 @@ +/** @file + RISC-V Timer Architectural Protocol + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "Timer.h" + +// +// The handle onto which the Timer Architectural Protocol will be installed +// +STATIC EFI_HANDLE mTimerHandle =3D NULL; + +// +// The Timer Architectural Protocol that this driver produces +// +EFI_TIMER_ARCH_PROTOCOL mTimer =3D { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +// +// Pointer to the CPU Architectural Protocol instance +// +EFI_CPU_ARCH_PROTOCOL *mCpu; + +// +// The notification function to call on every timer interrupt. +// A bug in the compiler prevents us from initializing this here. +// +STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; + +// +// The current period of the timer interrupt +// +STATIC UINT64 mTimerPeriod =3D 0; + +/** + Timer Interrupt Handler. + + @param InterruptType The type of interrupt that occured + @param SystemContext A pointer to the system context when the interru= pt occured +**/ +VOID +EFIAPI +TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 RiscvTimer; + + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + if (mTimerNotifyFunction !=3D NULL) { + mTimerNotifyFunction (mTimerPeriod); + } + + RiscVDisableTimerInterrupt (); // Disable SMode timer int + RiscVClearPendingTimerInterrupt (); + if (mTimerPeriod =3D=3D 0) { + gBS->RestoreTPL (OriginalTPL); + RiscVDisableTimerInterrupt (); // Disable SMode timer int + return; + } + + RiscvTimer =3D RiscVReadTimer (); + SbiSetTimer (RiscvTimer +=3D mTimerPeriod); + gBS->RestoreTPL (OriginalTPL); + RiscVEnableTimerInterrupt (); // enable SMode timer int +} + +/** + + This function registers the handler NotifyFunction so it is called every= time + the timer interrupt fires. It also passes the amount of time since the = last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS= is + returned. If the CPU does not support registering a timer interrupt han= dler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a h= andler + when a handler is already registered, then EFI_ALREADY_STARTED is return= ed. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ER= ROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fire= s. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so i= t can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support time= r interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a = handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a hand= ler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be reg= istered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", Notify= Function)); + mTimerNotifyFunction =3D NotifyFunction; + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 RiscvTimer; + + DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod)); + + if (TimerPeriod =3D=3D 0) { + mTimerPeriod =3D 0; + RiscVDisableTimerInterrupt (); // Disable SMode timer int + return EFI_SUCCESS; + } + + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us + RiscvTimer =3D RiscVReadTimer (); + SbiSetTimer (RiscvTimer + mTimerPeriod); + + mCpu->EnableInterrupt (mCpu); + RiscVEnableTimerInterrupt (); // enable SMode timer int + return EFI_SUCCESS; +} + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + *TimerPeriod =3D mTimerPeriod; + return EFI_SUCCESS; +} + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize the pointer to our notify function. + // + mTimerNotifyFunction =3D NULL; + + // + // Make sure the Timer Architectural Protocol is not already installed i= n the system + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid); + + // + // Find the CPU architectural protocol. + // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= )&mCpu); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be disabled + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, 0); + ASSERT_EFI_ERROR (Status); + + // + // Install interrupt handler for RISC-V Timer. + // + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be enabled at its default period + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATI= ON); + ASSERT_EFI_ERROR (Status); + + // + // Install the Timer Architectural Protocol onto a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mTimerHandle, + &gEfiTimerArchProtocolGuid, + &mTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimer.uni b/UefiCpuPkg/CpuTimerDxe/C= puTimer.uni new file mode 100644 index 000000000000..76de1f3f352a --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/CpuTimer.uni @@ -0,0 +1,14 @@ +// /** @file +// +// Timer Arch protocol strings. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Timer driver that= provides Timer Arch protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "Timer driver that= provides Timer Arch protocol." diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni b/UefiCpuPkg/CpuTimer= Dxe/CpuTimerExtra.uni new file mode 100644 index 000000000000..ceb93a7ce82f --- /dev/null +++ b/UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// Timer Localized Strings and Content +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Timer DXE Driver" --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95746): https://edk2.groups.io/g/devel/message/95746 Mute This Topic: https://groups.io/mt/94664334/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95747+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95747+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136586; cv=none; d=zohomail.com; s=zohoarc; b=O2RfNl6xSSEYRrT5JtXPIgL/9ePe79lxP3V0x4NlfcKr5rCO/2eEAnf92Hh/HKFrS3CTth9dScZq0xN40eG/17/C31OG/mIqGqxwt+oSwsICrBbQFWK0ri1LWK33TQSOgUDD96mAhijr4jLEjUBq+fa1Bs1d0QZ+Sd6CZsuRCLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136586; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=aDe0gGer1fnbf+/HNNAH9l6KpEjLa0uQBmhAspAeO2c=; b=BgcC4OIDzwmDT5ImY7N1xEoIHqDZxkFHC+lztf5xoCiuDhIsLpHjpK9U1xOZkGdE3amWnAQzzZprxWvdK3M+U6Ljy5WmIl0Ou/zW1lSQsglw0MeEiP+pJRM/sbTvbUdjO0zy6LQeF0lDNT4HyPU6vZSkXSaylqR5LCK5CG/rnfg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95747+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136586866373.0500229607236; Sun, 30 Oct 2022 06:29:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rs5gYY1788612xQS2CLMq7Dl; Sun, 30 Oct 2022 06:29:46 -0700 X-Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) by mx.groups.io with SMTP id smtpd.web09.8124.1667136585985169159 for ; Sun, 30 Oct 2022 06:29:46 -0700 X-Received: by mail-pl1-f175.google.com with SMTP id y4so8676851plb.2 for ; Sun, 30 Oct 2022 06:29:45 -0700 (PDT) X-Gm-Message-State: oH1ZAumk5cDhiDtlYhFf3IRHx1787277AA= X-Google-Smtp-Source: AMsMyM48VZ5if1eXG3x979dS1aFiYnK4e0wYOWBxDBE3rlakBcr3nDo2Vuv5BLQfty9wR8+aN5zZ9Q== X-Received: by 2002:a17:90b:4c12:b0:213:d3e3:ba4c with SMTP id na18-20020a17090b4c1200b00213d3e3ba4cmr2286833pjb.22.1667136585298; Sun, 30 Oct 2022 06:29:45 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:44 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 21/30] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Date: Sun, 30 Oct 2022 18:58:33 +0530 Message-Id: <20221030132842.54077-22-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136586; bh=t/Ht2/s5opRtJHccgESByoI98w1OxcWDcybg5vV2T44=; h=Cc:Date:From:Reply-To:Subject:To; b=IPwbq0xcVU70i3DfvVMw79PDogCTK1/utIx6pYYKXZMvEAtcppFZ0RDQbLBSklp6U0d owbQIn4gj4x9PM+MTrv4uoRqiGbdRJEcu1rxnalqJCnw080i0oZPc1SVzdRZGULPMTVSV NlNsPB3+6gkjM+OLZyPHTrWq1OOaj8QBhW8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136588154100009 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 This module is required by other architectures like RISC-V. Hence, move this to OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L --- ArmVirtPkg/ArmVirtPkg.dec | 9 = --------- OvmfPkg/OvmfPkg.dec | 7 = +++++++ {ArmVirtPkg =3D> OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf | = 3 +-- {ArmVirtPkg =3D> OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c | 0 4 files changed, 8 insertions(+), 11 deletions(-) diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec index 89d21ec3a364..4645c91a8375 100644 --- a/ArmVirtPkg/ArmVirtPkg.dec +++ b/ArmVirtPkg/ArmVirtPkg.dec @@ -34,8 +34,6 @@ [Guids.common] gEarly16550UartBaseAddressGuid =3D { 0xea67ca3e, 0x1f54, 0x436b, { 0x9= 7, 0x88, 0xd4, 0xeb, 0x29, 0xc3, 0x42, 0x67 } } gArmVirtSystemMemorySizeGuid =3D { 0x504eccb9, 0x1bf0, 0x4420, { 0x8= 6, 0x5d, 0xdc, 0x66, 0x06, 0xd4, 0x13, 0xbf } } =20 - gArmVirtVariableGuid =3D { 0x50bea1e5, 0xa2c5, 0x46e9, { 0x9b, 0x3a, 0= x59, 0x59, 0x65, 0x16, 0xb0, 0x0a } } - [PcdsFeatureFlag] # # Feature Flag PCD that defines whether TPM2 support is enabled @@ -69,10 +67,3 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # Cloud Hypervisor has no other way to pass Rsdp address to the guest ex= cept use a PCD. # gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x000000= 05 - -[PcdsDynamic] - # - # Whether to force disable ACPI, regardless of the fw_cfg settings - # exposed by QEMU - # - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x00000003 diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 5f5556c67c6c..7df05770b5d6 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -151,6 +151,7 @@ [Guids] gConfidentialComputingSevSnpBlobGuid =3D {0x067b1f5f, 0xcf26, 0x44c5, {= 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}} gUefiOvmfPkgPlatformInfoGuid =3D {0xdec9b486, 0x1f16, 0x47c7, {= 0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}} gVMMBootOrderGuid =3D {0x668f4529, 0x63d0, 0x4bb5, {= 0xb6, 0x5d, 0x6f, 0xbb, 0x9d, 0x36, 0xa4, 0x4a}} + gOvmfVariableGuid =3D {0x50bea1e5, 0xa2c5, 0x46e9, {= 0x9b, 0x3a, 0x59, 0x59, 0x65, 0x16, 0xb0, 0x0a}} =20 [Ppis] # PPI whose presence in the PPI database signals that the TPM base addre= ss @@ -460,6 +461,12 @@ [PcdsDynamic, PcdsDynamicEx] ## This PCD records LASA field in CC EVENTLOG ACPI table. gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLasa|0|UINT64|0x67 =20 + # + # Whether to force disable ACPI, regardless of the fw_cfg settings + # exposed by QEMU + # + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69 + [PcdsFeatureFlag] gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf b/Ovm= fPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf similarity index 89% rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf index e900aa992661..85873f73b2eb 100644 --- a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf +++ b/OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf @@ -19,7 +19,6 @@ [Sources] PlatformHasAcpiDtDxe.c =20 [Packages] - ArmVirtPkg/ArmVirtPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -38,7 +37,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] gEfiVariableArchProtocolGuid diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c b/OvmfP= kg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c similarity index 100% rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95747): https://edk2.groups.io/g/devel/message/95747 Mute This Topic: https://groups.io/mt/94664335/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95748+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95748+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136589; cv=none; d=zohomail.com; s=zohoarc; b=n29I9JhPhmtYkw+yCFtfErxLA1b7O4U27ev6anTnpfg78C6L4/txSjJjGi4BmFb75NWskKTTCKvKYAp6MdyDVb26PlN/YLTnUPcvpvAe2yqQeQLkb/g42Vuic7/C+3vwNN6AZjQFZrvcyQMN1/O5t1FXg8Q/KBOHbDvZUOI6NIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136589; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cC5Tn9LQJvfCUdVvgzbb/2EeyGBXm4xqfTPfV2Zzi5A=; b=kFnfYk1YCPJRsiiv4Lb8Ffb7uNSrNO3grl957oNTx9a1TMP3+6+kkx6D1ktIQh1S//lwhaBrdgwM1WZcbttGOu5UQniTrVwVtMQWGNLY0ZOWIbTHMCDWAyaTf9Vhsmz2zQtAsKrPUse3Haa6RZa4bFJLZVJdTYfFtOEa2YOFxRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95748+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136589353246.0168989422839; Sun, 30 Oct 2022 06:29:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gI6tYY1788612xcjmJEJblp7; Sun, 30 Oct 2022 06:29:49 -0700 X-Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) by mx.groups.io with SMTP id smtpd.web10.8244.1667136588307939990 for ; Sun, 30 Oct 2022 06:29:48 -0700 X-Received: by mail-pj1-f45.google.com with SMTP id 3-20020a17090a0f8300b00212d5cd4e5eso13751424pjz.4 for ; Sun, 30 Oct 2022 06:29:48 -0700 (PDT) X-Gm-Message-State: 1Vfl56zPBMVosRmSkdkOwlgyx1787277AA= X-Google-Smtp-Source: AMsMyM4YSGKM3Kh/xr2IeCsHGR7yrLhe5Q8LpUWjhP0YXeDs1WMF/p3sj78oX+R196Q8uSB7lt+9lw== X-Received: by 2002:a17:90b:2643:b0:205:bd0d:bdff with SMTP id pa3-20020a17090b264300b00205bd0dbdffmr9335891pjb.99.1667136587549; Sun, 30 Oct 2022 06:29:47 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:47 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 22/30] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe Date: Sun, 30 Oct 2022 18:58:34 +0530 Message-Id: <20221030132842.54077-23-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136589; bh=knIUTaNkEyb8rZ4cDFEHQ9OQM8iWBSI5oto383UMCgE=; h=Cc:Date:From:Reply-To:Subject:To; b=DkLIjxhhz3PcirytGvunJEFmAOo4AD7r5tj+JiEfhqOzRDFQCpRqqN7UbeO9vvNbZgi US7eB08RkFb8sipNDr+7+iikOsUj1vlUkhjegZGeZtZzC5OuEv/d/PkybzAFUNm2CngAj TU2qk5qN//Hw4Fb7TNdLyfNy/GaahrxDSoc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136590164100014 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 PlatformHasAcpiDtDxe is required by other architectures also. Hence, it is moved to OvmfPkg. So, update the consumers of this module with the new location. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Signed-off-by: Sunil V L --- ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 4 ++-- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf | 2 +- ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 2 +- ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc index 7ca7a391d9cf..c975e139a216 100644 --- a/ArmVirtPkg/ArmVirtCloudHv.dsc +++ b/ArmVirtPkg/ArmVirtCloudHv.dsc @@ -198,7 +198,7 @@ [PcdsDynamicDefault.common] gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 =20 [PcdsDynamicHii] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGui= d|0x0|FALSE|NV,BS + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS =20 ##########################################################################= ###### # diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index f77443229e8e..2ed1e15a08ca 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -300,7 +300,7 @@ [PcdsPatchableInModule] !endif =20 [PcdsDynamicHii] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGui= d|0x0|FALSE|NV,BS + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGu= id|0x0|FALSE|NV,BS =20 !if $(TPM2_CONFIG_ENABLE) =3D=3D TRUE gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS @@ -569,7 +569,7 @@ [Components.common] # # ACPI Support # - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf [Components.AARCH64] MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index f5db3ac432f3..d6f4ac5166d7 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -457,7 +457,7 @@ [Components.common] # # ACPI Support # - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf [Components.AARCH64] MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf { diff --git a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf= b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf index 4af06b2a6746..7cad40e11f33 100644 --- a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf +++ b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf @@ -36,7 +36,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] gEfiVariableArchProtocolGuid diff --git a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf b/ArmVirt= Pkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf index 1cf25780f830..5888fcdc0b26 100644 --- a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf +++ b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf @@ -37,7 +37,7 @@ [Guids] gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdForceNoAcpi + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi =20 [Depex] TRUE diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuF= vMain.fdf.inc index e06ca7424476..8a063bac04ac 100644 --- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc +++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc @@ -141,7 +141,7 @@ [FV.FvMain] # # ACPI Support # - INF ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf !if $(ARCH) =3D=3D AARCH64 INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95748): https://edk2.groups.io/g/devel/message/95748 Mute This Topic: https://groups.io/mt/94664337/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95749+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95749+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136591; cv=none; d=zohomail.com; s=zohoarc; b=DGLh6C7sWYGkL59faX7944unkTTalFV0EGFTPb15ggR/rW+X6k4MKV3gUbZxbsZp13ElhyBsFdBPn+VZ/uwKhKXfgu0/HG5mEv3YeLo0fNfW6W9v27ZQqtg8mdoRO/t0zewwsvYSk0t34ix0hGJVB6JtKy1iZkVVybDdTWmaZUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136591; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=C4xpPVc8U6IySVUDQVI0ljvNHnXvUcQN7R3McJm8pLk=; b=CulUEbBw3RBw3Md0pr+C8ssv8UutfKB4qvcDOaSnfOwCDlCERCjXMAoJc8MZvx+Y92ONfYodFiU+gg5scSqLuaOde0vKxEyyUdMjC9uLmopAt5fRlrwA3uEnvA6f4yo0sXYkIePcahBe2yS8wo8pC3FQvrEjFG4GxN9Eh8XGBOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95749+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136591955469.4066002989066; Sun, 30 Oct 2022 06:29:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7UENYY1788612xW3YDdRpzYO; Sun, 30 Oct 2022 06:29:51 -0700 X-Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mx.groups.io with SMTP id smtpd.web09.8125.1667136591060786087 for ; Sun, 30 Oct 2022 06:29:51 -0700 X-Received: by mail-pj1-f44.google.com with SMTP id u8-20020a17090a5e4800b002106dcdd4a0so13779241pji.1 for ; Sun, 30 Oct 2022 06:29:51 -0700 (PDT) X-Gm-Message-State: JprFzdefmHWwOVlgEOAlc3hyx1787277AA= X-Google-Smtp-Source: AMsMyM6OG2nyE0P4GuAhQ+Q60Bl3sNoJXOa2lnpxcqGa65qktjkMb3QFDrYi9xkTFkKEj+wgsfuHDA== X-Received: by 2002:a17:902:d492:b0:186:970f:57dd with SMTP id c18-20020a170902d49200b00186970f57ddmr9344975plg.86.1667136590322; Sun, 30 Oct 2022 06:29:50 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:49 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann , Jiewen Yao , Jordan Justen Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 23/30] ArmVirtPkg/PlatformBootManagerLib: Move to OvmfPkg Date: Sun, 30 Oct 2022 18:58:35 +0530 Message-Id: <20221030132842.54077-24-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136591; bh=+eNCAj5o6GqhlF68BQleoUBaLezJSrb8pL9WsDkAXig=; h=Cc:Date:From:Reply-To:Subject:To; b=oHEp3CoPDd8f78zGIjnfEeOcUv48+zGojEj12bkKSiTKvF7x+XCJJZ5sIWQK00o/KmP CBTSRrwQ8IpkNElzbjyKX97JnmdRrBhUGRn8R9nEeFJKCfzlN+FsBBPdIMeq5ad/IO6n6 6zBkQ4H+ysmonJIGB0KtGFpUMoiDBJ5xL/g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136592164100017 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 PlatformBootManagerLib in ArmVirtPkg is required for RISC-V also. So, move it to OvmfPkg. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Cc: Jiewen Yao Cc: Jordan Justen Signed-off-by: Sunil V L --- OvmfPkg/OvmfPkg.dec = | 7 +++++++ {ArmVirtPkg/Library/PlatformBootManagerLib =3D> OvmfPkg/Library/PlatformBo= otManagerLibVirt}/PlatformBootManagerLib.inf | 3 +-- {ArmVirtPkg/Library/PlatformBootManagerLib =3D> OvmfPkg/Library/PlatformBo= otManagerLibVirt}/PlatformBm.h | 0 {ArmVirtPkg/Library/PlatformBootManagerLib =3D> OvmfPkg/Library/PlatformBo= otManagerLibVirt}/PlatformBm.c | 0 {ArmVirtPkg/Library/PlatformBootManagerLib =3D> OvmfPkg/Library/PlatformBo= otManagerLibVirt}/QemuKernel.c | 0 OvmfPkg/OvmfPkg.ci.yaml = | 1 + 6 files changed, 9 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 7df05770b5d6..ba5194114c5c 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -467,6 +467,13 @@ [PcdsDynamic, PcdsDynamicEx] # gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69 =20 + # + # Binary representation of the GUID that determines the terminal type. T= he + # size must be exactly 16 bytes. The default value corresponds to + # EFI_VT_100_GUID. + # + gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, = 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4= D}|VOID*|0x70 + [PcdsFeatureFlag] gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerL= ib.inf b/OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.= inf similarity index 92% rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLi= b.inf rename to OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib= .inf index 997eb1a4429f..a747ea3feac0 100644 --- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf +++ b/OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.inf @@ -29,7 +29,6 @@ [Sources] QemuKernel.c =20 [Packages] - ArmVirtPkg/ArmVirtPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec @@ -61,7 +60,7 @@ [FixedPcd] gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits =20 [Pcd] - gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer + gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut =20 [Guids] diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h b/OvmfP= kg/Library/PlatformBootManagerLibVirt/PlatformBm.h similarity index 100% rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h rename to OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBm.h diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c b/OvmfP= kg/Library/PlatformBootManagerLibVirt/PlatformBm.c similarity index 100% rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c rename to OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBm.c diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c b/OvmfP= kg/Library/PlatformBootManagerLibVirt/QemuKernel.c similarity index 100% rename from ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c rename to OvmfPkg/Library/PlatformBootManagerLibVirt/QemuKernel.c diff --git a/OvmfPkg/OvmfPkg.ci.yaml b/OvmfPkg/OvmfPkg.ci.yaml index ff022242b018..c6efb9a8e59e 100644 --- a/OvmfPkg/OvmfPkg.ci.yaml +++ b/OvmfPkg/OvmfPkg.ci.yaml @@ -22,6 +22,7 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ + "Library/PlatformBootManagerLibVirt/PlatformBm.c" ], "skip": True }, --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95749): https://edk2.groups.io/g/devel/message/95749 Mute This Topic: https://groups.io/mt/94664338/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95750+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95750+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136594; cv=none; d=zohomail.com; s=zohoarc; b=UdOxTGWmTu/AOz+S9odt1dOVAtulDqmoeYU8DKKcCLo3WZ1ox7v8IYzx/Gg0Gvi+oYbsTlvn+WAcNmE+fXtxHCqs4Tx/DLpFDRV8aml5F97PKw9Wpfk3pYzqetlQoPxLd8h9+/X7QUtU1C1RdOie74xBmMD+ZUpnylq9O4ebTmw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136594; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NU+zXQtn+7nEzi4KVggxcmGCSSdUZoaKAc2g/dB95f0=; b=BNOa4xDFYs/jV6wP8R30z462QnS9LH6cXq6EqrYBLM4JsuzVvTrkSWPZsmA+wnruaXni0BB0BYaIxmAROCHJTG2W+yTVIjpssrOC0amN/iwvTd6NqlGX0EuPYwsKx/h7y/woFYKk+NllpaMhAmCnz4l65zk4BLyW2ZxcVeSEwxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95750+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136594417905.8644988290453; Sun, 30 Oct 2022 06:29:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Rk0OYY1788612xNBMM7YLQMN; Sun, 30 Oct 2022 06:29:54 -0700 X-Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) by mx.groups.io with SMTP id smtpd.web12.8286.1667136593450900454 for ; Sun, 30 Oct 2022 06:29:53 -0700 X-Received: by mail-pl1-f180.google.com with SMTP id c24so8650417pls.9 for ; Sun, 30 Oct 2022 06:29:53 -0700 (PDT) X-Gm-Message-State: XrVSXq46xbtQHxVWTM9bIRAPx1787277AA= X-Google-Smtp-Source: AMsMyM5cVBW7DFeP/I0DoM7wERq2IS+FYK8LsJQsJ5y8vS1GP2uFOd8M52PCPEhOXdLG41iZVEcPkA== X-Received: by 2002:a17:902:ebc7:b0:17e:7378:1da8 with SMTP id p7-20020a170902ebc700b0017e73781da8mr9295056plg.152.1667136592738; Sun, 30 Oct 2022 06:29:52 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:52 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 24/30] ArmVirtPkg: Fix up the paths to PlatformBootManagerLib Date: Sun, 30 Oct 2022 18:58:36 +0530 Message-Id: <20221030132842.54077-25-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136594; bh=tHO32G7MIlWK0a7fLuasvsJmiHUhuyYChJkKW5QebcQ=; h=Cc:Date:From:Reply-To:Subject:To; b=sskSDBDPz63NOVKgUtold1rMg8qKhuYebquY0DtY0lgdTnHgKV6yi0EXWbSayNok2dI zElro5T1ZPgCmIN/FlEkKPri1T2rBl1aYHCxLDbGmx6cTd5cgkY3vy2kypyapgGcRUqCS axt+cMkJjEof7ssg3lJf829kq/3AtIgXg5w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136596174100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 PlatformBootManagerLib has been moved to OvmfPkg so that other CPU architectures can reuse. So, update existing paths with the new location. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Signed-off-by: Sunil V L --- ArmVirtPkg/ArmVirtQemu.dsc | 4 ++-- ArmVirtPkg/ArmVirtQemuKernel.dsc | 4 ++-- ArmVirtPkg/ArmVirtPkg.ci.yaml | 1 - 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 2ed1e15a08ca..1d8b6dc9c04c 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -69,7 +69,7 @@ [LibraryClasses.common] =20 CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/Platfor= mBootManagerLib.inf + PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibVirt/Platfo= rmBootManagerLib.inf PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf @@ -173,7 +173,7 @@ [PcdsFixedAtBuild.common] !if $(TTY_TERMINAL) =3D=3D TRUE gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 # Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID - gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d= , 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94} + gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, = 0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x9= 4} !else gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1 !endif diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index d6f4ac5166d7..91119c2df9c4 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -69,7 +69,7 @@ [LibraryClasses.common] =20 CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/Platfor= mBootManagerLib.inf + PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibVirt/Platfo= rmBootManagerLib.inf PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf @@ -146,7 +146,7 @@ [PcdsFixedAtBuild.common] !if $(TTY_TERMINAL) =3D=3D TRUE gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 # Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID - gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d= , 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94} + gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, = 0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x9= 4} !else gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1 !endif diff --git a/ArmVirtPkg/ArmVirtPkg.ci.yaml b/ArmVirtPkg/ArmVirtPkg.ci.yaml index 1e799dc4e194..552511c2694e 100644 --- a/ArmVirtPkg/ArmVirtPkg.ci.yaml +++ b/ArmVirtPkg/ArmVirtPkg.ci.yaml @@ -24,7 +24,6 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ - "Library/PlatformBootManagerLib/PlatformBm.c" ] }, ## options defined .pytool/Plugin/CompilerPlugin --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95750): https://edk2.groups.io/g/devel/message/95750 Mute This Topic: https://groups.io/mt/94664339/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95751+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95751+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136597; cv=none; d=zohomail.com; s=zohoarc; b=NPNPwXTftffE3PZ+HzhfQORT0nlW3RBrvg2LW0HP7IlNs3lbPg37oJM5J7XcyjrxzxRIXuGnNcMnB92RSdQRCe+1/377hag0TDqzJLg4elRbbMr+YXU5lsog+xVaMbBpQyhW/VI26XMOr7oG1jxlQJa1iXdrxNMpqhaWsH+3qCk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136597; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5DIcJN+Qd4M2Sa8xeYMfxTEqrDQZJrLBZJ68uNNGY/k=; b=W/cUuwfX38+/U/kck3yIyKGuDCyCI30AtO5g/8Co4d7znVCweFb/n/Ew3z+oRe6dMoBd/riF0tB6O+9PXAF9DFhxy1d7GmYjeMj+qxrv6/gubfaBzX6EE0QWvjavu737JSrxCpHwIT0PIkY0LKY7p2b24ISYrkvn3IEVyv2Lkm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95751+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136597610422.7537411234699; Sun, 30 Oct 2022 06:29:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AiG6YY1788612xRQPrLAyQLb; Sun, 30 Oct 2022 06:29:57 -0700 X-Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) by mx.groups.io with SMTP id smtpd.web09.8126.1667136596823235723 for ; Sun, 30 Oct 2022 06:29:56 -0700 X-Received: by mail-pg1-f172.google.com with SMTP id 128so8654018pga.1 for ; Sun, 30 Oct 2022 06:29:56 -0700 (PDT) X-Gm-Message-State: 9TnNucAWitnAnvsRjXDhTXeBx1787277AA= X-Google-Smtp-Source: AMsMyM4G432e2psH2mbALQCfz/TFOEEfVdGrRznVJfwb/L5Nht6daJ0a2eAy/L8O1yGdkRRlbmiSTg== X-Received: by 2002:a63:105e:0:b0:46e:9bac:1c3 with SMTP id 30-20020a63105e000000b0046e9bac01c3mr7940125pgq.388.1667136596136; Sun, 30 Oct 2022 06:29:56 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:55 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Abner Chang , Daniel Schaefer , Jian J Wang , Liming Gao , Andrew Fish , Michael D Kinney , Ard Biesheuvel Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 25/30] EmbeddedPkg/NvVarStoreFormattedLib: Migrate to MdeModulePkg Date: Sun, 30 Oct 2022 18:58:37 +0530 Message-Id: <20221030132842.54077-26-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136597; bh=0lGUXIrR7AOUlHGVdGWwimIcErDR9Ml/NTjAxI+aLT0=; h=Cc:Date:From:Reply-To:Subject:To; b=m97312f3Nkq+hpX2Ay1v8gqLvRJExdh7/9ZD9YO5uIEcPFv8OglPgNOqJzIK70pXLRg LxPqr6YMuBNoSGG06qgpCKaLIE/yDP0GKlFY5POllacAzbfM8RdMVjNE6EVFGKJRvIYkV NogTn4DJrsPfnRLf2rLZ8MOt5sKCWZStDao= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136598193100005 Content-Type: text/plain; charset="utf-8" This library is required by NorFlashDxe. Since it will be used by both virtual and real platforms, migrate this library to MdeModulePkg. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Abner Chang Cc: Daniel Schaefer Cc: Jian J Wang Cc: Liming Gao Cc: Andrew Fish Cc: Michael D Kinney Signed-off-by: Sunil V L Acked-by: Ard Biesheuvel --- EmbeddedPkg/EmbeddedPkg.dec = | 3 --- MdeModulePkg/MdeModulePkg.dec = | 3 +++ MdeModulePkg/MdeModulePkg.dsc = | 2 ++ {EmbeddedPkg =3D> MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreF= ormattedLib.inf | 1 - {EmbeddedPkg =3D> MdeModulePkg}/Include/Guid/NvVarStoreFormatted.h = | 0 {EmbeddedPkg =3D> MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreF= ormattedLib.c | 0 6 files changed, 5 insertions(+), 4 deletions(-) diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index 341ef5e6a679..b1f5654835f6 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -69,9 +69,6 @@ [Guids.common] # HII form set GUID for ConsolePrefDxe driver gConsolePrefFormSetGuid =3D { 0x2d2358b4, 0xe96c, 0x484d, { 0xb2, 0xdd, = 0x7c, 0x2e, 0xdf, 0xc7, 0xd5, 0x6f } } =20 - ## Include/Guid/NvVarStoreFormatted.h - gEdkiiNvVarStoreFormattedGuid =3D { 0xd1a86e3f, 0x0707, 0x4c35, { 0x83, = 0xcd, 0xdc, 0x2c, 0x29, 0xc8, 0x91, 0xa3 } } - [Protocols.common] gHardwareInterruptProtocolGuid =3D { 0x2890B3EA, 0x053D, 0x1643, { 0xAD= , 0x0C, 0xD6, 0x48, 0x08, 0xDA, 0x3F, 0xF1 } } gHardwareInterrupt2ProtocolGuid =3D { 0x32898322, 0x2da1, 0x474a, { 0xba= , 0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94, 0x70 } } diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 58e6ab004882..492bff8b7890 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -412,6 +412,9 @@ [Guids] ## Include/Guid/MigratedFvInfo.h gEdkiiMigratedFvInfoGuid =3D { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4,= 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } } =20 + ## Include/Guid/NvVarStoreFormatted.h + gEdkiiNvVarStoreFormattedGuid =3D { 0xd1a86e3f, 0x0707, 0x4c35, { 0x83, = 0xcd, 0xdc, 0x2c, 0x29, 0xc8, 0x91, 0xa3 } } + # # GUID defined in UniversalPayload # diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc index 659482ab737f..4142e1178dcd 100644 --- a/MdeModulePkg/MdeModulePkg.dsc +++ b/MdeModulePkg/MdeModulePkg.dsc @@ -104,6 +104,7 @@ [LibraryClasses] VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibN= ull.inf VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + NvVarStoreFormattedLib|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVar= StoreFormattedLib.inf =20 [LibraryClasses.EBC.PEIM] IoLib|MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf @@ -443,6 +444,7 @@ [Components] MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.i= nf + MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf =20 [Components.IA32, Components.X64, Components.AARCH64] MdeModulePkg/Universal/EbcDxe/EbcDxe.inf diff --git a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLi= b.inf similarity index 96% rename from EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf rename to MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLi= b.inf index e2eed26c5b2d..5e8cd94cc9e0 100644 --- a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf +++ b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf @@ -32,7 +32,6 @@ [Sources] NvVarStoreFormattedLib.c =20 [Packages] - EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec =20 diff --git a/EmbeddedPkg/Include/Guid/NvVarStoreFormatted.h b/MdeModulePkg/= Include/Guid/NvVarStoreFormatted.h similarity index 100% rename from EmbeddedPkg/Include/Guid/NvVarStoreFormatted.h rename to MdeModulePkg/Include/Guid/NvVarStoreFormatted.h diff --git a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.c b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c similarity index 100% rename from EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.c rename to MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLi= b.c --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95751): https://edk2.groups.io/g/devel/message/95751 Mute This Topic: https://groups.io/mt/94664340/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95752+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95752+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136599; cv=none; d=zohomail.com; s=zohoarc; b=YlkdzF0yoFmBoRGp2unLjRhgaNAsVTwWFXsWcvtlcRK4EU/RdaxaNdU2ZzivsOkCgtbFo8PWRgOoF5zLf7D4ZHE72BIw8DUwxKn5gRiCRb7ICohc9x0wsNL4hRnlpJ8227VxoeZFVq51zmuy241PtIBMV+fcMJKHGCKt2xDiODM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136599; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qNLqU/z13uzk73Qt0wvduRua8E4lXQU+wFUaazTdAG4=; b=PPOGcHRh9R/tBnUmQ8ycMqnKOhOaXc0zNn8i/Aqi57dj0XhT2FME7QIHdjr6NF6EtPhqLN/pc50KrU/ezIrMJ2wNQ5zYlo1bxeUlmgfz+pTQc9y1R0Di4DgCgYDDSR0x+drL5NQFwBSrCLowTdqKRxJTADlqMEqWYipwYiVx3C8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95752+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136599914587.0983676392418; Sun, 30 Oct 2022 06:29:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Pe1vYY1788612xVkKLr5jiR1; Sun, 30 Oct 2022 06:29:59 -0700 X-Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) by mx.groups.io with SMTP id smtpd.web12.8288.1667136599019536418 for ; Sun, 30 Oct 2022 06:29:59 -0700 X-Received: by mail-pg1-f180.google.com with SMTP id h185so8619992pgc.10 for ; Sun, 30 Oct 2022 06:29:58 -0700 (PDT) X-Gm-Message-State: dPdU2VoXFwL2x9vykzGuL2ckx1787277AA= X-Google-Smtp-Source: AMsMyM66/dkGNxzsKPNbvU6uOmUpUWTCJGnf7QvaUtcKTy6gmrfzK3hlxcn/j1Wp1GL1y0Le2jJQfw== X-Received: by 2002:a63:87c7:0:b0:434:883:ea21 with SMTP id i190-20020a6387c7000000b004340883ea21mr8495414pge.152.1667136598397; Sun, 30 Oct 2022 06:29:58 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:58 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 26/30] ArmVirtPkg: Update the references to NvVarStoreFormattedLib Date: Sun, 30 Oct 2022 18:58:38 +0530 Message-Id: <20221030132842.54077-27-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136599; bh=g42Ia+qWeCuRGCQQL8J6wA5OTThQDXbX8aeIzDt/AEY=; h=Cc:Date:From:Reply-To:Subject:To; b=pKXeAHzt/y5QuZKUaDFRsCLvSagcLU7aPQl2zFWmf3w+18b36XWtB9lC9ME83XM1loM YqwlloEFXdL1zkbzPxB9x4zjWjI7hvnayaWbkQ8TwWNjeFo+QaR9l7NC51r0PKjpe87jV egvzz9e7C2MZw3sJktf8vreDridOxupdv2k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136600176100007 Content-Type: text/plain; charset="utf-8" The NvVarStoreFormattedLib library is moved to MdeModulePkg. So, updates its users with the new location. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann Signed-off-by: Sunil V L --- ArmVirtPkg/ArmVirtKvmTool.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 2 +- ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc index c598903b33d2..a9f8b9ec6946 100644 --- a/ArmVirtPkg/ArmVirtKvmTool.dsc +++ b/ArmVirtPkg/ArmVirtKvmTool.dsc @@ -258,7 +258,7 @@ [Components.common] MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } =20 diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 1d8b6dc9c04c..cd21fcb760a5 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -383,7 +383,7 @@ [Components.common] MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index 91119c2df9c4..c9c12827ca88 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -294,7 +294,7 @@ [Components.common] MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormatted= Lib.inf # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95752): https://edk2.groups.io/g/devel/message/95752 Mute This Topic: https://groups.io/mt/94664342/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95753+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95753+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136603; cv=none; d=zohomail.com; s=zohoarc; b=Kpz70rVN8VP0lkktrYw3J+fsG+yanUQ8BYBIEs11oTFjNetL73SnObL44sQ89exfwgEtqc/P5ZuhHXbvu8Z3Ry6ldHqBlV27/mJvk0J3PgCBK5ICkbcakxuTYTlH1udgDr91ziK3LgTg9T5fomXvy5Tyl2moVc2oImpZBfKAf2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136603; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=c2cNMjE9a40pnWnz2cQ90kY2zaSKC98Og7rExooEQIw=; b=eldpay5vHzzZODyVRMsOMtJha9/J1synTyFEQw/k6Y96I0md5j5ylUljvxfNdYO+Rp3IgJA2ZEFUvrLBVVPLT1LiP297w4NFaB8OuZr9DlR0c9FfFXyQYd/v0pNudRGiOtatc2zE2RYVIP9ZF/hLB5tKQhTvR86ej+9rMKZ52Fk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95753+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136603553529.4541325550202; Sun, 30 Oct 2022 06:30:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id suPPYY1788612xHKmxjKIwnj; Sun, 30 Oct 2022 06:30:03 -0700 X-Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mx.groups.io with SMTP id smtpd.web11.8335.1667136601943906464 for ; Sun, 30 Oct 2022 06:30:02 -0700 X-Received: by mail-pj1-f41.google.com with SMTP id q1-20020a17090a750100b002139ec1e999so3863783pjk.1 for ; Sun, 30 Oct 2022 06:30:01 -0700 (PDT) X-Gm-Message-State: 7UBSYkbwv3w6JA5cp4BBPz8Lx1787277AA= X-Google-Smtp-Source: AMsMyM4VFvZh2kFOtO5CRiN33kIgorKiPs7oKTguCb8Vx1r5VFy74v2FCrXFhXK/bLs/cn/2AO8SNw== X-Received: by 2002:a17:90a:5781:b0:20a:9962:bb4a with SMTP id g1-20020a17090a578100b0020a9962bb4amr26119422pji.185.1667136601190; Sun, 30 Oct 2022 06:30:01 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:30:00 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 27/30] OvmfPkg: Add VirtNorFlashPlatformLib library Date: Sun, 30 Oct 2022 18:58:39 +0530 Message-Id: <20221030132842.54077-28-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136603; bh=ZFW+uzWjEuZcgQvoIveOSdylGsTW9lyfvyn/kX4T77Y=; h=Cc:Date:From:Reply-To:Subject:To; b=WWqrQaVxrn++gLRBXxX54VvsRTXnjjNDlX1Z3IO3vF1xLuVYBcVfj95PA2/a5FJNLfg HIOpTZrlY+aoJJRhoiHjgXLTstZ/uBA0QiQfhPhc+tL59jbSuHF2LREMpXqgu8ituGAXD Mq0f8YjaI+O9obVIpqD0HcmkqQVPz+O5avM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136604232100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add the VirtNorFlashPlatformLib library for qemu virt machines. Add two instances of the library. One which uses DT information and the other which is static. They are copied from ArmVirtPkg and SbsaQemu. Two PCD variables used by the library are added in the OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Daniel Schaefer Signed-off-by: Sunil V L --- OvmfPkg/OvmfPkg.dec | = 4 + OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf | 4= 0 ++++++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf | 3= 0 +++++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c | 13= 6 ++++++++++++++++++++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 4= 0 ++++++ 5 files changed, 250 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index ba5194114c5c..142c34193d60 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -409,6 +409,10 @@ [PcdsFixedAtBuild] # check to decide whether to abort dispatch of the driver it is linked = into. gUefiOvmfPkgTokenSpaceGuid.PcdEntryPointOverrideFwCfgVarName|""|VOID*|0x= 68 =20 + ## The base address and size of the FVMAIN + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress|0|UINT64|0x71 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize|0|UINT32|0x72 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTree= Lib.inf b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib= .inf new file mode 100644 index 000000000000..5b7a45d15782 --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf @@ -0,0 +1,40 @@ +#/** @file +# +# Component description file for VirtNorFlashDeviceTreeLib module +# +# Copyright (c) 2014, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VirtNorFlashDeviceTreeLib + FILE_GUID =3D 42C30D8E-BFAD-4E77-9041-E7DAAE88DF7A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VirtNorFlashPlatformLib + +[Sources.common] + VirtNorFlashDeviceTreeLib.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + +[Protocols] + gFdtClientProtocolGuid ## CONSUMES + +[Depex] + gFdtClientProtocolGuid + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.= inf b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf new file mode 100644 index 000000000000..4e87bd437380 --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf @@ -0,0 +1,30 @@ +#/** @file +# +# Component description file for VirtNorFlashStaticLib module +# +# Copyright (c) 2014, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VirtNorFlashStaticLib + FILE_GUID =3D 064742F1-E531-4D7D-A154-22315889CC23 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VirtNorFlashPlatformLib + +[Sources.common] + VirtNorFlashStaticLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTree= Lib.c b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c new file mode 100644 index 000000000000..08750e66095d --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c @@ -0,0 +1,136 @@ +/** @file + + Copyright (c) 2014-2018, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include +#include + +#include + +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB + +#define MAX_FLASH_BANKS 4 + +EFI_STATUS +VirtNorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevices[MAX_FLASH_BANKS]; + +EFI_STATUS +VirtNorFlashPlatformGetDevices ( + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + FDT_CLIENT_PROTOCOL *FdtClient; + INT32 Node; + EFI_STATUS Status; + EFI_STATUS FindNodeStatus; + CONST UINT32 *Reg; + UINT32 PropSize; + UINT32 Num; + UINT64 Base; + UINT64 Size; + + Status =3D gBS->LocateProtocol ( + &gFdtClientProtocolGuid, + NULL, + (VOID **)&FdtClient + ); + ASSERT_EFI_ERROR (Status); + + Num =3D 0; + for (FindNodeStatus =3D FdtClient->FindCompatibleNode ( + FdtClient, + "cfi-flash", + &Node + ); + !EFI_ERROR (FindNodeStatus) && Num < MAX_FLASH_BANKS; + FindNodeStatus =3D FdtClient->FindNextCompatibleNode ( + FdtClient, + "cfi-flash", + Node, + &Node + )) + { + Status =3D FdtClient->GetNodeProperty ( + FdtClient, + Node, + "reg", + (CONST VOID **)&Reg, + &PropSize + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: GetNodeProperty () failed (Status =3D=3D %r)\n", + __FUNCTION__, + Status + )); + continue; + } + + ASSERT ((PropSize % (4 * sizeof (UINT32))) =3D=3D 0); + + while (PropSize >=3D (4 * sizeof (UINT32)) && Num < MAX_FLASH_BANKS) { + Base =3D SwapBytes64 (ReadUnaligned64 ((VOID *)&Reg[0])); + Size =3D SwapBytes64 (ReadUnaligned64 ((VOID *)&Reg[2])); + Reg +=3D 4; + + PropSize -=3D 4 * sizeof (UINT32); + + // + // Disregard any flash devices that overlap with the primary FV. + // The firmware is not updatable from inside the guest anyway. + // + if ((PcdGet64 (PcdOvmfFvBaseAddress) + PcdGet32 (PcdOvmfFvSize) > Ba= se) && + ((Base + Size) > PcdGet64 (PcdOvmfFvBaseAddress))) + { + continue; + } + + mNorFlashDevices[Num].DeviceBaseAddress =3D (UINTN)Base; + mNorFlashDevices[Num].RegionBaseAddress =3D (UINTN)Base; + mNorFlashDevices[Num].Size =3D (UINTN)Size; + mNorFlashDevices[Num].BlockSize =3D QEMU_NOR_BLOCK_SIZE; + Num++; + } + + // + // UEFI takes ownership of the NOR flash, and exposes its functionality + // through the UEFI Runtime Services GetVariable, SetVariable, etc. Th= is + // means we need to disable it in the device tree to prevent the OS fr= om + // attaching its device driver as well. + // Note that this also hides other flash banks, but the only other fla= sh + // bank we expect to encounter is the one that carries the UEFI execut= able + // code, which is not intended to be guest updatable, and is usually b= acked + // in a readonly manner by QEMU anyway. + // + Status =3D FdtClient->SetNodeProperty ( + FdtClient, + Node, + "status", + "disabled", + sizeof ("disabled") + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "Failed to set NOR flash status to 'disabled'\n"= )); + } + } + + *NorFlashDescriptions =3D mNorFlashDevices; + *Count =3D Num; + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.= c b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c new file mode 100644 index 000000000000..fdc2ccb6294e --- /dev/null +++ b/OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Linaro Ltd. All rights reserved + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include + +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB + +EFI_STATUS +VirtNorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =3D +{ + FixedPcdGet32 (PcdOvmfFdBaseAddress), + FixedPcdGet64 (PcdFlashNvStorageVariableBase), + FixedPcdGet32 (PcdOvmfFirmwareFdSize), + QEMU_NOR_BLOCK_SIZE +}; + +EFI_STATUS +VirtNorFlashPlatformGetDevices ( + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + *NorFlashDescriptions =3D &mNorFlashDevice; + *Count =3D 1; + return EFI_SUCCESS; +} --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95753): https://edk2.groups.io/g/devel/message/95753 Mute This Topic: https://groups.io/mt/94664345/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95754+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95754+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136605; cv=none; d=zohomail.com; s=zohoarc; b=mk55rPS0WDM7T3R/aVSP2NbgvJNAIEaa20GwjmzjHWJ/ypS/jCNZORFNBqLP9eEf8N2Qp8Ok2OTD+YlyuBUQrriQMoQIfWzN/Njgk/0Sxdopex66HqnLmXEqrHH2AyXy+ampk3783O4rBchMSsXUAN/r0MO/Urcl/NVletUruDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136605; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=agDUE0NEoaHEVKE2m+s2z/563QYuIzKHtyDJfBTmTdc=; b=M5JXH/4rfKCu7qPEbzAKh0LKL4gOhD+gJGy9dRtv1ZOruTQQeFqU3B5OJ6jrQ742Uz0vBt50MRJRi4lDhrYPW5nb3hB8jWVLRqs8Jj/CWst498yMj8sJSu/DniWSEEUPooMGMEKmlMeqUhmN9TXZYgwerGevXiFsq5N75aL3e9M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95754+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136605860108.06448552283268; Sun, 30 Oct 2022 06:30:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KHZJYY1788612x3DXo7zvlVD; Sun, 30 Oct 2022 06:30:05 -0700 X-Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by mx.groups.io with SMTP id smtpd.web12.8284.1667136578828028820 for ; Sun, 30 Oct 2022 06:30:04 -0700 X-Received: by mail-pl1-f172.google.com with SMTP id p21so4792285plr.7 for ; Sun, 30 Oct 2022 06:30:04 -0700 (PDT) X-Gm-Message-State: ZSbC6uFyUmM2F6jPYIIpfuTXx1787277AA= X-Google-Smtp-Source: AMsMyM408HZbEkNFXbyU4VDEVGH/Xia2MjP9n4nhW/dJa7l8M9LoTdcXt5AW5bytY9ibxtNbYRM1xQ== X-Received: by 2002:a17:902:e5c5:b0:186:5f09:8468 with SMTP id u5-20020a170902e5c500b001865f098468mr9460711plf.122.1667136603992; Sun, 30 Oct 2022 06:30:03 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:30:03 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 28/30] OvmfPkg: RiscVVirt: Add Qemu Virt platform support Date: Sun, 30 Oct 2022 18:58:40 +0530 Message-Id: <20221030132842.54077-29-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136605; bh=9Zfcva3Fce8L5enGMHnhrEmdeIMdz13z1tQvsJxmF1I=; h=Cc:Date:From:Reply-To:Subject:To; b=jeXbapMmyoyliyx6eeIu08AQz3zfkMoMDG8LP527EJBO+855XFelXaleHhuchdZAmDo +anUy1V6oQHd52nQbZ0iKuCqX6PitmJKRUPYx4hrZWu0Jdivc4RKLbZuLTlHmfxFF843d Ub/pIQ5t4eLhTEcP3bSIo1s3oQNktcylfSM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136606308100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - EDK2 will boot as S-mode payload of opensbi. - It supports building either code and variables in unified flash or in two separate drives via build time option UNIFIED_NVVARS. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang --- OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc | 727 ++++++++++++++++++++ OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf | 406 +++++++++++ OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf.inc | 66 ++ OvmfPkg/Platforms/RiscVVirt/VarStore.fdf.inc | 79 +++ 4 files changed, 1278 insertions(+) diff --git a/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc b/OvmfPkg/Platforms/= RiscVVirt/RiscVVirt.dsc new file mode 100644 index 000000000000..33c945f57624 --- /dev/null +++ b/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc @@ -0,0 +1,727 @@ +## @file +# RISC-V EFI on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D RiscVVirt + PLATFORM_GUID =3D 39DADB39-1B21-4867-838E-830B6149B9E0 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D OvmfPkg/Platforms/RiscVVirt/RiscVVirt= .fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE UNIFIED_VARSTORE =3D TRUE + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D TRUE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D TRUE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC: *_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf + TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf + RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRea= lTimeClockLib.inf +!if $(UNIFIED_VARSTORE) =3D=3D TRUE + VirtNorFlashPlatformLib|OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorF= lashStaticLib.inf +!else + VirtNorFlashPlatformLib|OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorF= lashDeviceTreeLib.inf +!endif + QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf +!endif + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common] +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + + # PCI Libraries + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf + DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf + QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFw= CfgSimpleParserLib.inf + QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf + + # PCI support + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridge= LibNull.inf + + # Boot Manager +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT= cg2PhysicalPresenceLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= b/PeiDxeTpmPlatformHierarchyLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf +!endif + + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf + + PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibVirt/Platfo= rmBootManagerLib.inf + + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + +[LibraryClasses.common.SEC] +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiC= puExceptionHandlerLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + +[LibraryClasses.common.PEI_CORE] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiC= puExceptionHandlerLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiC= puExceptionHandlerLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + ResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResou= rcePublicationLib.inf + +[LibraryClasses.common.DXE_CORE] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf + PciHostBridgeLib|OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf + PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostB= ridgeUtilityLib.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf + +[LibraryClasses.common.DXE_DRIVER] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + PlatformUpdateProgressLib|MdeModulePkg/Library/PlatformBootManagerLibNul= l/PlatformBootManagerLibNull.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000 + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x02 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + # + # F2 for UI APP + # + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"2.7" + + # Serial Port + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|9600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + +##########################################################################= ###### +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform +# +##########################################################################= ###### + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 + + # Set video resolution for text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + OvmfPkg/Sec/SecMain.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + + # + # PEI Phase modules + # + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompress= Lib.inf + } + + OvmfPkg/PlatformPei/PlatformPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf + } + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompr= essLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + + MdeModulePkg/Universal/Metronome/Metronome.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # RISC-V Platform module + # + UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf + + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf + + # + # RISC-V Core module + # + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + +# Graphic console + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Network Support + # + !include NetworkPkg/Network.dsc.inc + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # PCI support + # + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf + OvmfPkg/Virtio10Dxe/Virtio10.inf + + # + # Video support + # + OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf + OvmfPkg/VirtioGpuDxe/VirtioGpu.inf + OvmfPkg/PlatformDxe/Platform.inf + + # + # Platform Driver + # + OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf + EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf + OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + OvmfPkg/VirtioScsiDxe/VirtioScsi.inf + OvmfPkg/VirtioNetDxe/VirtioNet.inf + OvmfPkg/VirtioRngDxe/VirtioRng.inf + + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf + OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + # + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.in= f { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf { + + NULL|OvmfPkg/Library/BlobVerifierLibNull/BlobVerifierLibNull.inf + } + +# HTTPS(secure) support in GUI for updating ssl keys for PXE boot + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib= .inf + } + +# TFTP support for PXE boot + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpApp.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + + # HTTP support for PXE boot + ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf + } + ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf + } + +# HTTPS (secure) support for PXE boot + NetworkPkg/TlsDxe/TlsDxe.inf { + + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + RngLib|MdePkg/Library/DxeRngLib/DxeRngLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib= .inf + } + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf { + + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib= .inf + NULL|OvmfPkg/Library/TlsAuthConfigLib/TlsAuthConfigLib.inf + } + +[PcdsDynamicDefault.common] + # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this + # PCD and PcdPciDisableBusEnumeration above have not been assigned yet + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF + + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 + +[PcdsFeatureFlag.common] + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE diff --git a/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf b/OvmfPkg/Platforms/= RiscVVirt/RiscVVirt.fdf new file mode 100644 index 000000000000..be227cfd713a --- /dev/null +++ b/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf @@ -0,0 +1,406 @@ +# @file +# Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Platform definitions +# + +!include RiscVVirt.fdf.inc + +##########################################################################= ###### +!if $(UNIFIED_VARSTORE) =3D=3D TRUE +[FD.RISCV_VIRT] +BaseAddress =3D $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdB= aseAddress +Size =3D $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdS= ize +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +$(SECFV_OFFSET)|$(SECFV_SIZE) +FV =3D SECFV + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress|gUefiOvmfPkgTokenSpaceGuid= .PcdOvmfFvSize +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc + +!else +[FD.RISCV_CODE] +BaseAddress =3D $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdB= aseAddress +Size =3D $(CODE_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(CODE_BLOCKS) + +$(SECFV_OFFSET)|$(SECFV_SIZE) +FV =3D SECFV + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress|gUefiOvmfPkgTokenSpaceGuid= .PcdOvmfFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +[FD.RISCV_NVVARS] +BaseAddress =3D $(VARS_BASE_ADDRESS) +Size =3D $(VARS_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(VARS_BLOCK_SIZE) +NumBlocks =3D $(VARS_BLOCKS) + +!include VarStore.fdf.inc +!endif +##########################################################################= ###### + +[FD.RISCV_MEMFD] +BaseAddress =3D $(MEMFD_BASE_ADDRESS) +Size =3D 0x00a00000 +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D 0xa00 + +0x00000000|0x00010000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize + +0x00010000|0x001000 +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize + +0x00040000|0x00080000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfPeiMemFvSize +FV =3D PEIFV + +0x00100000|0x00900000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfDxeMemFvSize +FV =3D DXEFV + +##########################################################################= ################ + +[FV.SECFV] +BlockSize =3D 0x1000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# SEC Phase modules +# +# The code in this FV handles the initial firmware startup, and +# decompresses the PEI and DXE FVs which handles the rest of the boot sequ= ence. +# +INF OvmfPkg/Sec/SecMain.inf + +##########################################################################= ###### +[FV.PEIFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI PEI { + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeR= outerPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.i= nf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +} + +# +# PEI Phase modules +# +INF MdeModulePkg/Core/Pei/PeiMain.inf +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRou= terPei.inf +INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +# RISC-V Platform PEI Driver +INF OvmfPkg/PlatformPei/PlatformPei.inf + +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +} + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf + +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +# +# PCI support +# +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf +INF OvmfPkg/Virtio10Dxe/Virtio10.inf + +# +# Video support +# +INF OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf +INF OvmfPkg/VirtioGpuDxe/VirtioGpu.inf +INF OvmfPkg/PlatformDxe/Platform.inf + +# +# Platform Driver +# +INF OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf +INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf +INF OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf +INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf +INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf +INF OvmfPkg/VirtioNetDxe/VirtioNet.inf +INF OvmfPkg/VirtioRngDxe/VirtioRng.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + +INF MdeModulePkg/Universal/Metronome/Metronome.inf +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +INF OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf +INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + +# RISC-V Platform Drivers +INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf + +# RISC-V Core Drivers +INF UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf +INF UefiCpuPkg/CpuDxe/CpuDxe.inf + +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif + +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + +!ifndef $(SOURCE_DEBUG_ENABLE) +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +!endif + +INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand= .inf +INF ShellPkg/Application/Shell/Shell.inf + +# TFTP support for PXE boot +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpApp.inf + +# HTTP support for PXE boot +INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf +INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.inf + +# +# Network modules +# +!if $(E1000_ENABLE) + FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { + SECTION PE32 =3D Intel3.5/EFIX64/E3507X2.EFI + } +!endif + +!include NetworkPkg/Network.fdf.inc + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +INF MdeModulePkg/Application/UiApp/UiApp.inf +INF OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compressio= n. + # + SECTION FV_IMAGE =3D PEIFV + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/Platfo= rms/RiscVVirt/RiscVVirt.fdf.inc new file mode 100644 index 000000000000..4cbe7f369011 --- /dev/null +++ b/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf.inc @@ -0,0 +1,66 @@ +## @file +# Definitions of Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE PFLASH1_BASE =3D 0x22000000 +DEFINE PFLASH2_BASE =3D 0x23000000 + +DEFINE FW_BASE_ADDRESS =3D $(PFLASH1_BASE) +DEFINE FW_SIZE =3D 0x00300000 +DEFINE FW_BLOCKS =3D 0x300 + +DEFINE CODE_BASE_ADDRESS =3D $(FW_BASE_ADDRESS) +DEFINE CODE_SIZE =3D 0x00240000 +DEFINE CODE_BLOCKS =3D 0x240 + +# +# Separate varstore will start at 3rd pflash address +# +DEFINE VARS_BASE_ADDRESS =3D $(PFLASH2_BASE) + +DEFINE VARS_SIZE =3D 0x000C0000 +DEFINE VARS_BLOCK_SIZE =3D 0x40000 +DEFINE VARS_BLOCKS =3D 0x3 + +# +# The size of memory region must be power of 2. +# The base address must be aligned with the size. +# +# FW memory region +# +DEFINE SECFV_OFFSET =3D 0x00000000 +DEFINE SECFV_SIZE =3D 0x00040000 +DEFINE FVMAIN_OFFSET =3D 0x00040000 +DEFINE FVMAIN_SIZE =3D 0x00200000 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +!if $(UNIFIED_VARSTORE) =3D=3D TRUE +DEFINE VARS_OFFSET =3D $(CODE_SIZE) +!else +DEFINE VARS_OFFSET =3D 0x00000000 +!endif +DEFINE VARS_LIVE_SIZE =3D 0x00040000 +DEFINE VARS_FTW_WORKING_OFFSET =3D $(VARS_OFFSET) + $(VARS_LIVE_SIZE) +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00040000 +DEFINE VARS_FTW_SPARE_OFFSET =3D $(VARS_FTW_WORKING_OFFSET) + $(VA= RS_FTW_WORKING_SIZE) +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00040000 + +# +# Base Address where SEC phase will decompress and load +# the PEI and DXE FVs +# +DEFINE MEMFD_BASE_ADDRESS =3D 0x80200000 + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency =3D 10000000 diff --git a/OvmfPkg/Platforms/RiscVVirt/VarStore.fdf.inc b/OvmfPkg/Platfor= ms/RiscVVirt/VarStore.fdf.inc new file mode 100644 index 000000000000..30b170d77997 --- /dev/null +++ b/OvmfPkg/Platforms/RiscVVirt/VarStore.fdf.inc @@ -0,0 +1,79 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_LIVE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3FFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95754): https://edk2.groups.io/g/devel/message/95754 Mute This Topic: https://groups.io/mt/94664347/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95755+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95755+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136607; cv=none; d=zohomail.com; s=zohoarc; b=UaieXSS8Qqb+YUAfDQlgc25pcu9JUyAzizTPi45APydsNjVFEgjGIczRQ/0HWyvCWQqz6tnXiWX57tfyezzTxrjwtZEBojkIvfl/mDR8hcKwXcdXpM6rNKW/iapU+cWDO+0kqCEvrNUT/YtYnC+w5H7YYLzRSpYrUunjoMduDSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136607; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=17my+UXRKvti/iS/KYJyA9HQYM+FnUzgS2mliulLGC0=; b=OOpSTWXwb8sGQ2qHTzdMidkTf3r9+739Eqjnb9ssMnP7/LtI4IbYtsoBY7xcT90kOjB/UBUmqL/YnRI7qwoCKFaNK9GBGV1P1h3Unv+Lhfag8gYMMCNa9JXeMzIQzF4i4xXaJfJYKBcf/SBO3GyLvUsdPKK83aq/UsZm6uwSSHI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95755+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136607813390.4864784772292; Sun, 30 Oct 2022 06:30:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dvMeYY1788612xtY7pt6A7mF; Sun, 30 Oct 2022 06:30:07 -0700 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web10.8247.1667136606864014423 for ; Sun, 30 Oct 2022 06:30:06 -0700 X-Received: by mail-pf1-f176.google.com with SMTP id m6so8615586pfb.0 for ; Sun, 30 Oct 2022 06:30:06 -0700 (PDT) X-Gm-Message-State: ztMTl63awiJHQiR6gKhZjOvEx1787277AA= X-Google-Smtp-Source: AMsMyM49KvKl/ifPpgN38+47ZIKOyTpUaiMJINLXUk4L9ZAx+UUg7I6Q5+/4WaCk3sIRS+MtLfkw2Q== X-Received: by 2002:a63:8449:0:b0:46e:ecba:c46d with SMTP id k70-20020a638449000000b0046eecbac46dmr8419226pgd.310.1667136606108; Sun, 30 Oct 2022 06:30:06 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:30:05 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Andrew Fish , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 29/30] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt Date: Sun, 30 Oct 2022 18:58:41 +0530 Message-Id: <20221030132842.54077-30-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136607; bh=cdvWFpDSEPQwno4CgQdF66Lp95cFlycYLQfsmoJJmfY=; h=Cc:Date:From:Reply-To:Subject:To; b=Y8dnWwTV2zfsmrSUwGyu3nYwZjNPs+T3uqRQ/e8743g32HyvZ7vlUMGJZMg/CY17d0N olT5ok0lKkAKQ3xAInFGHref9R7iaAG0+X9i2w6UUkpnPbatASriCHH/VbsyUvpNeZ49b guLwK/b/58hkFuR7zdQgBIf0Aa8F7vdiv0s= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136608207100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RiscVVirt is created to support EDK2 for RISC-V qemu virt machine platform. Add maintainer entries. Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Signed-off-by: Sunil V L --- Maintainers.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 8e81ccfdeccf..e4faee5b7684 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -533,6 +533,10 @@ F: OvmfPkg/XenResetVector/ R: Anthony Perard [sheep] R: Julien Grall [jgrall] =20 +OvmfPkg: RISC-V Qemu Virt Platform +F: OvmfPkg/Platforms/RiscVVirt +R: Sunil V L [vlsunil] + PcAtChipsetPkg F: PcAtChipsetPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95755): https://edk2.groups.io/g/devel/message/95755 Mute This Topic: https://groups.io/mt/94664350/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 08:34:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95756+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95756+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1667136610; cv=none; d=zohomail.com; s=zohoarc; b=Qiubntu/u0xzrStuJbNMtgjKtJoYZr/VWyHlMaU8/OSXFWcdMSFm0zWQrZ668L9cWsHv2pZZCAxPVbl97aGbM/swOqtUySM5lPXgVO6LGYq17TSKwIZJN4CDUbOxVuu3JfthKl+qcSepOfahTF+uqpyU8aWTsPhWxqafU/zbMGw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667136610; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=IAuh7cCXyMcbUQGfM3zJSOBpRGHqG+Jf7qFTMmZpXGw=; b=B7HSVNkdtarR0PzRV3misfqYfvFANEuPdFIA//+HxmcVQxbn9vu+dlifpEN/TJFsrWEVp7WiksPCcVK4o6d2dXMh22zhOMZqw7xhvOLUgaJK+9N7q8v/zCnGPqUFCHu1B1cDmwVDXWsHIgzcjgYXi8mTut2FjbD5SvH3CJCcd84= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95756+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667136610419453.5345402397421; Sun, 30 Oct 2022 06:30:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id H1iLYY1788612x0jKLEk3M91; Sun, 30 Oct 2022 06:30:09 -0700 X-Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) by mx.groups.io with SMTP id smtpd.web09.8128.1667136609215065592 for ; Sun, 30 Oct 2022 06:30:09 -0700 X-Received: by mail-pl1-f181.google.com with SMTP id j12so8663653plj.5 for ; Sun, 30 Oct 2022 06:30:09 -0700 (PDT) X-Gm-Message-State: FykfA3m8BlQAKWlj3RP7WQBox1787277AA= X-Google-Smtp-Source: AMsMyM5VOaPnAJM1VZRKPjiZAvWtWbp/yIWUWH9BIWN11D63y9H+IzVv2R1+Xd24aGcAHETbBz4OpA== X-Received: by 2002:a17:902:ab15:b0:187:734:96a1 with SMTP id ik21-20020a170902ab1500b00187073496a1mr7522744plb.4.1667136608428; Sun, 30 Oct 2022 06:30:08 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:30:08 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Abner Chang Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V5 30/30] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file Date: Sun, 30 Oct 2022 18:58:42 +0530 Message-Id: <20221030132842.54077-31-sunilvl@ventanamicro.com> In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667136610; bh=ZNeoki6uU3s4yPWyHz4ZYQ4ZiuBmZLdKM0VFhsMFt2c=; h=Cc:Date:From:Reply-To:Subject:To; b=j4K9cK4+cpneLd6wdB7gybJ9rH8on5j4lV0xCkguuhNTwNbUOv2Y3WS1Fo0ZHdK8ZML RFcHE/olav7pGsjhUb5jTufWKAa9caUH1Ca78VIz9L2F0216lkhU1pgkivg6Di/YzfdJV WBEZDYwFvteeiO+TYSkNw0oLJdtI29eVKqQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667136612218100009 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index a377366798b0..953361ba0479 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -27,6 +27,7 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ + "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h" ] }, "CompilerPlugin": { --=20 2.38.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95756): https://edk2.groups.io/g/devel/message/95756 Mute This Topic: https://groups.io/mt/94664352/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-