From nobody Tue Feb 10 00:22:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95129+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95129+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1665655175; cv=none; d=zohomail.com; s=zohoarc; b=mOLXaAoaXCrI0tTZe4+A0yAbMwqgwx/fGtJ7LMjPx2RjiGx8eR2v65RMWvPJEpBCpE6Yh1b/+kBHHmFubCeeNnXwH4n41HTrRn5Gtp8YJbLWWeI3YXcktmjlG2iGX2prGPRVQvk7KUKRslw1uq24Iagf54xw/hY/Jg/SGanLrpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665655175; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Dn25KSYMy06aWo0nf6ggERnCUMs2k2lK0MmcrXGWGOQ=; b=ScVCN1GQiocv3nln/33MRZn/JmCB3Ql6WcGTYF7mxwpUZnQcrgkW2A75N5lGVZFQmvSwpGCz0hc9PoOxJfB57pfG041pI0WasKaz3hTRJFG6uO7ysC4gdsI7MYlqYUmYX7uyzoTQrORMF1Tz8e9/yCc0RBzFu/mfPYOiIkASTgs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95129+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1665655175836845.3909571847352; Thu, 13 Oct 2022 02:59:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LRk5YY1788612xfimaaRg8Xh; Thu, 13 Oct 2022 02:59:35 -0700 X-Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mx.groups.io with SMTP id smtpd.web10.5679.1665655174904282491 for ; Thu, 13 Oct 2022 02:59:34 -0700 X-Received: by mail-pj1-f48.google.com with SMTP id 70so1505485pjo.4 for ; Thu, 13 Oct 2022 02:59:34 -0700 (PDT) X-Gm-Message-State: LftUPhoh8gbM368WdoRx0F8px1787277AA= X-Google-Smtp-Source: AMsMyM7njfGwFGfz+tu4Nn+/S/rXib7waYySEY2ZkR9ckYflq1DBLapo9M3pyBCwWMKLQvhv0iyYzQ== X-Received: by 2002:a17:902:d50f:b0:178:6505:fae3 with SMTP id b15-20020a170902d50f00b001786505fae3mr34952300plg.54.1665655174097; Thu, 13 Oct 2022 02:59:34 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id w8-20020a17090abc0800b0020d43c5c9a0sm2931845pjr.18.2022.10.13.02.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 02:59:33 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 19/34] UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support Date: Thu, 13 Oct 2022 15:28:14 +0530 Message-Id: <20221013095829.1454581-20-sunilvl@ventanamicro.com> In-Reply-To: <20221013095829.1454581-1-sunilvl@ventanamicro.com> References: <20221013095829.1454581-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1665655175; bh=a1YZAJDREG6JsU2B/NMQ0ZRrqpLXZwREzQq0JHR7o48=; h=Cc:Date:From:Reply-To:Subject:To; b=ktpniKg+CW09KD7Zz5E2mnRzrLsdZEHEHqI+4ussvd2azsmp6+KsTPWmctOQp4ieT4X SHT5ZZ4wni0dNH3QdRq9j5/+24xDPWsb9sq0F5wyJF5W7+6bIOdOe4sjLdZxNzIRbzblk xoXMyWiovWeiNXnIX6qbwkgqR/XtFeUj3Ms= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1665655176125100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_U= EFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dsc | 12 +++--- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f694b3a77c2e..6ea90507e36f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -122,9 +122,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i= nf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -141,10 +145,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i= nf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandle= rLib.inf diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. =20 Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -12,8 +13,41 @@ // // Global Variables // -STATIC BOOLEAN mInterruptState =3D FALSE; -STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is = not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; =20 EFI_CPU_ARCH_PROTOCOL gCpu =3D { CpuFlushCpuDataCache, @@ -284,15 +318,39 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; =20 - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + InitializeCpuExceptionHandlers (NULL); =20 // // Make sure interrupts are disabled // DisableInterrupts (); =20 + // + // Install Boot protocol + // + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95129): https://edk2.groups.io/g/devel/message/95129 Mute This Topic: https://groups.io/mt/94300403/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-