From nobody Mon Feb 9 20:30:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+94918+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+94918+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1665396785; cv=none; d=zohomail.com; s=zohoarc; b=U59ZPk/1+B4HcWrJrG4cqz6byallDv+kRY0IuOQcYsmGmhRCz22EZZQv1mgtmJHoXOEXQ6FR/4X0hCvcx3hJS+C0zWRdm1qzXzyQ2f1KufRY4ThFYwOgZz+12o/XjSn4x+gm1xcuoFFn6NS+qo7OlMCDsW191u5ZM+Wf3MwH/mY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665396785; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=yWydyozO1Ul+Hu6NoVcMmLky8RrB5b9sd7jIXXTowxo=; b=FXTw/O9cew2iwL3jESWSxRIWhGSy5hvrU/SOWMWvIhkHmYbHFJePXuV7HxknnaIjIWPs0/5KdrBZBu3PD5Nnjiwiunqvo0glsN7IY8LdB77KnbaSpG0q47wHXiBYJl2+3ZO9zMZzpsoTk7Lm0vo+PJmr2ksg5A9VyK18udsODsY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+94918+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1665396785211967.4880137050403; Mon, 10 Oct 2022 03:13:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HO9MYY1788612xF2V1qin4C7; Mon, 10 Oct 2022 03:13:03 -0700 X-Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) by mx.groups.io with SMTP id smtpd.web10.4743.1665396780291515258 for ; Mon, 10 Oct 2022 03:13:02 -0700 X-Received: by mail-pf1-f169.google.com with SMTP id y8so10329021pfp.13 for ; Mon, 10 Oct 2022 03:13:02 -0700 (PDT) X-Gm-Message-State: n8st2wsFPk10jBqPDhhj4gEUx1787277AA= X-Google-Smtp-Source: AMsMyM74VOsxyLVTfO401EhJ52Oq4YZI/DkCmbjxQcfAVhjn/Gip2GNdilaoiv+H2stBQ+2dUTmjRg== X-Received: by 2002:a63:d551:0:b0:452:87e0:73d5 with SMTP id v17-20020a63d551000000b0045287e073d5mr15549077pgi.488.1665396782164; Mon, 10 Oct 2022 03:13:02 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id h17-20020a170902f55100b001788ccecbf5sm6302138plf.31.2022.10.10.03.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 03:13:01 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH 19/29] UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support Date: Mon, 10 Oct 2022 15:41:52 +0530 Message-Id: <20221010101202.1146624-20-sunilvl@ventanamicro.com> In-Reply-To: <20221010101202.1146624-1-sunilvl@ventanamicro.com> References: <20221010101202.1146624-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1665396783; bh=MqANDDFj11pdOqQrVrSrnsBX1vNgQ2P1dETLK93CZbY=; h=Cc:Date:From:Reply-To:Subject:To; b=cKH9CY6NoznqD6cvZuqWeBQsniOrQ2VsFkbxPjujMUYUfHKMQC+pOgNDt3pbhNDuTFV E5V9eU+7jAx0GwZzIBMI3WArJH6VMoaCyffyf9aB6eSudGcVAzJgvcK2NuN7Sx50fv5Wf Bwl7G6A8rUSksVra7daQy0RjYgSH5hRtgk8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1665396787295100041 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_U= EFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dsc | 12 +++--- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f694b3a77c2e..6ea90507e36f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -122,9 +122,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i= nf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -141,10 +145,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i= nf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandle= rLib.inf diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. =20 Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -12,8 +13,41 @@ // // Global Variables // -STATIC BOOLEAN mInterruptState =3D FALSE; -STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is = not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; =20 EFI_CPU_ARCH_PROTOCOL gCpu =3D { CpuFlushCpuDataCache, @@ -284,15 +318,39 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; =20 - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + InitializeCpuExceptionHandlers (NULL); =20 // // Make sure interrupts are disabled // DisableInterrupts (); =20 + // + // Install Boot protocol + // + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#94918): https://edk2.groups.io/g/devel/message/94918 Mute This Topic: https://groups.io/mt/94233027/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-