From nobody Sat May 4 05:18:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92473+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92473+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660636666; cv=none; d=zohomail.com; s=zohoarc; b=iVhoETelIff2IrsDKORVC0adt3p3Mze6o0D9r6fDR/XEELzqnMRlOju2ktLTYIuPdRhw6Pd0gko0nOiXwtNJB29jqRsAB+lDHew6hLGb4KA7ePSrD7ZU2nocJLJmhUZhYFojS1W3vprsUkXo0MCYHfHL2tIy1cy/RsUbFVyzwM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660636666; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=XpxHo9XhS4rt1POHjPc08Hb768SzVg9md5H1gN66Q2M=; b=bBt8PeYpUw3yso0oGPnsTcvWWBvM9bMnQWOyew0PhxTJ50G5u0UIlTXwHGmoQiE86eY+iXDRwCzEbX1dUIyO1Hfz4VRWSKca4sxRPd/5K94P6rJVHn+BOzYhfLP9joomiWgMss00ErMICaeac+aFl1upB5V2+X5uVZl8hmhd5AA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92473+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1660636666297639.0037802561914; Tue, 16 Aug 2022 00:57:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LPRSYY1788612xnL8XO04ANk; Tue, 16 Aug 2022 00:57:46 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.12972.1660636664990320101 for ; Tue, 16 Aug 2022 00:57:45 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="293427015" X-IronPort-AV: E=Sophos;i="5.93,240,1654585200"; d="scan'208";a="293427015" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2022 00:57:44 -0700 X-IronPort-AV: E=Sophos;i="5.93,240,1654585200"; d="scan'208";a="635792324" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.182.56]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2022 00:57:42 -0700 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH] UefiCpuPkg: Use Top of each AP's stack to save CpuMpData Date: Tue, 16 Aug 2022 15:57:15 +0800 Message-Id: <20220816075715.932-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: iJn6UGr0AdWE6Udz61UecCmyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660636666; bh=gRDz9Xbb2Pk1aLlDpNNKNkQzV5HxYzqe06Gkd1ERGIU=; h=Cc:Date:From:Reply-To:Subject:To; b=kT/9oQiKIzpUPnd4keHAHqkJemygu2R2/wVlz9sI15FxFsk4vuKelsZBAiEyt1z5J6J 4omKuaDG7t58ZE5BEXq8yVPubSMad9UWnjXIDpGCt79JjsQm83JBjlqnFpC3WfMrfz+jh 28Ac2F5JphPcIQHYo64KLvZjF/Qn/ioeDOA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660636668204100003 Content-Type: text/plain; charset="utf-8" To remove the dependency of CPU register, 4/8 byte at the top of the stack is occupied for CpuMpData. BIST information is also taken care here. This modification is only for PEI phase, since in DXE phase CpuMpData is accessed via global variable. Signed-off-by: Yuanhao Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar --- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 5 +++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 41 ++++++++++++++----- UefiCpuPkg/Library/MpInitLib/MpLib.h | 8 ++++ UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 10 +++-- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 +++ 5 files changed, 56 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index 28301bb8f0..4714f2d527 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -179,6 +179,11 @@ ProgramStack: mov esp, dword [edi + CPU_INFO_IN_HOB.ApTopOfStack] =20 CProcedureInvoke: + ; + ; Reserve 4 bytes for storing CpuMpData. + ; Using sub esp instead of push ebp to avoid overwriting the existed C= puMpData + ; + sub esp, 4 push ebp ; push BIST data at top of AP stack xor ebp, ebp ; clear ebp for call stack trace push ebp diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 8d1f24370a..a9188eb59f 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -571,6 +571,7 @@ InitializeApData ( { CPU_INFO_IN_HOB *CpuInfoInHob; MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; + AP_STACK_DATA *ApStackData; =20 CpuInfoInHob =3D (CPU_INFO_IN_HOB *)(UINT= N)CpuMpData->CpuInfoInHob; CpuInfoInHob[ProcessorNumber].InitialApicId =3D GetInitialApicId (); @@ -578,6 +579,12 @@ InitializeApData ( CpuInfoInHob[ProcessorNumber].Health =3D BistData; CpuInfoInHob[ProcessorNumber].ApTopOfStack =3D ApTopOfStack; =20 + // + // AP_STACK_DATA is stored at the top of AP Stack + // + ApStackData =3D (AP_STACK_DATA *)((UINTN)ApTopOfStack - sizeof (= AP_STACK_DATA)); + ApStackData->MpData =3D CpuMpData; + CpuMpData->CpuData[ProcessorNumber].Waiting =3D FALSE; CpuMpData->CpuData[ProcessorNumber].CpuHealthy =3D (BistData =3D=3D 0) ?= TRUE : FALSE; =20 @@ -623,6 +630,7 @@ ApWakeupFunction ( CPU_INFO_IN_HOB *CpuInfoInHob; UINT64 ApTopOfStack; UINTN CurrentApicMode; + AP_STACK_DATA *ApStackData; =20 // // AP finished assembly code and begin to execute C code @@ -648,7 +656,9 @@ ApWakeupFunction ( // This is first time AP wakeup, get BIST information from AP stack // ApTopOfStack =3D CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpDa= ta->CpuApStackSize; - BistData =3D *(UINT32 *)((UINTN)ApTopOfStack - sizeof (UINTN)); + ApStackData =3D (AP_STACK_DATA *)((UINTN)ApTopOfStack - sizeof (AP_= STACK_DATA)); + BistData =3D (UINT32)ApStackData->Bist; + // // CpuMpData->CpuData[0].VolatileRegisters is initialized based on B= SP environment, // to initialize AP in InitConfig path. @@ -1796,30 +1806,41 @@ MpInitLibInitialize ( AsmGetAddressMap (&AddressMap); GetApResetVectorSize (&AddressMap, &ApResetVectorSizeBelow1Mb, &ApResetV= ectorSizeAbove1Mb); ApStackSize =3D PcdGet32 (PcdCpuApStackSize); - ApLoopMode =3D GetApLoopMode (&MonitorFilterSize); + // + // ApStackSize must be power of 2 + // + ASSERT ((ApStackSize & (ApStackSize - 1)) =3D=3D 0); + ApLoopMode =3D GetApLoopMode (&MonitorFilterSize); =20 // // Save BSP's Control registers for APs. // SaveVolatileRegisters (&VolatileRegisters); =20 + // + // Allocate extra ApStackSize to let AP stack align on ApStackSize bound= ay + // BufferSize =3D ApStackSize * MaxLogicalProcessorNumber; + BufferSize +=3D ApStackSize; BufferSize +=3D MonitorFilterSize * MaxLogicalProcessorNumber; BufferSize +=3D ApResetVectorSizeBelow1Mb; BufferSize =3D ALIGN_VALUE (BufferSize, 8); BufferSize +=3D VolatileRegisters.Idtr.Limit + 1; BufferSize +=3D sizeof (CPU_MP_DATA); BufferSize +=3D (sizeof (CPU_AP_DATA) + sizeof (CPU_INFO_IN_HOB))* MaxLo= gicalProcessorNumber; - MpBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); + // + // Allocate extra ApStackSize to let stack align on ApStackSize bounday + // + MpBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); ASSERT (MpBuffer !=3D NULL); ZeroMem (MpBuffer, BufferSize); - Buffer =3D (UINTN)MpBuffer; + Buffer =3D ALIGN_VALUE ((UINTN)MpBuffer, ApStackSize); =20 // - // The layout of the Buffer is as below: + // The layout of the Buffer is as below (lower address on top): // - // +--------------------+ <-- Buffer - // AP Stacks (N) + // +--------------------+ <-- Buffer (Pointer of CpuMpData is stored = in the top of each AP's stack.) + // AP Stacks (N) (StackTop =3D (RSP + ApStackSize= ) & ~ApStackSize)) // +--------------------+ <-- MonitorBuffer // AP Monitor Filters (N) // +--------------------+ <-- BackupBufferAddr (CpuMpData->BackupBuff= er) @@ -1827,7 +1848,7 @@ MpInitLibInitialize ( // +--------------------+ // Padding // +--------------------+ <-- ApIdtBase (8-byte boundary) - // AP IDT All APs share one separate IDT. So AP can g= et address of CPU_MP_DATA from IDT Base. + // AP IDT All APs share one separate IDT. // +--------------------+ <-- CpuMpData // CPU_MP_DATA // +--------------------+ <-- CpuMpData->CpuData @@ -1866,8 +1887,8 @@ MpInitLibInitialize ( // Make sure no memory usage outside of the allocated buffer. // ASSERT ( - (CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProces= sorNumber) =3D=3D - Buffer + BufferSize + (CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProces= sorNumber) <=3D + (UINTN)MpBuffer + BufferSize ); =20 // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 974fb76019..69b621a340 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -302,6 +302,14 @@ struct _CPU_MP_DATA { UINT64 GhcbBase; }; =20 +// +// AP_STACK_DATA is stored at the top of each AP stack. +// +typedef struct { + UINTN Bist; + CPU_MP_DATA *MpData; +} AP_STACK_DATA; + #define AP_SAFE_STACK_SIZE 128 #define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE =20 diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 65400b95a2..e732371ddd 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -89,7 +89,7 @@ EnableDebugAgent ( /** Get pointer to CPU MP Data structure. For BSP, the pointer is retrieved from HOB. - For AP, the structure is just after IDT. + For AP, the structure is stored in the top of each AP's stack. =20 @return The pointer to CPU MP Data structure. **/ @@ -100,15 +100,17 @@ GetCpuMpData ( { CPU_MP_DATA *CpuMpData; MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; - IA32_DESCRIPTOR Idtr; + UINTN ApTopOfStack; + AP_STACK_DATA *ApStackData; =20 ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); if (ApicBaseMsr.Bits.BSP =3D=3D 1) { CpuMpData =3D GetCpuMpDataFromGuidedHob (); ASSERT (CpuMpData !=3D NULL); } else { - AsmReadIdtr (&Idtr); - CpuMpData =3D (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1); + ApTopOfStack =3D ALIGN_VALUE ((UINTN)&ApTopOfStack, (UINTN)PcdGet32 (P= cdCpuApStackSize)); + ApStackData =3D (AP_STACK_DATA *)((UINTN)ApTopOfStack- sizeof (AP_STA= CK_DATA)); + CpuMpData =3D (CPU_MP_DATA *)ApStackData->MpData; } =20 return CpuMpData; diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 1daaa72b1e..322bdd03e6 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -237,11 +237,17 @@ ProgramStack: mov rsp, qword [rdi + CPU_INFO_IN_HOB.ApTopOfStack] =20 CProcedureInvoke: + ; + ; Reserve 8 bytes for storing CpuMpData. + ; Using sub rsp instead of push rbp to avoid overwriting existed CpuMp= Data + ; + sub rsp, 8 push rbp ; Push BIST data at top of AP stack xor rbp, rbp ; Clear ebp for call stack trace push rbp mov rbp, rsp =20 + push qword 0 ; Push 8 bytes for alignment mov rax, qword [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitializeFlo= atingPointUnits)] sub rsp, 20h call rax ; Call assembly function to initialize FP= U per UEFI spec --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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