From nobody Sun May 5 05:18:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92337+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92337+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660189896; cv=none; d=zohomail.com; s=zohoarc; b=GxIZ6f3zEZaM8ZukUr5T+Svkf+0VhICztmilaq1WW4uTwQ7Ajq+KKeD9Qs851URjkDGs53BLKzJjH88jNVkL2/vTjphmgIQ3x8r6FFhLVJhx55fAlOOZ1EB+3qo6BuVbTNqANOgIjPHlcjZTVcQysqVjLXXDVrTk4W5bpEC/qT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660189896; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Hmfpz06kMGfBosxu9yYDvHRbzbtbGD6Hkw4l4RmjmiM=; b=APDKjLXFU9g29AD3RqkWJ3Qe08kKhmRCncrZH1Dv7p7s9Ce18y687h91eGxgIX98xAVomf0FjP5Eb4XSuCdujYQR3S2/O3fOr1EsDHvgRPyFPNvIxs419LqeuPqFF/6haa7bwI13UbsPC6M6/WSQwdHm6r/8wmDEgIqzS9AbO+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92337+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1660189896171787.2030436251428; Wed, 10 Aug 2022 20:51:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id GqCXYY1788612xQj4cgddv3M; Wed, 10 Aug 2022 20:51:34 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web08.2543.1660189889088559202 for ; Wed, 10 Aug 2022 20:51:34 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10435"; a="377541695" X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="377541695" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 20:51:33 -0700 X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="665190594" X-Received: from duntan-mobl.ccr.corp.intel.com ([10.239.157.47]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 20:51:30 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Ray Ni Subject: [edk2-devel] [Patch V3 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag Date: Thu, 11 Aug 2022 11:51:12 +0800 Message-Id: <20220811035113.694-2-dun.tan@intel.com> In-Reply-To: <20220811035113.694-1-dun.tan@intel.com> References: <20220811035113.694-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: kPlNuvYfgwVIyYpHzzNgNOu6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660189894; bh=TzwtmkUqUTq8zFAWjB/NyLMlNfGcYDcBjHwM/4MiHXU=; h=Cc:Date:From:Reply-To:Subject:To; b=QA5izUwlyltATaCHc2WxFYNYI6qHy62LEojbMqU/YWCnu7xw4AiFYIUHzhqqOGY4rbV 4Erk2QChuUnpbs/3vUCN/0dR7H3wOYza94SUj1C3cLMGqW/3Dks70inbowR139NVlTxOW A69OHN1G+i9JfIcroAYsGjEOlj68ZN46J6M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660189897413100003 Content-Type: text/plain; charset="utf-8" This patch is code refactoring and doesn't change any functionality. Add a new mIsShadowStack flag to identify whether current memory is shadow stack. Previous smm code logic regards a RO range as shadow stack and set the dirty bit in corresponding page table entry if mInternalCr3 is not 0, which may be confusing. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Rahul Kumar Cc: Ray Ni Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 1f7cc15727..10de8dd8e4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -32,7 +32,8 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 }, }; =20 -UINTN mInternalCr3; +UINTN mInternalCr3; +BOOLEAN mIsShadowStack =3D FALSE; =20 /** Set the internal page table base address. @@ -249,7 +250,7 @@ ConvertPageEntryAttribute ( if ((Attributes & EFI_MEMORY_RO) !=3D 0) { if (IsSet) { NewPageEntry &=3D ~(UINT64)IA32_PG_RW; - if (mInternalCr3 !=3D 0) { + if (mIsShadowStack) { // Environment setup // ReadOnly page need set Dirty bit for shadow stack NewPageEntry |=3D IA32_PG_D; @@ -734,10 +735,11 @@ SetShadowStack ( EFI_STATUS Status; =20 SetPageTableBase (Cr3); - - Status =3D SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); + mIsShadowStack =3D TRUE; + Status =3D SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMO= RY_RO); =20 SetPageTableBase (0); + mIsShadowStack =3D FALSE; =20 return Status; } --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92337): https://edk2.groups.io/g/devel/message/92337 Mute This Topic: https://groups.io/mt/92952029/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 05:18:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92338+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92338+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660189898; cv=none; d=zohomail.com; s=zohoarc; b=njokFt2J6VrHF6e/rujcB8JP7JDVJS7hwsbpy9GXe7QTyxD5xVUYLi/9nkClvyMnSYKZu8+Uy+LdgZRH9nwAFij1R0z5FReDFuzS8Xzz6jOyPNI/XMfl6DhwtvvdF5ZWkKzTkR51NfW3QXTgL+8ONqMNec3+0HLqesL0GbVN4zk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660189898; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=STRDL1XTF9/SXBOLPR0bt4MQ1UR6/D3BwKRRkHmQUBM=; b=jm89RGla0YmopHxXFr3nl+rpcv2oxUAvlpZ59JMQ87DmtXD938UtBj3QYDI4J3HuraV6bP1H80HO5ArkXJRNp9EhgpxQwYPFiUO6VV+DGx8RLoiLDCVDXNzIgIUuMDMCI/akBHaAouU2KULnC4uWmDfCkSLny1zM63wiVGz0tII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92338+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1660189898446886.7210513501722; Wed, 10 Aug 2022 20:51:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id f4uqYY1788612x0pbpx1nQKO; Wed, 10 Aug 2022 20:51:37 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web08.2543.1660189889088559202 for ; Wed, 10 Aug 2022 20:51:36 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10435"; a="377541698" X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="377541698" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 20:51:34 -0700 X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="665190618" X-Received: from duntan-mobl.ccr.corp.intel.com ([10.239.157.47]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 20:51:33 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Ray Ni Subject: [edk2-devel] [Patch V3 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm Date: Thu, 11 Aug 2022 11:51:13 +0800 Message-Id: <20220811035113.694-3-dun.tan@intel.com> In-Reply-To: <20220811035113.694-1-dun.tan@intel.com> References: <20220811035113.694-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: zThgVm1oE3o0j4Y1qnjpx6drx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660189897; bh=xnI5OBaqx4o1WNYCtXI1gAJAPJAFDaJmAF2qDTPaGrk=; h=Cc:Date:From:Reply-To:Subject:To; b=joiA9XkPbQLtTF6d4aWG1a4efXigWjBnQSGtkiyBhmv5jIqvHzWfaFLUIf31VH5frYx bqebug3rWlxOHJ2SSWM9SZG3MNDXlCngSA2mBgzxR3CBojW90d9kdk/YX3h1P7u95eBwW IJGpKJkyF0+jc1B7+wxig0kbEMiG7Y0Pkho= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660189899460100005 Content-Type: text/plain; charset="utf-8" This patch is code refactoring and doesn't change any functionality. Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous code, mInternalCr3 is used to pass address of page table which is different from Cr3 register in different level of SetMemoryAttributes function. Now remove it and pass the page table base address from the root function parameter to simplify the code logic. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Rahul Kumar Cc: Ray Ni Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 30 +++++------------= ------------- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 +++++++++--------= --------- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 113 +++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++---------------------------------= --------------------- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 74 +++++++++++++++++= ++++++--------------------------------------------------- 4 files changed, 96 insertions(+), 147 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpu= DxeSmm/Ia32/PageTbl.c index 8ec8790c05..97058a2810 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -28,26 +28,6 @@ EnableCet ( VOID ); =20 -/** - Get page table base address and the depth of the page table. - - @param[out] Base Page table base address. - @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level p= aging. -**/ -VOID -GetPageTable ( - OUT UINTN *Base, - OUT BOOLEAN *FiveLevels OPTIONAL - ) -{ - *Base =3D ((mInternalCr3 =3D=3D 0) ? - (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) : - mInternalCr3); - if (FiveLevels !=3D NULL) { - *FiveLevels =3D FALSE; - } -} - /** Create PageTable for SMM use. =20 @@ -297,10 +277,10 @@ SetPageTableAttributes ( DEBUG ((DEBUG_INFO, "Start...\n")); PageTableSplitted =3D FALSE; =20 - GetPageTable (&PageTableBase, NULL); - L3PageTable =3D (UINT64 *)PageTableBase; + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + L3PageTable =3D (UINT64 *)PageTableBase; =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4K= B, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)= PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index3 =3D 0; Index3 < 4; Index3++) { @@ -309,7 +289,7 @@ SetPageTableAttributes ( continue; } =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, = SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRES= S)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index2 =3D 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) { @@ -323,7 +303,7 @@ SetPageTableAttributes ( continue; } =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable= , SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDR= ESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted =3D (PageTableSplitted || IsSplitted); } } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index dfeceec2aa..ef8bf5947d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -264,7 +264,7 @@ extern UINTN mMaxNumberOfCpus; extern UINTN mNumberOfCpus; extern EFI_SMM_CPU_PROTOCOL mSmmCpu; extern EFI_MM_MP_PROTOCOL mSmmMp; -extern UINTN mInternalCr3; +extern BOOLEAN m5LevelPagingNeeded; =20 /// /// The mode of the CPU at the time an SMI occurs @@ -682,7 +682,6 @@ SmmBlockingStartupThisAp ( =20 **/ EFI_STATUS -EFIAPI SmmSetMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, @@ -712,7 +711,6 @@ SmmSetMemoryAttributes ( =20 **/ EFI_STATUS -EFIAPI SmmClearMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, @@ -957,22 +955,12 @@ SetPageTableAttributes ( VOID ); =20 -/** - Get page table base address and the depth of the page table. - - @param[out] Base Page table base address. - @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level p= aging. -**/ -VOID -GetPageTable ( - OUT UINTN *Base, - OUT BOOLEAN *FiveLevels OPTIONAL - ); - /** This function sets the attributes for the memory region specified by Bas= eAddress and Length from their current attributes to the attributes specified by Attr= ibutes. =20 + @param[in] PageTableBase The page table base. + @param[in] EnablePML5Paging If PML5 paging is enabled. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to set for the = memory region. @@ -993,8 +981,9 @@ GetPageTable ( =20 **/ EFI_STATUS -EFIAPI SmmSetMemoryAttributesEx ( + IN UINTN PageTableBase, + IN BOOLEAN EnablePML5Paging, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, @@ -1005,6 +994,8 @@ SmmSetMemoryAttributesEx ( This function clears the attributes for the memory region specified by B= aseAddress and Length from their current attributes to the attributes specified by Attr= ibutes. =20 + @param[in] PageTableBase The page table base. + @param[in] EnablePML5Paging If PML5 paging is enabled. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to clear for th= e memory region. @@ -1025,8 +1016,9 @@ SmmSetMemoryAttributesEx ( =20 **/ EFI_STATUS -EFIAPI SmmClearMemoryAttributesEx ( + IN UINTN PageTableBase, + IN BOOLEAN EnablePML5Paging, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 10de8dd8e4..773ab927e6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -32,23 +32,8 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 }, }; =20 -UINTN mInternalCr3; -BOOLEAN mIsShadowStack =3D FALSE; - -/** - Set the internal page table base address. - If it is non zero, further MemoryAttribute modification will be on this = page table. - If it is zero, further MemoryAttribute modification will be on real page= table. - - @param Cr3 page table base. -**/ -VOID -SetPageTableBase ( - IN UINTN Cr3 - ) -{ - mInternalCr3 =3D Cr3; -} +BOOLEAN mIsShadowStack =3D FALSE; +BOOLEAN m5LevelPagingNeeded =3D FALSE; =20 /** Return length according to page attributes. @@ -99,31 +84,31 @@ PageAttributeToMask ( /** Return page table entry to match the address. =20 - @param[in] Address The address to be checked. - @param[out] PageAttributes The page attribute of the page entry. + @param[in] PageTableBase The page table base. + @param[in] Enable5LevelPaging If PML5 paging is enabled. + @param[in] Address The address to be checked. + @param[out] PageAttributes The page attribute of the page entry. =20 @return The page entry. **/ VOID * GetPageTableEntry ( + IN UINTN PageTableBase, + IN BOOLEAN Enable5LevelPaging, IN PHYSICAL_ADDRESS Address, OUT PAGE_ATTRIBUTE *PageAttribute ) { - UINTN Index1; - UINTN Index2; - UINTN Index3; - UINTN Index4; - UINTN Index5; - UINT64 *L1PageTable; - UINT64 *L2PageTable; - UINT64 *L3PageTable; - UINT64 *L4PageTable; - UINT64 *L5PageTable; - UINTN PageTableBase; - BOOLEAN Enable5LevelPaging; - - GetPageTable (&PageTableBase, &Enable5LevelPaging); + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINTN Index5; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + UINT64 *L5PageTable; =20 Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; Index4 =3D ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK; @@ -399,6 +384,8 @@ SplitPage ( =20 Caller should make sure BaseAddress and Length is at page boundary. =20 + @param[in] PageTableBase The page table base. + @param[in] EnablePML5Paging If PML5 paging is enabled. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to modify for t= he memory region. @@ -420,8 +407,9 @@ SplitPage ( range specified by BaseAddress and Leng= th. **/ RETURN_STATUS -EFIAPI ConvertMemoryPageAttributes ( + IN UINTN PageTableBase, + IN BOOLEAN EnablePML5Paging, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, @@ -475,7 +463,7 @@ ConvertMemoryPageAttributes ( // Below logic is to check 2M/4K page to make sure we do not waste memor= y. // while (Length !=3D 0) { - PageEntry =3D GetPageTableEntry (BaseAddress, &PageAttribute); + PageEntry =3D GetPageTableEntry (PageTableBase, EnablePML5Paging, Base= Address, &PageAttribute); if (PageEntry =3D=3D NULL) { return RETURN_UNSUPPORTED; } @@ -558,6 +546,8 @@ FlushTlbForAll ( This function sets the attributes for the memory region specified by Bas= eAddress and Length from their current attributes to the attributes specified by Attr= ibutes. =20 + @param[in] PageTableBase The page table base. + @param[in] EnablePML5Paging If PML5 paging is enabled. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to set for the = memory region. @@ -578,8 +568,9 @@ FlushTlbForAll ( =20 **/ EFI_STATUS -EFIAPI SmmSetMemoryAttributesEx ( + IN UINTN PageTableBase, + IN BOOLEAN EnablePML5Paging, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, @@ -589,7 +580,7 @@ SmmSetMemoryAttributesEx ( EFI_STATUS Status; BOOLEAN IsModified; =20 - Status =3D ConvertMemoryPageAttributes (BaseAddress, Length, Attributes,= TRUE, IsSplitted, &IsModified); + Status =3D ConvertMemoryPageAttributes (PageTableBase, EnablePML5Paging,= BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified); if (!EFI_ERROR (Status)) { if (IsModified) { // @@ -606,6 +597,8 @@ SmmSetMemoryAttributesEx ( This function clears the attributes for the memory region specified by B= aseAddress and Length from their current attributes to the attributes specified by Attr= ibutes. =20 + @param[in] PageTableBase The page table base. + @param[in] EnablePML5Paging If PML5 paging is enabled. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to clear for th= e memory region. @@ -626,8 +619,9 @@ SmmSetMemoryAttributesEx ( =20 **/ EFI_STATUS -EFIAPI SmmClearMemoryAttributesEx ( + IN UINTN PageTableBase, + IN BOOLEAN EnablePML5Paging, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, @@ -637,7 +631,7 @@ SmmClearMemoryAttributesEx ( EFI_STATUS Status; BOOLEAN IsModified; =20 - Status =3D ConvertMemoryPageAttributes (BaseAddress, Length, Attributes,= FALSE, IsSplitted, &IsModified); + Status =3D ConvertMemoryPageAttributes (PageTableBase, EnablePML5Paging,= BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified); if (!EFI_ERROR (Status)) { if (IsModified) { // @@ -673,14 +667,20 @@ SmmClearMemoryAttributesEx ( =20 **/ EFI_STATUS -EFIAPI SmmSetMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes ) { - return SmmSetMemoryAttributesEx (BaseAddress, Length, Attributes, NULL); + IA32_CR4 Cr4; + UINTN PageTableBase; + BOOLEAN Enable5LevelPaging; + + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + Cr4.UintN =3D AsmReadCr4 (); + Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); + return SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, Base= Address, Length, Attributes, NULL); } =20 /** @@ -706,14 +706,20 @@ SmmSetMemoryAttributes ( =20 **/ EFI_STATUS -EFIAPI SmmClearMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes ) { - return SmmClearMemoryAttributesEx (BaseAddress, Length, Attributes, NULL= ); + IA32_CR4 Cr4; + UINTN PageTableBase; + BOOLEAN Enable5LevelPaging; + + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + Cr4.UintN =3D AsmReadCr4 (); + Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); + return SmmClearMemoryAttributesEx (PageTableBase, Enable5LevelPaging, Ba= seAddress, Length, Attributes, NULL); } =20 /** @@ -734,11 +740,8 @@ SetShadowStack ( { EFI_STATUS Status; =20 - SetPageTableBase (Cr3); mIsShadowStack =3D TRUE; - Status =3D SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMO= RY_RO); - - SetPageTableBase (0); + Status =3D SmmSetMemoryAttributesEx (Cr3, m5LevelPagingNeeded, B= aseAddress, Length, EFI_MEMORY_RO, NULL); mIsShadowStack =3D FALSE; =20 return Status; @@ -762,12 +765,7 @@ SetNotPresentPage ( { EFI_STATUS Status; =20 - SetPageTableBase (Cr3); - - Status =3D SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RP); - - SetPageTableBase (0); - + Status =3D SmmSetMemoryAttributesEx (Cr3, m5LevelPagingNeeded, BaseAddre= ss, Length, EFI_MEMORY_RP, NULL); return Status; } =20 @@ -1560,6 +1558,9 @@ EdkiiSmmGetMemoryAttributes ( UINT64 MemAttr; PAGE_ATTRIBUTE PageAttr; INT64 Size; + UINTN PageTableBase; + BOOLEAN EnablePML5Paging; + IA32_CR4 Cr4; =20 if ((Length < SIZE_4KB) || (Attributes =3D=3D NULL)) { return EFI_INVALID_PARAMETER; @@ -1568,8 +1569,12 @@ EdkiiSmmGetMemoryAttributes ( Size =3D (INT64)Length; MemAttr =3D (UINT64)-1; =20 + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + Cr4.UintN =3D AsmReadCr4 (); + EnablePML5Paging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); + do { - PageEntry =3D GetPageTableEntry (BaseAddress, &PageAttr); + PageEntry =3D GetPageTableEntry (PageTableBase, EnablePML5Paging, Base= Address, &PageAttr); if ((PageEntry =3D=3D NULL) || (PageAttr =3D=3D PageNone)) { return EFI_UNSUPPORTED; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 538394f239..6587212f4e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -18,7 +18,6 @@ extern UINTN mSmmShadowStackSize; LIST_ENTRY mPagePool =3D INITIALIZE_LIST_HEAD_VAR= IABLE (mPagePool); BOOLEAN m1GPageTableSupport =3D FALSE; BOOLEAN mCpuSmmRestrictedMemoryAccess; -BOOLEAN m5LevelPagingNeeded; X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded; =20 /** @@ -113,36 +112,6 @@ Is5LevelPagingNeeded ( } } =20 -/** - Get page table base address and the depth of the page table. - - @param[out] Base Page table base address. - @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level p= aging. -**/ -VOID -GetPageTable ( - OUT UINTN *Base, - OUT BOOLEAN *FiveLevels OPTIONAL - ) -{ - IA32_CR4 Cr4; - - if (mInternalCr3 =3D=3D 0) { - *Base =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; - if (FiveLevels !=3D NULL) { - Cr4.UintN =3D AsmReadCr4 (); - *FiveLevels =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); - } - - return; - } - - *Base =3D mInternalCr3; - if (FiveLevels !=3D NULL) { - *FiveLevels =3D m5LevelPagingNeeded; - } -} - /** Set sub-entries number in entry. =20 @@ -1195,20 +1164,21 @@ SetPageTableAttributes ( VOID ) { - UINTN Index2; - UINTN Index3; - UINTN Index4; - UINTN Index5; - UINT64 *L1PageTable; - UINT64 *L2PageTable; - UINT64 *L3PageTable; - UINT64 *L4PageTable; - UINT64 *L5PageTable; - UINTN PageTableBase; - BOOLEAN IsSplitted; - BOOLEAN PageTableSplitted; - BOOLEAN CetEnabled; - BOOLEAN Enable5LevelPaging; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINTN Index5; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + UINT64 *L5PageTable; + UINTN PageTableBase; + BOOLEAN IsSplitted; + BOOLEAN PageTableSplitted; + BOOLEAN CetEnabled; + BOOLEAN Enable5LevelPaging; + IA32_CR4 Cr4; =20 // // Don't mark page table memory as read-only if @@ -1258,11 +1228,13 @@ SetPageTableAttributes ( PageTableSplitted =3D FALSE; L5PageTable =3D NULL; =20 - GetPageTable (&PageTableBase, &Enable5LevelPaging); + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + Cr4.UintN =3D AsmReadCr4 (); + Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); =20 if (Enable5LevelPaging) { L5PageTable =3D (UINT64 *)PageTableBase; - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_= 4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PH= YSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted =3D (PageTableSplitted || IsSplitted); } =20 @@ -1276,7 +1248,7 @@ SetPageTableAttributes ( L4PageTable =3D (UINT64 *)PageTableBase; } =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, = SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PH= YSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index4 =3D 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) { @@ -1285,7 +1257,7 @@ SetPageTableAttributes ( continue; } =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable= , SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_= PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index3 =3D 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) { @@ -1299,7 +1271,7 @@ SetPageTableAttributes ( continue; } =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTab= le, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EF= I_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted= ); PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index2 =3D 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) { @@ -1313,7 +1285,7 @@ SetPageTableAttributes ( continue; } =20 - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageT= able, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (= EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitt= ed); PageTableSplitted =3D (PageTableSplitted || IsSplitted); } } --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92338): https://edk2.groups.io/g/devel/message/92338 Mute This Topic: https://groups.io/mt/92952030/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-