From nobody Mon Feb 9 12:24:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92262+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92262+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660092517; cv=none; d=zohomail.com; s=zohoarc; b=lFLA3GfYxBTD7p4uxLoGbkdJDJsl7bwQ5aCEemaTh3YgxoRPNh5q+q+5VgYbNuQ4h/m8PtQ4Yx0iJfkKXc9CCN4cO5OD5i4eLH7lFs0tgD4qSliX8aOGAVzJOL02UMBhYaELpRvf1IQAH5fZEW05iOS5yP8evXMxbvQ484ptxKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660092517; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xc2TgrlsqrkgM7j3cboCdiJ7kzuzCB4Q756RV3Zu0us=; b=L4v1pAjSk3g03xG4OQxrcpHvpDVCxQtcnvzZfvTuuLeOqyBFki59vRJzPvh2Ja28R+SEKObkwnTKMD3gSjw0jcZWKn9OkN39ONZTqIGGnSWKaJg7anvQk2ZL0EoCorN9LZQ9errTdPl3eUWrRnU1oGK37YTPuExfpFa010uNeZU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92262+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166009251775324.804529641884073; Tue, 9 Aug 2022 17:48:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id u0geYY1788612xJksk5rDS7W; Tue, 09 Aug 2022 17:48:37 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web08.510.1660092515070874926 for ; Tue, 09 Aug 2022 17:48:35 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10434"; a="377257848" X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="377257848" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 17:48:35 -0700 X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="555542634" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.212.149.229]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 17:48:34 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v2 4/4] IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers. Date: Tue, 9 Aug 2022 17:48:22 -0700 Message-Id: <20220810004822.1499-5-chasel.chiu@intel.com> In-Reply-To: <20220810004822.1499-1-chasel.chiu@intel.com> References: <20220810004822.1499-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: 1RyU5tTX26SqgylML4HshyqMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660092517; bh=7a7Fm0g8FU7q92r3DbEK9QKuqL7kGEoXlj2V0wrUxtQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ACpuGG61aLL5EEK8xCZ7v7xOD9yP3asjwnOZRPIbLwOTtgNbUJFy3FTQSDH8oRPRLHA pA9jJ4YShVlfAwCmFzhuc8+mtLakVoA8g7uGKO4yOi0vnzA949xVsL+RrIDuTBRrMsQvS M9yegoXQllmKo9yqS1WiblkZb1chXwwKig4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660092518612100007 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Implement MultiPhase wrapper handlers and only call to MultiPhase handlers when FSP supports. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 33 +++++++++++++= ++++++++++++-------- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 27 +++++++++++++= ++++++++------ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- 4 files changed, 49 insertions(+), 15 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelF= sp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c index ac27524d08..ea206a7960 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include =20 @@ -35,6 +36,8 @@ #include #include #include +#include +#include =20 extern EFI_GUID gFspHobGuid; =20 @@ -119,25 +122,39 @@ PeiFspMemoryInit ( =20 TimeStampCounterStart =3D AsmReadTsc (); Status =3D CallFspMemoryInit (FspmUpdDataPtr, &FspHobList= Ptr); - // Create hobs after memory initialization and not in temp RAM. Hence pa= ssing the recorded timestamp here - PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCount= erStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_ST= ATUS_CODE_API_ENTRY); - PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); - DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d mil= lisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCount= erStart), 1000000))); =20 // // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { - DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status)= ); + DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset %r\n", Status)); CallFspWrapperResetSystem (Status); } =20 - if (EFI_ERROR (Status)) { + if ((Status !=3D FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspMemoryInitApi(), St= atus =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); } =20 - DEBUG ((DEBUG_INFO, "FspMemoryInit status: 0x%x\n", Status)); - ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "FspMemoryInit status: %r\n", Status)); + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) { + // + // call to Variable request handler + // + FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseMemInit= ApiIndex); + } + + // + // See if MultiPhase process is required or not + // + FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseMemInitApiInde= x); // FspM MultiPhase + + // + // Create hobs after memory initialization and not in temp RAM. Hence pa= ssing the recorded timestamp here + // + PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCount= erStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_ST= ATUS_CODE_API_ENTRY); + PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); + DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d mil= lisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCount= erStart), 1000000))); =20 Status =3D TestFspMemoryInitApiOutput (FspmUpdDataPtr, &FspHobListPtr); if (EFI_ERROR (Status)) { diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelF= sp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index ee48dd69d3..091ddb697a 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include #include +#include =20 extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc; extern EFI_GUID gFspHobGuid; @@ -318,23 +320,36 @@ PeiMemoryDiscoveredNotify ( TimeStampCounterStart =3D AsmReadTsc (); PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_= CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY= ); Status =3D CallFspSiliconInit ((VOID *)FspsUpdDataPtr); - PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); - DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d mi= llisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCoun= terStart), 1000000))); =20 // // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { - DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status= )); + DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset %r\n", Status)); CallFspWrapperResetSystem (Status); } =20 - if (EFI_ERROR (Status)) { + if ((Status !=3D FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspSiliconInitApi(), S= tatus =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); } =20 - DEBUG ((DEBUG_INFO, "FspSiliconInit status: 0x%x\n", Status)); - ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status)); + + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) { + // + // call to Variable request handler + // + FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseSiInitA= piIndex); + } + + // + // See if MultiPhase process is required or not + // + FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseSiInitApiIndex= ); // FspS MultiPhase + + PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); + DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d mi= llisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCoun= terStart), 1000000))); =20 Status =3D TestFspSiliconInitApiOutput ((VOID *)NULL); if (RETURN_ERROR (Status)) { diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/Inte= lFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf index e2262d693c..332509e0bc 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf @@ -46,6 +46,7 @@ FspWrapperApiLib FspWrapperApiTestLib FspMeasurementLib + FspWrapperMultiPhaseProcessLib =20 [Packages] MdePkg/MdePkg.dec diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/Inte= lFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf index 0598f85ab3..f9c2ffca1c 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf @@ -6,7 +6,7 @@ # register TemporaryRamDonePpi to call TempRamExit API, and register Memor= yDiscoveredPpi # notify to call FspSiliconInit API. # -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -46,6 +46,7 @@ FspWrapperApiLib FspWrapperApiTestLib FspMeasurementLib + FspWrapperMultiPhaseProcessLib =20 [Packages] MdePkg/MdePkg.dec --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92262): https://edk2.groups.io/g/devel/message/92262 Mute This Topic: https://groups.io/mt/92928034/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-