From nobody Sun Feb 8 22:07:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92260+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92260+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660092516; cv=none; d=zohomail.com; s=zohoarc; b=j6eDdxiON728XPNQYiFDvw2IP95gF4Ukgj/weGpVx0O6WnlAdtbQy87q0LPLg482Hfgx2ToMcOWxP7X+/EIn9PbjyhvYvT09I0wVoqxmy/sgKZ2gbB5jsIbKXOf4r14Y0C2WKgTzhJST1wHqKNxoAlWtqGdNjkidSU3Th/x3cmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660092516; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=u2zJ3IPiusww4jTuNHZ2owDz/K6Cggn4or2hxVhJ9B4=; b=KC6H8qWg65xz1G3hhFKfNIrJA4mn1WEFapOHa3zZQnLQ9Uwu1NGlOoIBMh2vo7xBg05zwNIbFyRTPeWk2Bl1AxBPPx5afTefz6qT/QIpJT6Wgrqk4BA64k1+0wMdOf0zK8htlKk2KIPK4p6eYc+VTBDEFnc+SK4qMiVBkr0Yw1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92260+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1660092516680271.6537706932304; Tue, 9 Aug 2022 17:48:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ozOzYY1788612xFZhkDnE3jt; Tue, 09 Aug 2022 17:48:36 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web08.510.1660092515070874926 for ; Tue, 09 Aug 2022 17:48:35 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10434"; a="377257842" X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="377257842" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 17:48:34 -0700 X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="555542623" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.212.149.229]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 17:48:34 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v2 1/4] IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface. Date: Tue, 9 Aug 2022 17:48:19 -0700 Message-Id: <20220810004822.1499-2-chasel.chiu@intel.com> In-Reply-To: <20220810004822.1499-1-chasel.chiu@intel.com> References: <20220810004822.1499-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: EsIR6oiUAyDe8KngtMD13tVFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660092516; bh=Z7L2Zmvgz9eLkby3/fLlqpm/jyd5gpM+RANPvHBLanM=; h=Cc:Date:From:Reply-To:Subject:To; b=pRWm/t0PZPjMeznVen6Js3Ek//oMg4RVoYR9iJX/E2CpbAmmEhr8Q+vgtEcGKLl8wvN ZRMG7YEBPaHhQxGrWvgKsv/twI+VsFQFUmrWhBX1NA5q4EIAMyUr8EkBY7wnVTjV38moZ woHQY9w/c8bPWlyFcGgFr7djENjf77z5tvA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660092518624100008 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Provide FSP 2.4 MultiPhase interface and scripts support. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c | 184 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++ IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c | 30 += +++++++++++++++++++++++++++++ IntelFsp2Pkg/Include/FspEas/FspApi.h | 62 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- IntelFsp2Pkg/Include/FspGlobalData.h | 5 += +++- IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h | 54 += +++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h | 19 += ++++++++++++++++++ IntelFsp2Pkg/IntelFsp2Pkg.dec | 12 += +++++++++-- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 4 += +++ IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf | 50 += +++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/Tools/SplitFspBin.py | 48 += ++++++++++++++++++++++++----------------------- 10 files changed, 440 insertions(+), 28 deletions(-) diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c b= /IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c new file mode 100644 index 0000000000..1ab355085b --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c @@ -0,0 +1,184 @@ +/** @file + Null instance of Platform Sec Lib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +FspMultiPhaseSwitchStack ( + ) +{ + SetFspApiReturnStatus (EFI_SUCCESS); + Pei2LoaderSwitchStack (); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FspVariableRequestSwitchStack ( + IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPara= ms + ) +{ + FSP_GLOBAL_DATA *FspData; + + FspData =3D GetFspGlobalDataPointer (); + if (((UINTN)FspData =3D=3D 0) || ((UINTN)FspData =3D=3D 0xFFFFFFFF)) { + return EFI_UNSUPPORTED; + } + + FspData->VariableRequestParameterPtr =3D (VOID *)FspVariableRequestParam= s; + SetFspApiReturnStatus (FSP_STATUS_VARIABLE_REQUEST); + Pei2LoaderSwitchStack (); + + return EFI_SUCCESS; +} + +/** + This function supports FspMultiPhase implementation. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseWorker ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + FSP_MULTI_PHASE_PARAMS *FspMultiPhaseParams; + FSP_GLOBAL_DATA *FspData; + FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS *FspMultiPhaseGetNumber; + BOOLEAN FspDataValid; + UINT32 NumberOfPhasesSupported; + + FspDataValid =3D TRUE; + FspData =3D GetFspGlobalDataPointer (); + if (((UINTN)FspData =3D=3D 0) || ((UINTN)FspData =3D=3D 0xFFFFFFFF)) { + FspDataValid =3D FALSE; + } + + // + // It is required that FspData->NumberOfPhases to be reset to 0 after + // current FSP component finished. + // The next component FspData->NumberOfPhases will only be re-initialize= d when FspData->NumberOfPhases =3D 0 + // + if ((FspDataValid =3D=3D TRUE) && (FspData->NumberOfPhases =3D=3D 0)) { + FspData->NumberOfPhases =3D PcdGet32 (PcdMultiPhaseNumberOfPhases); + FspData->PhasesExecuted =3D 0; + if (FspMultiPhasePlatformGetNumberOfPhases (ApiIdx, &NumberOfPhasesSup= ported) =3D=3D TRUE) { + // + // Platform has implemented runtime controling for NumberOfPhasesSup= ported + // + FspData->NumberOfPhases =3D NumberOfPhasesSupported; + } + } + + FspMultiPhaseParams =3D (FSP_MULTI_PHASE_PARAMS *)ApiParam; + + if (FspDataValid =3D=3D FALSE) { + return EFI_DEVICE_ERROR; + } else { + switch (FspMultiPhaseParams->MultiPhaseAction) { + case EnumMultiPhaseGetNumberOfPhases: + if ((FspMultiPhaseParams->MultiPhaseParamPtr =3D=3D NULL) || (FspM= ultiPhaseParams->PhaseIndex !=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + FspMultiPhaseGetNumber =3D (FSP_MULTI_PHASE_GET_NU= MBER_OF_PHASES_PARAMS *)FspMultiPhaseParams->MultiPhaseParamPtr; + FspMultiPhaseGetNumber->NumberOfPhases =3D FspData->NumberOfPhases; + FspMultiPhaseGetNumber->PhasesExecuted =3D FspData->PhasesExecuted; + break; + + case EnumMultiPhaseExecutePhase: + if ((FspMultiPhaseParams->PhaseIndex > FspData->PhasesExecuted) &&= (FspMultiPhaseParams->PhaseIndex <=3D FspData->NumberOfPhases)) { + FspData->PhasesExecuted =3D FspMultiPhaseParams->PhaseIndex; + return Loader2PeiSwitchStack (); + } else { + return EFI_INVALID_PARAMETER; + } + + break; + + case EnumMultiPhaseGetVariableRequestInfo: + // + // return variable request info + // + FspMultiPhaseParams->MultiPhaseParamPtr =3D FspData->VariableReque= stParameterPtr; + break; + + case EnumMultiPhaseCompleteVariableRequest: + // + // retrieve complete variable request params + // + FspData->VariableRequestParameterPtr =3D FspMultiPhaseParams->Mult= iPhaseParamPtr; + return Loader2PeiSwitchStack (); + break; + + default: + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + This function handles FspMultiPhaseMemInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseMemInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + return FspMultiPhaseWorker (ApiIdx, ApiParam); +} + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandlerV2 ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + return FspMultiPhaseWorker (ApiIdx, ApiParam); +} diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNu= ll.c b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c index a6f3892ed8..27b2e75d1d 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c @@ -28,6 +28,7 @@ FspUpdSignatureCheck ( =20 /** This function handles FspMultiPhaseSiInitApi. + Starting from FSP 2.4 this funciton is obsolete and FspMultiPhaseSiInitA= piHandlerV2 is the replacement. =20 @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. @@ -42,3 +43,32 @@ FspMultiPhaseSiInitApiHandler ( { return EFI_SUCCESS; } + +/** + FSP MultiPhase Platform cnotrol function. + Certain phases may depend on feature enabling or disabling which will be= controlled by Platform. + + @param[in] ApiIdx - Internal index of the FSP API. + @param[in] NumberOfPhasesSupported - How many phases are supported by cu= rrent FSP Component. + + @retval TRUE - NumberOfPhases are modified by Platform during runtime. + @retval FALSE - The Default build time NumberOfPhases should be used. + +**/ +BOOLEAN +EFIAPI +FspMultiPhasePlatformGetNumberOfPhases ( + IN UINT8 ApiIdx, + IN OUT UINT32 *NumberOfPhasesSupported + ) +{ + /* Example for platform runtime controling + if ((ApiIdx =3D=3D FspMultiPhaseSiInitApiIndex) && (Feature1Enable =3D= =3D FALSE)) { + *NumberOfPhasesSupported =3D 0; + return TRUE; + } + return FALSE + */ + + return FALSE; +} diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 361e916b5f..af42d7f707 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -487,10 +487,38 @@ typedef struct { /// Action definition for FspMultiPhaseSiInit API /// typedef enum { - EnumMultiPhaseGetNumberOfPhases =3D 0x0, - EnumMultiPhaseExecutePhase =3D 0x1 + EnumMultiPhaseGetNumberOfPhases =3D 0x0, + EnumMultiPhaseExecutePhase =3D 0x1, + EnumMultiPhaseGetVariableRequestInfo =3D 0x2, + EnumMultiPhaseCompleteVariableRequest =3D 0x3 } FSP_MULTI_PHASE_ACTION; =20 +typedef enum { + EnumFspVariableRequestGetVariable =3D 0x0, + EnumFspVariableRequestGetNextVariableName =3D 0x1, + EnumFspVariableRequestSetVariable =3D 0x2, + EnumFspVariableRequestQueryVariableInfo =3D 0x3 +} FSP_VARIABLE_REQUEST_TYPE; + +#pragma pack(16) +typedef struct { + IN FSP_VARIABLE_REQUEST_TYPE VariableRequest; + IN OUT CHAR16 *VariableName; + IN OUT UINT64 *VariableNameSize; + IN OUT EFI_GUID *VariableGuid; + IN OUT UINT32 *Attributes; + IN OUT UINT64 *DataSize; + IN OUT VOID *Data; + OUT UINT64 *MaximumVariableStorageSize; + OUT UINT64 *RemainingVariableStorageSize; + OUT UINT64 *MaximumVariableSize; +} FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS; + +typedef struct { + EFI_STATUS VariableRequestStatus; +} FSP_MULTI_PHASE_COMPLETE_VARIABLE_REQUEST_PARAMS; +#pragma pack() + /// /// Data structure returned by FSP when bootloader calling /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) @@ -690,4 +718,34 @@ EFI_STATUS IN VOID *FspiUpdDataPtr ); =20 +/** + This FSP API provides multi-phase memory and silicon initialization, whi= ch brings greater modularity to the existing + FspMemoryInit() and FspSiliconInit() API. Increased modularity is achiev= ed by adding an extra API to FSP-M and FSP-S. + This allows the bootloader to add board specific initialization steps th= roughout the MemoryInit and SiliconInit flows as needed. + The FspMemoryInit() API is always called before FspMultiPhaseMemInit(); = it is the first phase of memory initialization. Similarly, + the FspSiliconInit() API is always called before FspMultiPhaseSiInit(); = it is the first phase of silicon initialization. + After the first phase, subsequent phases are invoked by calling the FspM= ultiPhaseMem/SiInit() API. + The FspMultiPhaseMemInit() API may only be called after the FspMemoryIni= t() API and before the FspSiliconInit() API; + or in the case that FSP-T is being used, before the TempRamExit() API. T= he FspMultiPhaseSiInit() API may only be called after + the FspSiliconInit() API and before NotifyPhase() API; or in the case th= at FSP-I is being used, before the FspSmmInit() API. + The multi-phase APIs may not be called at any other time. + + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNu= mberOfPhases: + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr will contain + how many phases supported by F= SP. + For action - EnumMultiPhaseExecu= tePhase: + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr shall be NULL. + @retval EFI_SUCCESS FSP execution environment was in= itialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were = not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIRED_* A reset is required. These statu= s codes will not be returned during S3. + @retval FSP_STATUS_VARIABLE_REQUEST A variable request has been made= by FSP that needs boot loader handling. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MULTI_PHASE_INIT)( + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseInitParamPtr + ); + #endif diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 32c6d460e4..81813df3ce 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -12,7 +12,7 @@ =20 #define FSP_IN_API_MODE 0 #define FSP_IN_DISPATCH_MODE 1 -#define FSP_GLOBAL_DATA_VERSION 0x2 +#define FSP_GLOBAL_DATA_VERSION 0x3 =20 #pragma pack(1) =20 @@ -25,6 +25,7 @@ typedef enum { FspSiliconInitApiIndex, FspMultiPhaseSiInitApiIndex, FspSmmInitApiIndex, + FspMultiPhaseMemInitApiIndex, FspApiIndexMax } FSP_API_INDEX; =20 @@ -82,6 +83,8 @@ typedef struct { VOID *FunctionParameterPtr; FSP_INFO_HEADER *FspInfoHeader; VOID *UpdDataPtr; + VOID *FspHobListPtr; + VOID *VariableRequestParameterPtr; /// /// End of UINTN and pointer section /// At this point, next field offset must be either *0h or *8h to diff --git a/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h b/IntelFsp2Pkg= /Include/Library/FspMultiPhaseLib.h new file mode 100644 index 0000000000..7ac4e197d9 --- /dev/null +++ b/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h @@ -0,0 +1,54 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_SEC_PLATFORM_LIB_H_ +#define _FSP_SEC_PLATFORM_LIB_H_ + +EFI_STATUS +EFIAPI +FspMultiPhaseSwitchStack ( + ); + +EFI_STATUS +EFIAPI +FspVariableRequestSwitchStack ( + IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPara= ms + ); + +/** + This function handles FspMultiPhaseMemInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseMemInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandlerV2 ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +#endif diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/IntelFsp2Pk= g/Include/Library/FspSecPlatformLib.h index 920115e90e..236ce804c5 100644 --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -81,6 +81,7 @@ FspUpdSignatureCheck ( =20 /** This function handles FspMultiPhaseSiInitApi. + Starting from FSP 2.4 this funciton is obsolete and FspMultiPhaseSiInitA= piHandlerV2 is the replacement. =20 @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. @@ -93,4 +94,22 @@ FspMultiPhaseSiInitApiHandler ( IN VOID *ApiParam ); =20 +/** + FSP MultiPhase Platform cnotrol function. + Certain phases may depend on feature enabling or disabling which will be= controlled by Platform. + + @param[in] ApiIdx - Internal index of the FSP API. + @param[in] NumberOfPhasesSupported - How many phases are supported by cu= rrent FSP Component. + + @retval TRUE - NumberOfPhases are modified by Platform during runtime. + @retval FALSE - The Default build time NumberOfPhases should be used. + +**/ +BOOLEAN +EFIAPI +FspMultiPhasePlatformGetNumberOfPhases ( + IN UINTN ApiIdx, + IN OUT UINT32 *NumberOfPhasesSupported + ); + #endif diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 2d3eb708b9..d1c3d3ee7b 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -37,6 +37,9 @@ ## @libraryclass Provides FSP platform sec related actions. FspSecPlatformLib|Include/Library/FspSecPlatformLib.h =20 + ## @libraryclass Provides FSP MultiPhase service functions. + FspMultiPhaseLib|Include/Library/FspMultiPhaseLib.h + [Ppis] # # PPI to indicate FSP is ready to enter notify phase @@ -112,5 +115,10 @@ gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UI= NT32|0x10000006 =20 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx] - gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT3= 2|0x46530000 - gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT3= 2|0x46530100 + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT= 32|0x46530000 + gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT= 32|0x46530100 + # + # Different FSP Components may have different NumberOfPhases which can b= e defined + # by each FspSecCore module from DSC. + # + gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases |0x00000000|UINT= 32|0x46530101 diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index b2d7867880..0713f0028d 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -45,6 +45,7 @@ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSe= cPlatformLibNull.inf + FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiP= haseLib.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf @@ -64,12 +65,15 @@ IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.i= nf + IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf =20 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf + IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf + IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf =20 [PcdsFixedAtBuild.common] diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib= .inf b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf new file mode 100644 index 0000000000..a79f6aecda --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf @@ -0,0 +1,50 @@ +## @file +# FSP MultiPhase Lib. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseFspMultiPhaseLib + FILE_GUID =3D C128CADC-623E-4E41-97CB-A7138E627460 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspMultiPhaseLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspMultiPhaseLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + +[Pcd] + gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases # CONSUMES diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFs= pBin.py index ddabab7d8c..419e5ba985 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -103,29 +103,31 @@ class FSP_COMMON_HEADER(Structure): =20 class FSP_INFORMATION_HEADER(Structure): _fields_ =3D [ - ('Signature', ARRAY(c_char, 4)), - ('HeaderLength', c_uint32), - ('Reserved1', c_uint16), - ('SpecVersion', c_uint8), - ('HeaderRevision', c_uint8), - ('ImageRevision', c_uint32), - ('ImageId', ARRAY(c_char, 8)), - ('ImageSize', c_uint32), - ('ImageBase', c_uint32), - ('ImageAttribute', c_uint16), - ('ComponentAttribute', c_uint16), - ('CfgRegionOffset', c_uint32), - ('CfgRegionSize', c_uint32), - ('Reserved2', c_uint32), - ('TempRamInitEntryOffset', c_uint32), - ('Reserved3', c_uint32), - ('NotifyPhaseEntryOffset', c_uint32), - ('FspMemoryInitEntryOffset', c_uint32), - ('TempRamExitEntryOffset', c_uint32), - ('FspSiliconInitEntryOffset', c_uint32), - ('FspMultiPhaseSiInitEntryOffset', c_uint32), - ('ExtendedImageRevision', c_uint16), - ('Reserved4', c_uint16) + ('Signature', ARRAY(c_char, 4)), + ('HeaderLength', c_uint32), + ('Reserved1', c_uint16), + ('SpecVersion', c_uint8), + ('HeaderRevision', c_uint8), + ('ImageRevision', c_uint32), + ('ImageId', ARRAY(c_char, 8)), + ('ImageSize', c_uint32), + ('ImageBase', c_uint32), + ('ImageAttribute', c_uint16), + ('ComponentAttribute', c_uint16), + ('CfgRegionOffset', c_uint32), + ('CfgRegionSize', c_uint32), + ('Reserved2', c_uint32), + ('TempRamInitEntryOffset', c_uint32), + ('Reserved3', c_uint32), + ('NotifyPhaseEntryOffset', c_uint32), + ('FspMemoryInitEntryOffset', c_uint32), + ('TempRamExitEntryOffset', c_uint32), + ('FspSiliconInitEntryOffset', c_uint32), + ('FspMultiPhaseSiInitEntryOffset', c_uint32), + ('ExtendedImageRevision', c_uint16), + ('Reserved4', c_uint16), + ('FspMultiPhaseMemInitEntryOffset', c_uint32), + ('FspSmmInitEntryOffset', c_uint32) ] =20 class FSP_PATCH_TABLE(Structure): --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92260): https://edk2.groups.io/g/devel/message/92260 Mute This Topic: https://groups.io/mt/92928032/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-