From nobody Mon May 6 00:18:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92227+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92227+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660008372; cv=none; d=zohomail.com; s=zohoarc; b=fuk5E9JmDn2wVw1EecaCv4ulfGAR03SQOqJLn1ED2wDg0ZoB9DDI0y8bkFjosu9CNGG0MX8MIUYZ1B2axjMU8DZRtuh474f0vd6uApyqG8mPUo60xnb/tvPtC2XYGR2wh2gdGCE3Bp3vbWgnVedKza+WheTCp4Evj5hX33j1cKw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660008372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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d="scan'208";a="377020601" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 18:26:10 -0700 X-IronPort-AV: E=Sophos;i="5.93,223,1654585200"; d="scan'208";a="932291957" X-Received: from unknown (HELO shwdesfp01.ccr.corp.intel.com) ([10.239.158.151]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 18:26:07 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Dandan Bi , Liming Gao , Jian J Wang , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v3 1/3] UefiCpuPkg: Simplify InitializeSeparateExceptionStacks Date: Tue, 9 Aug 2022 09:25:35 +0800 Message-Id: <20220809012537.1513-2-zhiguang.liu@intel.com> In-Reply-To: <20220809012537.1513-1-zhiguang.liu@intel.com> References: <20220809012537.1513-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: 2azYe9pFtvNhOirjFUu8A0Rtx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660008370; bh=bkIuo5S8Vt4+3vPMa95csiBnhjTCxHN2jI5wGkKCqck=; h=Cc:Date:From:Reply-To:Subject:To; b=IoVu7FerYR60aS9rKA5rmm9pf4jFKZCl4QE6EW0+AOeBv/128RV1bZFRGFfi7vOHE+u +LNyJO5GzkYdx+5TH1YqJNCCEO/KGrPwe4/0mvfHiwMYenOYcBEBvE5MLotRe+Cjxq1NC x5j96Lr0dUtcELoHaaokCnG+q13SQ4sULUQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660008372640100005 Content-Type: text/plain; charset="utf-8" Hide the Exception implementation details in CpuExcetionHandlerLib and caller only need to provide buffer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Dandan Bi Cc: Liming Gao Cc: Jian J Wang Cc: Ard Biesheuvel Reviewed-by: Sami Mujawar Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- .../Library/ArmExceptionLib/ArmExceptionLib.c | 15 +- MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 4 +- .../Include/Library/CpuExceptionHandlerLib.h | 15 +- .../CpuExceptionHandlerLibNull.c | 15 +- UefiCpuPkg/CpuDxe/CpuMp.c | 162 ++++------------ UefiCpuPkg/CpuMpPei/CpuMpPei.c | 176 ++++-------------- .../CpuExceptionHandlerLib/DxeException.c | 113 ++++++++--- .../CpuExceptionHandlerLib/PeiCpuException.c | 95 +++++++++- .../PeiCpuExceptionHandlerLib.inf | 4 +- .../SecPeiCpuException.c | 15 +- .../CpuExceptionHandlerLib/SmmException.c | 15 +- 11 files changed, 289 insertions(+), 340 deletions(-) diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c b/ArmPkg/Libr= ary/ArmExceptionLib/ArmExceptionLib.c index 2c7bc66aa7..a521c33f32 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c @@ -288,20 +288,23 @@ CommonCExceptionHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_SUCCESS; diff --git a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c b/MdeModulePkg/Core/Dx= e/DxeMain/DxeMain.c index 0a1f3d79e2..5733f0c8ec 100644 --- a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c +++ b/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c @@ -1,7 +1,7 @@ /** @file DXE Core Main Entry Point =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -260,7 +260,7 @@ DxeMain ( // Setup Stack Guard // if (PcdGetBool (PcdCpuStackGuard)) { - Status =3D InitializeSeparateExceptionStacks (NULL); + Status =3D InitializeSeparateExceptionStacks (NULL, NULL); ASSERT_EFI_ERROR (Status); } =20 diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 9a495081f7..8d44ed916a 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -104,20 +104,23 @@ InitializeCpuExceptionHandlers ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ); =20 /** diff --git a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHa= ndlerLibNull.c b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExcepti= onHandlerLibNull.c index 8aeedcb4d1..74908a379b 100644 --- a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi= bNull.c +++ b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi= bNull.c @@ -83,20 +83,23 @@ DumpCpuContext ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c index e385f585c7..f3ca813d2a 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.c +++ b/UefiCpuPkg/CpuDxe/CpuMp.c @@ -596,23 +596,13 @@ CollectBistDataFromHob ( } } =20 -/** - Get GDT register value. - - This function is mainly for AP purpose because AP may have different GDT - table than BSP. - - @param[in,out] Buffer The pointer to private data buffer. - -**/ -VOID -EFIAPI -GetGdtr ( - IN OUT VOID *Buffer - ) -{ - AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); -} +// +// Structure for InitializeSeparateExceptionStacks +// +typedef struct { + VOID *Buffer; + UINTN *BufferSize; +} EXCEPTION_STACK_SWITCH_CONTEXT; =20 /** Initializes CPU exceptions handlers for the sake of stack switch require= ment. @@ -629,27 +619,17 @@ InitializeExceptionStackSwitchHandlers ( IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + EXCEPTION_STACK_SWITCH_CONTEXT *SwitchStackData; =20 - EssData =3D Buffer; - // - // We don't plan to replace IDT table with a new one, but we should not = assume - // the AP's IDT is the same as BSP's IDT either. - // - AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable =3D (VOID *)Idtr.Base; - EssData->Ia32.IdtTableSize =3D Idtr.Limit + 1; - Status =3D InitializeSeparateExceptionStacks (EssDat= a); - ASSERT_EFI_ERROR (Status); + SwitchStackData =3D (EXCEPTION_STACK_SWITCH_CONTEXT *)Buffer; + InitializeSeparateExceptionStacks (SwitchStackData->Buffer, SwitchStackD= ata->BufferSize); } =20 /** Initializes MP exceptions handlers for the sake of stack switch requirem= ent. =20 This function will allocate required resources required to setup stack s= witch - and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor. + and pass them through SwitchStackData to each logic processor. =20 **/ VOID @@ -657,129 +637,53 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - - ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * Exception= Number; - - StackTop =3D AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors= ); - ASSERT (StackTop !=3D NULL); - StackTop +=3D NewStackSize * mNumberOfProcessors; - - // - // The default exception handlers must have been initialized. Let's just= skip - // it in this method. - // - EssData.Ia32.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.Ia32.InitDefaultHandlers =3D FALSE; - - EssData.Ia32.StackSwitchExceptions =3D FixedPcdGetPtr (PcdCpuStackS= witchExceptionList); - EssData.Ia32.StackSwitchExceptionNumber =3D ExceptionNumber; - EssData.Ia32.KnownGoodStackSize =3D FixedPcdGet32 (PcdCpuKnownGo= odStackSize); + UINTN Index; + UINTN Bsp; + EXCEPTION_STACK_SWITCH_CONTEXT SwitchStackData; + UINTN BufferSize; =20 - // - // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. - // - Gdtr.Base =3D 0; - Gdtr.Limit =3D 0; + SwitchStackData.BufferSize =3D &BufferSize; MpInitLibWhoAmI (&Bsp); + for (Index =3D 0; Index < mNumberOfProcessors; ++Index) { - // - // To support stack switch, we need to re-construct GDT but not IDT. - // + SwitchStackData.Buffer =3D NULL; + BufferSize =3D 0; + if (Index =3D=3D Bsp) { - GetGdtr (&Gdtr); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { // - // AP might have different size of GDT from BSP. + // AP might need different buffer size from BSP. // - MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); + MpInitLibStartupThisAP (InitializeExceptionStackSwitchHandlers, Inde= x, NULL, 0, (VOID *)&SwitchStackData, NULL); } =20 - // - // X64 needs only one TSS of current task working for all exceptions - // because of its IST feature. IA32 needs one TSS for each exception - // in addition to current task. Since AP is not supposed to allocate - // memory, we have to do it in BSP. To simplify the code, we allocate - // memory for IA32 case to cover both IA32 and X64 exception stack - // switch. - // - // Layout of memory to allocate for each processor: - // -------------------------------- - // | Alignment | (just in case) - // -------------------------------- - // | | - // | Original GDT | - // | | - // -------------------------------- - // | Current task descriptor | - // -------------------------------- - // | | - // | Exception task descriptors | X ExceptionNumber - // | | - // -------------------------------- - // | Current task-state segment | - // -------------------------------- - // | | - // | Exception task-state segment | X ExceptionNumber - // | | - // -------------------------------- - // - OldGdtSize =3D Gdtr.Limit + 1; - EssData.Ia32.ExceptionTssDescSize =3D sizeof (IA32_TSS_DESCRIPTOR) * - (ExceptionNumber + 1); - EssData.Ia32.ExceptionTssSize =3D sizeof (IA32_TASK_STATE_SEGMENT) * - (ExceptionNumber + 1); - NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + - OldGdtSize + - EssData.Ia32.ExceptionTssDescSize + - EssData.Ia32.ExceptionTssSize; - - GdtBuffer =3D AllocateRuntimeZeroPool (NewGdtSize); - ASSERT (GdtBuffer !=3D NULL); - - // - // Make sure GDT table alignment - // - EssData.Ia32.GdtTable =3D ALIGN_POINTER (GdtBuffer, sizeof (IA32_T= SS_DESCRIPTOR)); - NewGdtSize -=3D ((UINT8 *)EssData.Ia32.GdtTable - GdtBuf= fer); - EssData.Ia32.GdtTableSize =3D NewGdtSize; - - EssData.Ia32.ExceptionTssDesc =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize); - EssData.Ia32.ExceptionTss =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize + - EssData.Ia32.ExceptionTssDescSize); + if (BufferSize =3D=3D 0) { + continue; + } =20 - EssData.Ia32.KnownGoodStackTop =3D (UINTN)StackTop; + SwitchStackData.Buffer =3D AllocateRuntimeZeroPool (BufferSize); + ASSERT (SwitchStackData.Buffer !=3D NULL); DEBUG (( DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", + "Buffer[cpu%lu] for InitializeExceptionStackSwitchHandlers: 0x%lX wi= th size 0x%x\n", (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop + (UINT64)(UINTN)SwitchStackData.Buffer, + (UINT32)BufferSize )); =20 if (Index =3D=3D Bsp) { - InitializeExceptionStackSwitchHandlers (&EssData); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { MpInitLibStartupThisAP ( InitializeExceptionStackSwitchHandlers, Index, NULL, 0, - (VOID *)&EssData, + (VOID *)&SwitchStackData, NULL ); } - - StackTop -=3D NewStackSize; } } =20 diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c index d4786979fa..c0be11d3ad 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.c +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.c @@ -1,7 +1,7 @@ /** @file CPU PEI Module installs CPU Multiple Processor PPI. =20 - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -411,23 +411,13 @@ PeiWhoAmI ( return MpInitLibWhoAmI (ProcessorNumber); } =20 -/** - Get GDT register value. - - This function is mainly for AP purpose because AP may have different GDT - table than BSP. - - @param[in,out] Buffer The pointer to private data buffer. - -**/ -VOID -EFIAPI -GetGdtr ( - IN OUT VOID *Buffer - ) -{ - AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); -} +// +// Structure for InitializeSeparateExceptionStacks +// +typedef struct { + VOID *Buffer; + UINTN *BufferSize; +} EXCEPTION_STACK_SWITCH_CONTEXT; =20 /** Initializes CPU exceptions handlers for the sake of stack switch require= ment. @@ -444,27 +434,17 @@ InitializeExceptionStackSwitchHandlers ( IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + EXCEPTION_STACK_SWITCH_CONTEXT *SwitchStackData; =20 - EssData =3D Buffer; - // - // We don't plan to replace IDT table with a new one, but we should not = assume - // the AP's IDT is the same as BSP's IDT either. - // - AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable =3D (VOID *)Idtr.Base; - EssData->Ia32.IdtTableSize =3D Idtr.Limit + 1; - Status =3D InitializeSeparateExceptionStacks (EssDat= a); - ASSERT_EFI_ERROR (Status); + SwitchStackData =3D (EXCEPTION_STACK_SWITCH_CONTEXT *)Buffer; + InitializeSeparateExceptionStacks (SwitchStackData->Buffer, SwitchStackD= ata->BufferSize); } =20 /** Initializes MP exceptions handlers for the sake of stack switch requirem= ent. =20 This function will allocate required resources required to setup stack s= witch - and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor. + and pass them through SwitchStackData to each logic processor. =20 **/ VOID @@ -472,148 +452,60 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - EFI_STATUS Status; - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - UINTN NumberOfProcessors; + UINTN Index; + UINTN Bsp; + EXCEPTION_STACK_SWITCH_CONTEXT SwitchStackData; + UINTN BufferSize; + UINTN NumberOfProcessors; =20 if (!PcdGetBool (PcdCpuStackGuard)) { return; } =20 + SwitchStackData.BufferSize =3D &BufferSize; MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL); MpInitLibWhoAmI (&Bsp); =20 - ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * Exception= Number; - - StackTop =3D AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfPr= ocessors)); - ASSERT (StackTop !=3D NULL); - if (StackTop =3D=3D NULL) { - return; - } - - StackTop +=3D NewStackSize * NumberOfProcessors; - - // - // The default exception handlers must have been initialized. Let's just= skip - // it in this method. - // - EssData.Ia32.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.Ia32.InitDefaultHandlers =3D FALSE; - - EssData.Ia32.StackSwitchExceptions =3D FixedPcdGetPtr (PcdCpuStackS= witchExceptionList); - EssData.Ia32.StackSwitchExceptionNumber =3D ExceptionNumber; - EssData.Ia32.KnownGoodStackSize =3D FixedPcdGet32 (PcdCpuKnownGo= odStackSize); - - // - // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. - // - Gdtr.Base =3D 0; - Gdtr.Limit =3D 0; for (Index =3D 0; Index < NumberOfProcessors; ++Index) { - // - // To support stack switch, we need to re-construct GDT but not IDT. - // + SwitchStackData.Buffer =3D NULL; + BufferSize =3D 0; + if (Index =3D=3D Bsp) { - GetGdtr (&Gdtr); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { // - // AP might have different size of GDT from BSP. + // AP might need different buffer size from BSP. // - MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); + MpInitLibStartupThisAP (InitializeExceptionStackSwitchHandlers, Inde= x, NULL, 0, (VOID *)&SwitchStackData, NULL); } =20 - // - // X64 needs only one TSS of current task working for all exceptions - // because of its IST feature. IA32 needs one TSS for each exception - // in addition to current task. Since AP is not supposed to allocate - // memory, we have to do it in BSP. To simplify the code, we allocate - // memory for IA32 case to cover both IA32 and X64 exception stack - // switch. - // - // Layout of memory to allocate for each processor: - // -------------------------------- - // | Alignment | (just in case) - // -------------------------------- - // | | - // | Original GDT | - // | | - // -------------------------------- - // | Current task descriptor | - // -------------------------------- - // | | - // | Exception task descriptors | X ExceptionNumber - // | | - // -------------------------------- - // | Current task-state segment | - // -------------------------------- - // | | - // | Exception task-state segment | X ExceptionNumber - // | | - // -------------------------------- - // - OldGdtSize =3D Gdtr.Limit + 1; - EssData.Ia32.ExceptionTssDescSize =3D sizeof (IA32_TSS_DESCRIPTOR) * - (ExceptionNumber + 1); - EssData.Ia32.ExceptionTssSize =3D sizeof (IA32_TASK_STATE_SEGMENT) * - (ExceptionNumber + 1); - NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + - OldGdtSize + - EssData.Ia32.ExceptionTssDescSize + - EssData.Ia32.ExceptionTssSize; - - Status =3D PeiServicesAllocatePool ( - NewGdtSize, - (VOID **)&GdtBuffer - ); - ASSERT (GdtBuffer !=3D NULL); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return; + if (BufferSize =3D=3D 0) { + continue; } =20 - // - // Make sure GDT table alignment - // - EssData.Ia32.GdtTable =3D ALIGN_POINTER (GdtBuffer, sizeof (IA32_T= SS_DESCRIPTOR)); - NewGdtSize -=3D ((UINT8 *)EssData.Ia32.GdtTable - GdtBuf= fer); - EssData.Ia32.GdtTableSize =3D NewGdtSize; - - EssData.Ia32.ExceptionTssDesc =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize); - EssData.Ia32.ExceptionTss =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize + - EssData.Ia32.ExceptionTssDescSize); - - EssData.Ia32.KnownGoodStackTop =3D (UINTN)StackTop; + SwitchStackData.Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (BufferSiz= e)); + ASSERT (SwitchStackData.Buffer !=3D NULL); + ZeroMem (SwitchStackData.Buffer, EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES = (BufferSize))); DEBUG (( DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", + "Buffer[cpu%lu] for InitializeExceptionStackSwitchHandlers: 0x%lX wi= th size 0x%x\n", (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop + (UINT64)(UINTN)SwitchStackData.Buffer, + (UINT32)BufferSize )); =20 if (Index =3D=3D Bsp) { - InitializeExceptionStackSwitchHandlers (&EssData); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { MpInitLibStartupThisAP ( InitializeExceptionStackSwitchHandlers, Index, NULL, 0, - (VOID *)&EssData, + (VOID *)&SwitchStackData, NULL ); } - - StackTop -=3D NewStackSize; } } =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index e62bb5e6c0..04e8409922 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -104,48 +104,105 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { CPU_EXCEPTION_INIT_DATA EssData; IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Gdtr; - - if (InitData =3D=3D NULL) { + UINTN NeedBufferSize; + UINTN StackTop; + UINT8 *NewGdtTable; + + // + // X64 needs only one TSS of current task working for all exceptions + // because of its IST feature. IA32 needs one TSS for each exception + // in addition to current task. To simplify the code, we report the + // needed memory for IA32 case to cover both IA32 and X64 exception + // stack switch. + // + // Layout of memory needed for each processor: + // -------------------------------- + // | Alignment | (just in case) + // -------------------------------- + // | | + // | Original GDT | + // | | + // -------------------------------- + // | Current task descriptor | + // -------------------------------- + // | | + // | Exception task descriptors | X ExceptionNumber + // | | + // -------------------------------- + // | Current task-state segment | + // -------------------------------- + // | | + // | Exception task-state segment | X ExceptionNumber + // | | + // -------------------------------- + // + AsmReadGdtr (&Gdtr); + if ((Buffer =3D=3D NULL) && (BufferSize =3D=3D NULL)) { SetMem (mNewGdt, sizeof (mNewGdt), 0); - - AsmReadIdtr (&Idtr); - AsmReadGdtr (&Gdtr); - - EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.X64.KnownGoodStackTop =3D (UINTN)mNewStack + sizeof (= mNewStack); - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_= LIST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_= NUMBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D mNewGdt; - EssData.X64.GdtTableSize =3D sizeof (mNewGdt); - EssData.X64.ExceptionTssDesc =3D mNewGdt + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D mNewGdt + Gdtr.Limit + 1 + = CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; - - InitData =3D &EssData; + StackTop =3D (UINTN)mNewStack + sizeof (mNewStack); + NewGdtTable =3D mNewGdt; + } else { + if (BufferSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Total needed size includes stack size, new GDT table size, TSS size. + // Add another DESCRIPTOR size for alignment requiremet. + // + NeedBufferSize =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_KNOWN_GOOD_= STACK_SIZE + + CPU_TSS_DESC_SIZE + Gdtr.Limit + 1 + + CPU_TSS_SIZE + + sizeof (IA32_TSS_DESCRIPTOR); + if (*BufferSize < NeedBufferSize) { + *BufferSize =3D NeedBufferSize; + return EFI_BUFFER_TOO_SMALL; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + StackTop =3D (UINTN)Buffer + CPU_STACK_SWITCH_EXCEPTION_NUMBER * CP= U_KNOWN_GOOD_STACK_SIZE; + NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); } =20 - return ArchSetupExceptionStack (InitData); + AsmReadIdtr (&Idtr); + EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; + EssData.X64.KnownGoodStackTop =3D StackTop; + EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; + EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; + EssData.X64.IdtTable =3D (VOID *)Idtr.Base; + EssData.X64.IdtTableSize =3D Idtr.Limit + 1; + EssData.X64.GdtTable =3D NewGdtTable; + EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; + EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + + return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index 494c2ab433..52ec0fb803 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -151,25 +151,104 @@ InitializeCpuExceptionHandlers ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { - if (InitData =3D=3D NULL) { + CPU_EXCEPTION_INIT_DATA EssData; + IA32_DESCRIPTOR Idtr; + IA32_DESCRIPTOR Gdtr; + UINTN NeedBufferSize; + UINTN StackTop; + UINT8 *NewGdtTable; + + // + // X64 needs only one TSS of current task working for all exceptions + // because of its IST feature. IA32 needs one TSS for each exception + // in addition to current task. To simplify the code, we report the + // needed memory for IA32 case to cover both IA32 and X64 exception + // stack switch. + // + // Layout of memory needed for each processor: + // -------------------------------- + // | Alignment | (just in case) + // -------------------------------- + // | | + // | Original GDT | + // | | + // -------------------------------- + // | Current task descriptor | + // -------------------------------- + // | | + // | Exception task descriptors | X ExceptionNumber + // | | + // -------------------------------- + // | Current task-state segment | + // -------------------------------- + // | | + // | Exception task-state segment | X ExceptionNumber + // | | + // -------------------------------- + // + + if ((Buffer =3D=3D NULL) && (BufferSize =3D=3D NULL)) { return EFI_UNSUPPORTED; } =20 - return ArchSetupExceptionStack (InitData); + if (BufferSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + AsmReadGdtr (&Gdtr); + // + // Total needed size includes stack size, new GDT table size, TSS size. + // Add another DESCRIPTOR size for alignment requiremet. + // + NeedBufferSize =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_KNOWN_GOOD_ST= ACK_SIZE + + CPU_TSS_DESC_SIZE + Gdtr.Limit + 1 + + CPU_TSS_SIZE + + sizeof (IA32_TSS_DESCRIPTOR); + if (*BufferSize < NeedBufferSize) { + *BufferSize =3D NeedBufferSize; + return EFI_BUFFER_TOO_SMALL; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + StackTop =3D (UINTN)Buffer + CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_= KNOWN_GOOD_STACK_SIZE; + NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); + + AsmReadIdtr (&Idtr); + EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; + EssData.X64.KnownGoodStackTop =3D StackTop; + EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; + EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; + EssData.X64.IdtTable =3D (VOID *)Idtr.Base; + EssData.X64.IdtTableSize =3D Idtr.Limit + 1; + EssData.X64.GdtTable =3D NewGdtTable; + EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; + EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + + return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index cf5bfe4083..7c2ec3b2db 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -1,7 +1,7 @@ ## @file # CPU Exception Handler library instance for PEI module. # -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -56,6 +56,8 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 4313cc5582..ad5e0e9ed4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -201,20 +201,23 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c index 1c97dab926..46a86ad2c6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c @@ -97,20 +97,23 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92227): https://edk2.groups.io/g/devel/message/92227 Mute This Topic: https://groups.io/mt/92907049/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 00:18:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92228+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92228+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660008373; cv=none; d=zohomail.com; s=zohoarc; b=V0abtzrlaosQ6ZmIpGR4scytOEFEMV+3YJSqN4zwF1yepfhuSFw1HT2VmdZZq0AcMEBnXfyVJBPwNBE4+P8CnqAAvYW4wPu97kGYqY+Yi8YnIlVy+GV9KckMztCvPsu4brcyxFnQ13HSDq4Y3+AvSPVeOaO0RvvFHn4aSMR4Bgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660008373; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Yo8MVZcrZrMu0xFUpOyIsN+SfVXWBA9O/n4XHLD1970=; b=iI7A1BDGltd+3VHg7ksVzffHHnWruFf4LJno8Gk8Fijt5iR8mmtS8boS9VqGq6inRM0lla1ArS7bkETMDIkPupdKcp9hlAxf+7PAhF7ZP+UR7uNdjXUqXvAPNjMCrNXEPCcvAL9Xx4L9R+8UZgHOqWg4NHTKur1bFIOe7pEslXc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92228+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1660008373946721.6552969535023; Mon, 8 Aug 2022 18:26:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AvzMYY1788612x0cOyUkCVhE; Mon, 08 Aug 2022 18:26:13 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.6742.1660008368004129018 for ; Mon, 08 Aug 2022 18:26:12 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10433"; a="377020615" X-IronPort-AV: E=Sophos;i="5.93,223,1654585200"; d="scan'208";a="377020615" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 18:26:12 -0700 X-IronPort-AV: E=Sophos;i="5.93,223,1654585200"; d="scan'208";a="932291965" X-Received: from unknown (HELO shwdesfp01.ccr.corp.intel.com) ([10.239.158.151]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 18:26:10 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Dandan Bi , Liming Gao , Jian J Wang Subject: [edk2-devel] [PATCH v3 2/3] MdeModulePkg: Move CPU_EXCEPTION_INIT_DATA to UefiCpuPkg Date: Tue, 9 Aug 2022 09:25:36 +0800 Message-Id: <20220809012537.1513-3-zhiguang.liu@intel.com> In-Reply-To: <20220809012537.1513-1-zhiguang.liu@intel.com> References: <20220809012537.1513-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: uNIdUMjzjdHrZfVgVVB50vowx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660008373; bh=NkHQx9GrmJxW3uPxIAA51c4TW6d3xqedEIaubyC7CYE=; h=Cc:Date:From:Reply-To:Subject:To; b=rmJ9eJ+/9qJiDixgVwRDyIgw+Sih5eM47BEyVocgZ9xQUrgGfB7yHvvLTHDoYtUPqYL UepGI2KCh3l51KDOtjtyvEfKBwHaxIm1kiw9l7MkjTMQ72Z7ZFOtGo6eJ4YU8zYfHR6rJ 3uV4Sx7RicqyJ43GiMfQftI/tx/vVPeFCdk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660008374610100009 Content-Type: text/plain; charset="utf-8" Since the API InitializeSeparateExceptionStacks is simplified and does't use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become a inner implementation of CpuExcetionHandlerLib. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Dandan Bi Cc: Liming Gao Cc: Jian J Wang Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- .../Include/Library/CpuExceptionHandlerLib.h | 67 ------------------ .../CpuExceptionCommon.h | 69 ++++++++++++++++++- 2 files changed, 68 insertions(+), 68 deletions(-) diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 8d44ed916a..94e9b20ae1 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -13,73 +13,6 @@ #include #include =20 -#define CPU_EXCEPTION_INIT_DATA_REV 1 - -typedef union { - struct { - // - // Revision number of this structure. - // - UINT32 Revision; - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - // - // Flag to indicate if default handlers should be initialized or not. - // - BOOLEAN InitDefaultHandlers; - } Ia32, X64; -} CPU_EXCEPTION_INIT_DATA; - /** Initializes all CPU exceptions entries and provides the default exceptio= n handlers. =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index fd42c4be0f..443eaf359b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -1,7 +1,7 @@ /** @file Common header file for CPU Exception Handler Library. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -49,6 +49,73 @@ =20 #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) =20 +#define CPU_EXCEPTION_INIT_DATA_REV 1 + +typedef union { + struct { + // + // Revision number of this structure. + // + UINT32 Revision; + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; + // + // Flag to indicate if default handlers should be initialized or not. + // + BOOLEAN InitDefaultHandlers; + } Ia32, X64; +} CPU_EXCEPTION_INIT_DATA; + // // Record exception handler information // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92228): https://edk2.groups.io/g/devel/message/92228 Mute This Topic: https://groups.io/mt/92907051/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 00:18:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92229+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92229+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1660008376; cv=none; d=zohomail.com; s=zohoarc; b=RN1CDby/UmYr/DgQqTzH3ROnOWtcVUdzhxzRMjzzxPQPKXe2CbDICiONEa/F9t5a+EbRaZOkZj0JPhcvxvGoyCtUUbPfTjylGee8CpDr1sR+Tev1/g1EfericYkr70nG7OKzUM15/SzZKFpnYu2hOCKRbDvW3bX+EmGKjOPoiyM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660008376; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=UxyukaBMycrK8Trh/J67V8tQQXms7Y5oaA/FO6ysmdc=; b=ZnxV10vQJkOWsSgupTJtm6guMKtTcKX5gAjNg5M2LS7OUPUO1G6CE90h2I+Xelz4dD2GzarETNJNMo6ArSJ6LNx8rpYtcIwuGxQjEdPktUMGqszOJvepiJl0idHBL5PNDRvN+XnUN9thyrEfv2PYzhqLmsc5IFm+Tgb10OSZJvQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92229+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1660008376161142.0504166120054; Mon, 8 Aug 2022 18:26:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RvbLYY1788612xGzU9gitgR9; Mon, 08 Aug 2022 18:26:14 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.6742.1660008368004129018 for ; Mon, 08 Aug 2022 18:26:14 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10433"; a="377020618" X-IronPort-AV: E=Sophos;i="5.93,223,1654585200"; d="scan'208";a="377020618" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 18:26:14 -0700 X-IronPort-AV: E=Sophos;i="5.93,223,1654585200"; d="scan'208";a="932291973" X-Received: from unknown (HELO shwdesfp01.ccr.corp.intel.com) ([10.239.158.151]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 18:26:12 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH v3 3/3] UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA Date: Tue, 9 Aug 2022 09:25:37 +0800 Message-Id: <20220809012537.1513-4-zhiguang.liu@intel.com> In-Reply-To: <20220809012537.1513-1-zhiguang.liu@intel.com> References: <20220809012537.1513-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: ww6Cj1NRYmiJtK3EtJeUfASkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1660008374; bh=Wsy6UKasgvhUAn/HIe7B74QqM3gKQ8J5+cIIgdwQ+8I=; h=Cc:Date:From:Reply-To:Subject:To; b=RULu+fEBdrFAllozGL5AwSNxlxNiPa9Mhtx0KleQGXYLNbeoJn+hglwXhVkouhNL4BV 5cMtAEmMM6ddowDW9o6HcS8vr0aLiftf5hfsQNRuQU4yrC9SaDmmrRZPmhD9+HVGZs+uf QRB7o2BkynB9TLUeWSDd3epirBe54rPg43g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1660008376660100013 Content-Type: text/plain; charset="utf-8" CPU_EXCEPTION_INIT_DATA is now an internal implementation of CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the same definition. Also, two fields (Revision and InitDefaultHandlers)are useless, can be removed. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- .../CpuExceptionCommon.h | 118 ++++++++---------- .../CpuExceptionHandlerLib/DxeException.c | 25 ++-- .../Ia32/ArchExceptionHandler.c | 71 ++++++----- .../CpuExceptionHandlerLib/PeiCpuException.c | 25 ++-- .../X64/ArchExceptionHandler.c | 67 +++++----- 5 files changed, 145 insertions(+), 161 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 443eaf359b..11a5624f51 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -49,71 +49,59 @@ =20 #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) =20 -#define CPU_EXCEPTION_INIT_DATA_REV 1 - -typedef union { - struct { - // - // Revision number of this structure. - // - UINT32 Revision; - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - // - // Flag to indicate if default handlers should be initialized or not. - // - BOOLEAN InitDefaultHandlers; - } Ia32, X64; +typedef struct { + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; } CPU_EXCEPTION_INIT_DATA; =20 // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index 04e8409922..d90c607bd7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -190,19 +190,18 @@ InitializeSeparateExceptionStacks ( } =20 AsmReadIdtr (&Idtr); - EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.X64.KnownGoodStackTop =3D StackTop; - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D NewGdtTable; - EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; - EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + EssData.KnownGoodStackTop =3D StackTop; + EssData.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable =3D (VOID *)Idtr.Base; + EssData.IdtTableSize =3D Idtr.Limit + 1; + EssData.GdtTable =3D NewGdtTable; + EssData.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limit + = 1; + EssData.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 + CP= U_TSS_DESC_SIZE; + EssData.ExceptionTssSize =3D CPU_TSS_SIZE; =20 return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index f13e8e7020..194d3a499b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file IA32 CPU Exception Handler functons. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -132,16 +132,15 @@ ArchSetupExceptionStack ( EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.Revision !=3D CPU_EXCEPTION_INIT_DATA_REV) || - (StackSwitchData->Ia32.KnownGoodStackTop =3D=3D 0) || - (StackSwitchData->Ia32.KnownGoodStackSize =3D=3D 0) || - (StackSwitchData->Ia32.StackSwitchExceptions =3D=3D NULL) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber =3D=3D 0) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NU= M) || - (StackSwitchData->Ia32.GdtTable =3D=3D NULL) || - (StackSwitchData->Ia32.IdtTable =3D=3D NULL) || - (StackSwitchData->Ia32.ExceptionTssDesc =3D=3D NULL) || - (StackSwitchData->Ia32.ExceptionTss =3D=3D NULL)) + (StackSwitchData->KnownGoodStackTop =3D=3D 0) || + (StackSwitchData->KnownGoodStackSize =3D=3D 0) || + (StackSwitchData->StackSwitchExceptions =3D=3D NULL) || + (StackSwitchData->StackSwitchExceptionNumber =3D=3D 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable =3D=3D NULL) || + (StackSwitchData->IdtTable =3D=3D NULL) || + (StackSwitchData->ExceptionTssDesc =3D=3D NULL) || + (StackSwitchData->ExceptionTss =3D=3D NULL)) { return EFI_INVALID_PARAMETER; } @@ -151,16 +150,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exce= ption // task-state segments. // - if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != =3D 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchD= ata->Ia32.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->= GdtTable)) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia3= 2.ExceptionTssDescSize > - ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.Gdt= TableSize)) + if ((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->Exceptio= nTssDescSize > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -169,20 +168,20 @@ ArchSetupExceptionStack ( // We need one descriptor and one TSS for current task and every excepti= on // specified. // - if (StackSwitchData->Ia32.ExceptionTssDescSize < - sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExc= eptionNumber + 1)) + if (StackSwitchData->ExceptionTssDescSize < + sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->StackSwitchExceptio= nNumber + 1)) { return EFI_INVALID_PARAMETER; } =20 - if (StackSwitchData->Ia32.ExceptionTssSize < - sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitc= hExceptionNumber + 1)) + if (StackSwitchData->ExceptionTssSize < + sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->StackSwitchExce= ptionNumber + 1)) { return EFI_INVALID_PARAMETER; } =20 - TssDesc =3D StackSwitchData->Ia32.ExceptionTssDesc; - Tss =3D StackSwitchData->Ia32.ExceptionTss; + TssDesc =3D StackSwitchData->ExceptionTssDesc; + Tss =3D StackSwitchData->ExceptionTss; =20 // // Initialize new GDT table and/or IDT table, if any @@ -192,20 +191,20 @@ ArchSetupExceptionStack ( =20 GdtSize =3D (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) * - (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) - - (UINTN)(StackSwitchData->Ia32.GdtTable); - if ((UINTN)StackSwitchData->Ia32.GdtTable !=3D Gdtr.Base) { - CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit= + 1); - Gdtr.Base =3D (UINTN)StackSwitchData->Ia32.GdtTable; + (StackSwitchData->StackSwitchExceptionNumber + 1) - + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; Gdtr.Limit =3D (UINT16)GdtSize - 1; } =20 - if ((UINTN)StackSwitchData->Ia32.IdtTable !=3D Idtr.Base) { - Idtr.Base =3D (UINTN)StackSwitchData->Ia32.IdtTable; + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; } =20 - if (StackSwitchData->Ia32.IdtTableSize > 0) { - Idtr.Limit =3D (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit =3D (UINT16)(StackSwitchData->IdtTableSize - 1); } =20 // @@ -227,10 +226,10 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // AsmGetTssTemplateMap (&TemplateMap); - StackTop =3D StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNME= NT; + StackTop =3D StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable =3D StackSwitchData->Ia32.IdtTable; - for (Index =3D 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumb= er; ++Index) { + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->StackSwitchExceptionNumber; += +Index) { TssDesc +=3D 1; Tss +=3D 1; =20 @@ -251,7 +250,7 @@ ArchSetupExceptionStack ( // // Fixup TSS // - Vector =3D StackSwitchData->Ia32.StackSwitchExceptions[Index]; + Vector =3D StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >=3D CPU_EXCEPTION_NUM) || (Vector >=3D (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -271,7 +270,7 @@ ArchSetupExceptionStack ( Tss->FS =3D AsmReadFs (); Tss->GS =3D AsmReadGs (); =20 - StackTop -=3D StackSwitchData->Ia32.KnownGoodStackSize; + StackTop -=3D StackSwitchData->KnownGoodStackSize; =20 // // Update IDT to use Task Gate for given exception @@ -291,7 +290,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdt= r.Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Bas= e)); =20 // // Publish IDT diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index 52ec0fb803..5952295126 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -236,19 +236,18 @@ InitializeSeparateExceptionStacks ( NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); =20 AsmReadIdtr (&Idtr); - EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.X64.KnownGoodStackTop =3D StackTop; - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D NewGdtTable; - EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; - EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + EssData.KnownGoodStackTop =3D StackTop; + EssData.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable =3D (VOID *)Idtr.Base; + EssData.IdtTableSize =3D Idtr.Limit + 1; + EssData.GdtTable =3D NewGdtTable; + EssData.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limit + = 1; + EssData.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 + CP= U_TSS_DESC_SIZE; + EssData.ExceptionTssSize =3D CPU_TSS_SIZE; =20 return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index cd7dccd481..c14ac66c43 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file x64 CPU Exception Handler. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -136,16 +136,15 @@ ArchSetupExceptionStack ( UINTN GdtSize; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.Revision !=3D CPU_EXCEPTION_INIT_DATA_REV) || - (StackSwitchData->X64.KnownGoodStackTop =3D=3D 0) || - (StackSwitchData->X64.KnownGoodStackSize =3D=3D 0) || - (StackSwitchData->X64.StackSwitchExceptions =3D=3D NULL) || - (StackSwitchData->X64.StackSwitchExceptionNumber =3D=3D 0) || - (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM= ) || - (StackSwitchData->X64.GdtTable =3D=3D NULL) || - (StackSwitchData->X64.IdtTable =3D=3D NULL) || - (StackSwitchData->X64.ExceptionTssDesc =3D=3D NULL) || - (StackSwitchData->X64.ExceptionTss =3D=3D NULL)) + (StackSwitchData->KnownGoodStackTop =3D=3D 0) || + (StackSwitchData->KnownGoodStackSize =3D=3D 0) || + (StackSwitchData->StackSwitchExceptions =3D=3D NULL) || + (StackSwitchData->StackSwitchExceptionNumber =3D=3D 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable =3D=3D NULL) || + (StackSwitchData->IdtTable =3D=3D NULL) || + (StackSwitchData->ExceptionTssDesc =3D=3D NULL) || + (StackSwitchData->ExceptionTss =3D=3D NULL)) { return EFI_INVALID_PARAMETER; } @@ -155,16 +154,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exce= ption // task-state segments. // - if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != =3D 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchDa= ta->X64.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->= GdtTable)) { return EFI_INVALID_PARAMETER; } =20 - if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64= .ExceptionTssDescSize) > - ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTa= bleSize)) + if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->Excepti= onTssDescSize) > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -172,20 +171,20 @@ ArchSetupExceptionStack ( // // One task gate descriptor and one task-state segment are needed. // - if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIP= TOR)) { + if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)= ) { return EFI_INVALID_PARAMETER; } =20 - if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGM= ENT)) { + if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)= ) { return EFI_INVALID_PARAMETER; } =20 // // Interrupt stack table supports only 7 vectors. // - TssDesc =3D StackSwitchData->X64.ExceptionTssDesc; - Tss =3D StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->I= ST)) { + TssDesc =3D StackSwitchData->ExceptionTssDesc; + Tss =3D StackSwitchData->ExceptionTss; + if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST))= { return EFI_INVALID_PARAMETER; } =20 @@ -196,19 +195,19 @@ ArchSetupExceptionStack ( AsmReadGdtr (&Gdtr); =20 GdtSize =3D (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) - - (UINTN)(StackSwitchData->X64.GdtTable); - if ((UINTN)StackSwitchData->X64.GdtTable !=3D Gdtr.Base) { - CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit = + 1); - Gdtr.Base =3D (UINTN)StackSwitchData->X64.GdtTable; + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; Gdtr.Limit =3D (UINT16)GdtSize - 1; } =20 - if ((UINTN)StackSwitchData->X64.IdtTable !=3D Idtr.Base) { - Idtr.Base =3D (UINTN)StackSwitchData->X64.IdtTable; + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; } =20 - if (StackSwitchData->X64.IdtTableSize > 0) { - Idtr.Limit =3D (UINT16)(StackSwitchData->X64.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit =3D (UINT16)(StackSwitchData->IdtTableSize - 1); } =20 // @@ -232,20 +231,20 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // ZeroMem (Tss, sizeof (*Tss)); - StackTop =3D StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMEN= T; + StackTop =3D StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable =3D StackSwitchData->X64.IdtTable; - for (Index =3D 0; Index < StackSwitchData->X64.StackSwitchExceptionNumbe= r; ++Index) { + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->StackSwitchExceptionNumber; += +Index) { // // Fixup IST // Tss->IST[Index] =3D StackTop; - StackTop -=3D StackSwitchData->X64.KnownGoodStackSize; + StackTop -=3D StackSwitchData->KnownGoodStackSize; =20 // // Set the IST field to enable corresponding IST // - Vector =3D StackSwitchData->X64.StackSwitchExceptions[Index]; + Vector =3D StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >=3D CPU_EXCEPTION_NUM) || (Vector >=3D (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -263,7 +262,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr= .Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Bas= e)); =20 // // Publish IDT --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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