From nobody Mon Feb 9 20:31:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92152+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92152+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659681577; cv=none; d=zohomail.com; s=zohoarc; b=KUZTndrHFL0ecMFfgoJWdiaOY8TTmvz8qob6nMDSm5dds+eoIKohJzFL3hdXELQ2RshOm1IpHcmd1kC2Yz71S5Xuk8Vv63pCZQIsAxIGtpxjOt/a47t+hUqd3PLqO3HcSzoTkwOS8gFxwQ+Hmi+2G92jr6wV3Uzl1522G254o3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659681577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kJ5tEiNQPn5IvMaOWLvmqhV4sL3sZj7SgW/doLrGfoU=; b=jDpGOOXAc5GBy8G0yCKe6TmloWSeEf39CtQ+5o1ZQ2OFV3WLFAPbB8AKy2BxUZF/gIA5KyCOCHmuhxgQB1g4DvlWtRzjMxZHd0HMgvJjBlDtdrnxhyfnFl3BxckmC13yVnbJa+rFz/t72RZZ2SBZ5WO3W8jlaTt2Q//bdpXqNF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92152+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659681577919703.420993819755; Thu, 4 Aug 2022 23:39:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id G1kzYY1788612xYvuB3jHwH1; Thu, 04 Aug 2022 23:39:36 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web08.4050.1659681568025593867 for ; Thu, 04 Aug 2022 23:39:35 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="273180965" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="273180965" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:35 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="554011619" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:33 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH v2 3/3] UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA Date: Fri, 5 Aug 2022 14:39:12 +0800 Message-Id: <20220805063912.1347-4-zhiguang.liu@intel.com> In-Reply-To: <20220805063912.1347-1-zhiguang.liu@intel.com> References: <20220805063912.1347-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: iUE3jk5dBkaYDRXlnVxF2wVqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659681576; bh=5VKl24CISwwWY3Kcuk86CsJTiflayrOw3GnePYKMwH4=; h=Cc:Date:From:Reply-To:Subject:To; b=UnEWuv8Vqcl2ywRcThAYM/xdualK/qQrt1Sd9grIy0nS2STxSx4UPlbf/XTe6X70n66 GmQ8MH+0dUkOBXSr/PzyrRE10s8I4nez71n53PSrUeu55+ssq7gpO8mj+rtaSZU9FGU/Z 12dWVYm9OTIwvdA8U4C+LNQFIgH71Bv+C/8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659681578636100011 Content-Type: text/plain; charset="utf-8" CPU_EXCEPTION_INIT_DATA is now an internal implementation of CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the same definition Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu --- .../CpuExceptionCommon.h | 108 +++++++++--------- .../CpuExceptionHandlerLib/DxeException.c | 24 ++-- .../Ia32/ArchExceptionHandler.c | 68 +++++------ .../CpuExceptionHandlerLib/PeiCpuException.c | 24 ++-- .../X64/ArchExceptionHandler.c | 64 +++++------ 5 files changed, 143 insertions(+), 145 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 67d81d50d2..11a5624f51 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -49,61 +49,59 @@ =20 #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) =20 -typedef union { - struct { - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - } Ia32, X64; +typedef struct { + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; } CPU_EXCEPTION_INIT_DATA; =20 // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index 674029f8ac..d90c607bd7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -190,18 +190,18 @@ InitializeSeparateExceptionStacks ( } =20 AsmReadIdtr (&Idtr); - EssData.X64.KnownGoodStackTop =3D StackTop; - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D NewGdtTable; - EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; - EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + EssData.KnownGoodStackTop =3D StackTop; + EssData.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable =3D (VOID *)Idtr.Base; + EssData.IdtTableSize =3D Idtr.Limit + 1; + EssData.GdtTable =3D NewGdtTable; + EssData.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limit + = 1; + EssData.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 + CP= U_TSS_DESC_SIZE; + EssData.ExceptionTssSize =3D CPU_TSS_SIZE; =20 return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index fa62074023..194d3a499b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -132,15 +132,15 @@ ArchSetupExceptionStack ( EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.KnownGoodStackTop =3D=3D 0) || - (StackSwitchData->Ia32.KnownGoodStackSize =3D=3D 0) || - (StackSwitchData->Ia32.StackSwitchExceptions =3D=3D NULL) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber =3D=3D 0) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NU= M) || - (StackSwitchData->Ia32.GdtTable =3D=3D NULL) || - (StackSwitchData->Ia32.IdtTable =3D=3D NULL) || - (StackSwitchData->Ia32.ExceptionTssDesc =3D=3D NULL) || - (StackSwitchData->Ia32.ExceptionTss =3D=3D NULL)) + (StackSwitchData->KnownGoodStackTop =3D=3D 0) || + (StackSwitchData->KnownGoodStackSize =3D=3D 0) || + (StackSwitchData->StackSwitchExceptions =3D=3D NULL) || + (StackSwitchData->StackSwitchExceptionNumber =3D=3D 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable =3D=3D NULL) || + (StackSwitchData->IdtTable =3D=3D NULL) || + (StackSwitchData->ExceptionTssDesc =3D=3D NULL) || + (StackSwitchData->ExceptionTss =3D=3D NULL)) { return EFI_INVALID_PARAMETER; } @@ -150,16 +150,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exce= ption // task-state segments. // - if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != =3D 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchD= ata->Ia32.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->= GdtTable)) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia3= 2.ExceptionTssDescSize > - ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.Gdt= TableSize)) + if ((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->Exceptio= nTssDescSize > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -168,20 +168,20 @@ ArchSetupExceptionStack ( // We need one descriptor and one TSS for current task and every excepti= on // specified. // - if (StackSwitchData->Ia32.ExceptionTssDescSize < - sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExc= eptionNumber + 1)) + if (StackSwitchData->ExceptionTssDescSize < + sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->StackSwitchExceptio= nNumber + 1)) { return EFI_INVALID_PARAMETER; } =20 - if (StackSwitchData->Ia32.ExceptionTssSize < - sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitc= hExceptionNumber + 1)) + if (StackSwitchData->ExceptionTssSize < + sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->StackSwitchExce= ptionNumber + 1)) { return EFI_INVALID_PARAMETER; } =20 - TssDesc =3D StackSwitchData->Ia32.ExceptionTssDesc; - Tss =3D StackSwitchData->Ia32.ExceptionTss; + TssDesc =3D StackSwitchData->ExceptionTssDesc; + Tss =3D StackSwitchData->ExceptionTss; =20 // // Initialize new GDT table and/or IDT table, if any @@ -191,20 +191,20 @@ ArchSetupExceptionStack ( =20 GdtSize =3D (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) * - (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) - - (UINTN)(StackSwitchData->Ia32.GdtTable); - if ((UINTN)StackSwitchData->Ia32.GdtTable !=3D Gdtr.Base) { - CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit= + 1); - Gdtr.Base =3D (UINTN)StackSwitchData->Ia32.GdtTable; + (StackSwitchData->StackSwitchExceptionNumber + 1) - + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; Gdtr.Limit =3D (UINT16)GdtSize - 1; } =20 - if ((UINTN)StackSwitchData->Ia32.IdtTable !=3D Idtr.Base) { - Idtr.Base =3D (UINTN)StackSwitchData->Ia32.IdtTable; + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; } =20 - if (StackSwitchData->Ia32.IdtTableSize > 0) { - Idtr.Limit =3D (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit =3D (UINT16)(StackSwitchData->IdtTableSize - 1); } =20 // @@ -226,10 +226,10 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // AsmGetTssTemplateMap (&TemplateMap); - StackTop =3D StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNME= NT; + StackTop =3D StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable =3D StackSwitchData->Ia32.IdtTable; - for (Index =3D 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumb= er; ++Index) { + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->StackSwitchExceptionNumber; += +Index) { TssDesc +=3D 1; Tss +=3D 1; =20 @@ -250,7 +250,7 @@ ArchSetupExceptionStack ( // // Fixup TSS // - Vector =3D StackSwitchData->Ia32.StackSwitchExceptions[Index]; + Vector =3D StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >=3D CPU_EXCEPTION_NUM) || (Vector >=3D (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -270,7 +270,7 @@ ArchSetupExceptionStack ( Tss->FS =3D AsmReadFs (); Tss->GS =3D AsmReadGs (); =20 - StackTop -=3D StackSwitchData->Ia32.KnownGoodStackSize; + StackTop -=3D StackSwitchData->KnownGoodStackSize; =20 // // Update IDT to use Task Gate for given exception @@ -290,7 +290,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdt= r.Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Bas= e)); =20 // // Publish IDT diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index fe8d02d3e4..5952295126 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -236,18 +236,18 @@ InitializeSeparateExceptionStacks ( NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); =20 AsmReadIdtr (&Idtr); - EssData.X64.KnownGoodStackTop =3D StackTop; - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D NewGdtTable; - EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; - EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + EssData.KnownGoodStackTop =3D StackTop; + EssData.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable =3D (VOID *)Idtr.Base; + EssData.IdtTableSize =3D Idtr.Limit + 1; + EssData.GdtTable =3D NewGdtTable; + EssData.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limit + = 1; + EssData.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 + CP= U_TSS_DESC_SIZE; + EssData.ExceptionTssSize =3D CPU_TSS_SIZE; =20 return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index ff0dde4f12..c14ac66c43 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -136,15 +136,15 @@ ArchSetupExceptionStack ( UINTN GdtSize; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->X64.KnownGoodStackTop =3D=3D 0) || - (StackSwitchData->X64.KnownGoodStackSize =3D=3D 0) || - (StackSwitchData->X64.StackSwitchExceptions =3D=3D NULL) || - (StackSwitchData->X64.StackSwitchExceptionNumber =3D=3D 0) || - (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM= ) || - (StackSwitchData->X64.GdtTable =3D=3D NULL) || - (StackSwitchData->X64.IdtTable =3D=3D NULL) || - (StackSwitchData->X64.ExceptionTssDesc =3D=3D NULL) || - (StackSwitchData->X64.ExceptionTss =3D=3D NULL)) + (StackSwitchData->KnownGoodStackTop =3D=3D 0) || + (StackSwitchData->KnownGoodStackSize =3D=3D 0) || + (StackSwitchData->StackSwitchExceptions =3D=3D NULL) || + (StackSwitchData->StackSwitchExceptionNumber =3D=3D 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable =3D=3D NULL) || + (StackSwitchData->IdtTable =3D=3D NULL) || + (StackSwitchData->ExceptionTssDesc =3D=3D NULL) || + (StackSwitchData->ExceptionTss =3D=3D NULL)) { return EFI_INVALID_PARAMETER; } @@ -154,16 +154,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exce= ption // task-state segments. // - if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != =3D 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchDa= ta->X64.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->= GdtTable)) { return EFI_INVALID_PARAMETER; } =20 - if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64= .ExceptionTssDescSize) > - ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTa= bleSize)) + if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->Excepti= onTssDescSize) > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -171,20 +171,20 @@ ArchSetupExceptionStack ( // // One task gate descriptor and one task-state segment are needed. // - if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIP= TOR)) { + if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)= ) { return EFI_INVALID_PARAMETER; } =20 - if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGM= ENT)) { + if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)= ) { return EFI_INVALID_PARAMETER; } =20 // // Interrupt stack table supports only 7 vectors. // - TssDesc =3D StackSwitchData->X64.ExceptionTssDesc; - Tss =3D StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->I= ST)) { + TssDesc =3D StackSwitchData->ExceptionTssDesc; + Tss =3D StackSwitchData->ExceptionTss; + if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST))= { return EFI_INVALID_PARAMETER; } =20 @@ -195,19 +195,19 @@ ArchSetupExceptionStack ( AsmReadGdtr (&Gdtr); =20 GdtSize =3D (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) - - (UINTN)(StackSwitchData->X64.GdtTable); - if ((UINTN)StackSwitchData->X64.GdtTable !=3D Gdtr.Base) { - CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit = + 1); - Gdtr.Base =3D (UINTN)StackSwitchData->X64.GdtTable; + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; Gdtr.Limit =3D (UINT16)GdtSize - 1; } =20 - if ((UINTN)StackSwitchData->X64.IdtTable !=3D Idtr.Base) { - Idtr.Base =3D (UINTN)StackSwitchData->X64.IdtTable; + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; } =20 - if (StackSwitchData->X64.IdtTableSize > 0) { - Idtr.Limit =3D (UINT16)(StackSwitchData->X64.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit =3D (UINT16)(StackSwitchData->IdtTableSize - 1); } =20 // @@ -231,20 +231,20 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // ZeroMem (Tss, sizeof (*Tss)); - StackTop =3D StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMEN= T; + StackTop =3D StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable =3D StackSwitchData->X64.IdtTable; - for (Index =3D 0; Index < StackSwitchData->X64.StackSwitchExceptionNumbe= r; ++Index) { + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->StackSwitchExceptionNumber; += +Index) { // // Fixup IST // Tss->IST[Index] =3D StackTop; - StackTop -=3D StackSwitchData->X64.KnownGoodStackSize; + StackTop -=3D StackSwitchData->KnownGoodStackSize; =20 // // Set the IST field to enable corresponding IST // - Vector =3D StackSwitchData->X64.StackSwitchExceptions[Index]; + Vector =3D StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >=3D CPU_EXCEPTION_NUM) || (Vector >=3D (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -262,7 +262,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr= .Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Bas= e)); =20 // // Publish IDT --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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