From nobody Sat Apr 20 02:47:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92150+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92150+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659681572; cv=none; d=zohomail.com; s=zohoarc; b=gKpN/6iCJO7ykkRdDKhuriAF8tuoMJrlm+QPWvIsvSZ7Tyz4jxUKTwP5J58q0RzrUX8k5N7kAKyVWTuXvpG/ewB8mSWD4owd2m6mSQgeJhhZ+Q8S5zBqGpUHnJjb11paNULsSRToE3GlDgQaZb0n0ovMkJP7ufnDg4b9thGCy2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659681572; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ORQJXwlFONJUXI1hyPbWCnRaX094IoyxR2w59Tg7NB8=; b=WWssmnmvyuoqopf7QcNyC+LxuGXgWccD0cChWip8BCYhi0ZRAeFw7QwKpfMzhf3/UBcxtdwvrVrmeglZ49cLHGpBmnbHzJOXbElyE8PlcRFtvCcSBhpwJZAdbdLOPcbPTTG9Hz7f07m7TMwcyoCwRLa51HEz60cCAdKqVYas1x0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92150+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659681572146771.7195810759404; Thu, 4 Aug 2022 23:39:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZrsCYY1788612xmbyvrPYNtv; Thu, 04 Aug 2022 23:39:31 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web08.4050.1659681568025593867 for ; Thu, 04 Aug 2022 23:39:31 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="273180926" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="273180926" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="554011594" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:27 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Dandan Bi , Liming Gao , Jian J Wang , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v2 1/3] UefiCpuPkg: Simplify InitializeSeparateExceptionStacks Date: Fri, 5 Aug 2022 14:39:10 +0800 Message-Id: <20220805063912.1347-2-zhiguang.liu@intel.com> In-Reply-To: <20220805063912.1347-1-zhiguang.liu@intel.com> References: <20220805063912.1347-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: fvoB9HQXV3yozSOpqXx7bS4Mx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659681571; bh=BLn0igQ8Cg460BgSmq4vCAett32IokLUCdXXu1eRU/M=; h=Cc:Date:From:Reply-To:Subject:To; b=tMG42fwc8ktk1wG0sYV1ZbEPKYYzjyzgCJ1tszAPPtEJsOQWnNwSfqyoHUtzZE5wyTv 267E3mp4A4tkDSw4Bn+KSIWt9Z1YvpwpS7RwURDHN+ITrR6AnuGhaibzaG/0/pEdZIL9M wbubHF8a7QPo9yhkojVqLrB1NYzwgBQTRJE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659681574604100003 Content-Type: text/plain; charset="utf-8" Hide the Exception implementation details in CpuExcetionHandlerLib and caller only need to provide buffer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Dandan Bi Cc: Liming Gao Cc: Jian J Wang Cc: Ard Biesheuvel Reviewed-by: Sami Mujawar Signed-off-by: Zhiguang Liu --- .../Library/ArmExceptionLib/ArmExceptionLib.c | 15 +- MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 4 +- .../Include/Library/CpuExceptionHandlerLib.h | 15 +- .../CpuExceptionHandlerLibNull.c | 15 +- UefiCpuPkg/CpuDxe/CpuMp.c | 157 +++------------- UefiCpuPkg/CpuDxe/CpuMp.h | 10 +- UefiCpuPkg/CpuMpPei/CpuMpPei.c | 173 +++--------------- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 10 +- .../CpuExceptionHandlerLib/DxeException.c | 112 +++++++++--- .../Ia32/ArchExceptionHandler.c | 3 +- .../CpuExceptionHandlerLib/PeiCpuException.c | 94 +++++++++- .../PeiCpuExceptionHandlerLib.inf | 4 +- .../SecPeiCpuException.c | 15 +- .../CpuExceptionHandlerLib/SmmException.c | 15 +- .../X64/ArchExceptionHandler.c | 3 +- 15 files changed, 294 insertions(+), 351 deletions(-) diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c b/ArmPkg/Libr= ary/ArmExceptionLib/ArmExceptionLib.c index 2c7bc66aa7..a521c33f32 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c @@ -288,20 +288,23 @@ CommonCExceptionHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_SUCCESS; diff --git a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c b/MdeModulePkg/Core/Dx= e/DxeMain/DxeMain.c index 0a1f3d79e2..5733f0c8ec 100644 --- a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c +++ b/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c @@ -1,7 +1,7 @@ /** @file DXE Core Main Entry Point =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -260,7 +260,7 @@ DxeMain ( // Setup Stack Guard // if (PcdGetBool (PcdCpuStackGuard)) { - Status =3D InitializeSeparateExceptionStacks (NULL); + Status =3D InitializeSeparateExceptionStacks (NULL, NULL); ASSERT_EFI_ERROR (Status); } =20 diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 9a495081f7..8d44ed916a 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -104,20 +104,23 @@ InitializeCpuExceptionHandlers ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ); =20 /** diff --git a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHa= ndlerLibNull.c b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExcepti= onHandlerLibNull.c index 8aeedcb4d1..74908a379b 100644 --- a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi= bNull.c +++ b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi= bNull.c @@ -83,20 +83,23 @@ DumpCpuContext ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c index e385f585c7..d5cf03899b 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.c +++ b/UefiCpuPkg/CpuDxe/CpuMp.c @@ -596,24 +596,6 @@ CollectBistDataFromHob ( } } =20 -/** - Get GDT register value. - - This function is mainly for AP purpose because AP may have different GDT - table than BSP. - - @param[in,out] Buffer The pointer to private data buffer. - -**/ -VOID -EFIAPI -GetGdtr ( - IN OUT VOID *Buffer - ) -{ - AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); -} - /** Initializes CPU exceptions handlers for the sake of stack switch require= ment. =20 @@ -629,27 +611,17 @@ InitializeExceptionStackSwitchHandlers ( IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + EXCEPTION_STACK_SWITCH_CONTEXT *SwitchStackData; =20 - EssData =3D Buffer; - // - // We don't plan to replace IDT table with a new one, but we should not = assume - // the AP's IDT is the same as BSP's IDT either. - // - AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable =3D (VOID *)Idtr.Base; - EssData->Ia32.IdtTableSize =3D Idtr.Limit + 1; - Status =3D InitializeSeparateExceptionStacks (EssDat= a); - ASSERT_EFI_ERROR (Status); + SwitchStackData =3D (EXCEPTION_STACK_SWITCH_CONTEXT *)Buffer; + InitializeSeparateExceptionStacks (SwitchStackData->Buffer, SwitchStackD= ata->BufferSize); } =20 /** Initializes MP exceptions handlers for the sake of stack switch requirem= ent. =20 This function will allocate required resources required to setup stack s= witch - and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor. + and pass them through SwitchStackData to each logic processor. =20 **/ VOID @@ -657,129 +629,52 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - - ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * Exception= Number; - - StackTop =3D AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors= ); - ASSERT (StackTop !=3D NULL); - StackTop +=3D NewStackSize * mNumberOfProcessors; + UINTN Index; + UINTN Bsp; + UINT8 *Buffer; + EXCEPTION_STACK_SWITCH_CONTEXT SwitchStackData; + UINTN BufferSize; =20 - // - // The default exception handlers must have been initialized. Let's just= skip - // it in this method. - // - EssData.Ia32.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.Ia32.InitDefaultHandlers =3D FALSE; - - EssData.Ia32.StackSwitchExceptions =3D FixedPcdGetPtr (PcdCpuStackS= witchExceptionList); - EssData.Ia32.StackSwitchExceptionNumber =3D ExceptionNumber; - EssData.Ia32.KnownGoodStackSize =3D FixedPcdGet32 (PcdCpuKnownGo= odStackSize); - - // - // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. - // - Gdtr.Base =3D 0; - Gdtr.Limit =3D 0; + SwitchStackData.BufferSize =3D &BufferSize; MpInitLibWhoAmI (&Bsp); + for (Index =3D 0; Index < mNumberOfProcessors; ++Index) { - // - // To support stack switch, we need to re-construct GDT but not IDT. - // + SwitchStackData.Buffer =3D NULL; + BufferSize =3D 0; + if (Index =3D=3D Bsp) { - GetGdtr (&Gdtr); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { // - // AP might have different size of GDT from BSP. + // AP might need different buffer size from BSP. // - MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); + MpInitLibStartupThisAP (InitializeExceptionStackSwitchHandlers, Inde= x, NULL, 0, (VOID *)&SwitchStackData, NULL); } =20 - // - // X64 needs only one TSS of current task working for all exceptions - // because of its IST feature. IA32 needs one TSS for each exception - // in addition to current task. Since AP is not supposed to allocate - // memory, we have to do it in BSP. To simplify the code, we allocate - // memory for IA32 case to cover both IA32 and X64 exception stack - // switch. - // - // Layout of memory to allocate for each processor: - // -------------------------------- - // | Alignment | (just in case) - // -------------------------------- - // | | - // | Original GDT | - // | | - // -------------------------------- - // | Current task descriptor | - // -------------------------------- - // | | - // | Exception task descriptors | X ExceptionNumber - // | | - // -------------------------------- - // | Current task-state segment | - // -------------------------------- - // | | - // | Exception task-state segment | X ExceptionNumber - // | | - // -------------------------------- - // - OldGdtSize =3D Gdtr.Limit + 1; - EssData.Ia32.ExceptionTssDescSize =3D sizeof (IA32_TSS_DESCRIPTOR) * - (ExceptionNumber + 1); - EssData.Ia32.ExceptionTssSize =3D sizeof (IA32_TASK_STATE_SEGMENT) * - (ExceptionNumber + 1); - NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + - OldGdtSize + - EssData.Ia32.ExceptionTssDescSize + - EssData.Ia32.ExceptionTssSize; - - GdtBuffer =3D AllocateRuntimeZeroPool (NewGdtSize); - ASSERT (GdtBuffer !=3D NULL); - - // - // Make sure GDT table alignment - // - EssData.Ia32.GdtTable =3D ALIGN_POINTER (GdtBuffer, sizeof (IA32_T= SS_DESCRIPTOR)); - NewGdtSize -=3D ((UINT8 *)EssData.Ia32.GdtTable - GdtBuf= fer); - EssData.Ia32.GdtTableSize =3D NewGdtSize; - - EssData.Ia32.ExceptionTssDesc =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize); - EssData.Ia32.ExceptionTss =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize + - EssData.Ia32.ExceptionTssDescSize); - - EssData.Ia32.KnownGoodStackTop =3D (UINTN)StackTop; + ASSERT (BufferSize !=3D 0); + Buffer =3D AllocateRuntimeZeroPool (BufferSize); + ASSERT (Buffer !=3D NULL); + SwitchStackData.Buffer =3D Buffer; DEBUG (( DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", + "Buffer[cpu%lu] for InitializeExceptionStackSwitchHandlers: 0x%lX wi= th size 0x%x\n", (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop + (UINT64)(UINTN)Buffer, + (UINT32)BufferSize )); =20 if (Index =3D=3D Bsp) { - InitializeExceptionStackSwitchHandlers (&EssData); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { MpInitLibStartupThisAP ( InitializeExceptionStackSwitchHandlers, Index, NULL, 0, - (VOID *)&EssData, + (VOID *)&SwitchStackData, NULL ); } - - StackTop -=3D NewStackSize; } } =20 diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h index b461753510..c8a726d9bc 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.h +++ b/UefiCpuPkg/CpuDxe/CpuMp.h @@ -1,7 +1,7 @@ /** @file CPU DXE MP support =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -9,6 +9,14 @@ #ifndef _CPU_MP_H_ #define _CPU_MP_H_ =20 +// +// Structure for InitializeSeparateExceptionStacks +// +typedef struct { + VOID *Buffer; + UINTN *BufferSize; +} EXCEPTION_STACK_SWITCH_CONTEXT; + /** Initialize Multi-processor support. =20 diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c index d4786979fa..576e6b81a2 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.c +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.c @@ -1,7 +1,7 @@ /** @file CPU PEI Module installs CPU Multiple Processor PPI. =20 - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -411,24 +411,6 @@ PeiWhoAmI ( return MpInitLibWhoAmI (ProcessorNumber); } =20 -/** - Get GDT register value. - - This function is mainly for AP purpose because AP may have different GDT - table than BSP. - - @param[in,out] Buffer The pointer to private data buffer. - -**/ -VOID -EFIAPI -GetGdtr ( - IN OUT VOID *Buffer - ) -{ - AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); -} - /** Initializes CPU exceptions handlers for the sake of stack switch require= ment. =20 @@ -444,27 +426,17 @@ InitializeExceptionStackSwitchHandlers ( IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + EXCEPTION_STACK_SWITCH_CONTEXT *SwitchStackData; =20 - EssData =3D Buffer; - // - // We don't plan to replace IDT table with a new one, but we should not = assume - // the AP's IDT is the same as BSP's IDT either. - // - AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable =3D (VOID *)Idtr.Base; - EssData->Ia32.IdtTableSize =3D Idtr.Limit + 1; - Status =3D InitializeSeparateExceptionStacks (EssDat= a); - ASSERT_EFI_ERROR (Status); + SwitchStackData =3D (EXCEPTION_STACK_SWITCH_CONTEXT *)Buffer; + InitializeSeparateExceptionStacks (SwitchStackData->Buffer, SwitchStackD= ata->BufferSize); } =20 /** Initializes MP exceptions handlers for the sake of stack switch requirem= ent. =20 This function will allocate required resources required to setup stack s= witch - and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor. + and pass them through SwitchStackData to each logic processor. =20 **/ VOID @@ -472,148 +444,59 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - EFI_STATUS Status; - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - UINTN NumberOfProcessors; + UINTN Index; + UINTN Bsp; + UINT8 *Buffer; + EXCEPTION_STACK_SWITCH_CONTEXT SwitchStackData; + UINTN BufferSize; + UINTN NumberOfProcessors; =20 if (!PcdGetBool (PcdCpuStackGuard)) { return; } =20 + SwitchStackData.BufferSize =3D &BufferSize; MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL); MpInitLibWhoAmI (&Bsp); =20 - ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * Exception= Number; - - StackTop =3D AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfPr= ocessors)); - ASSERT (StackTop !=3D NULL); - if (StackTop =3D=3D NULL) { - return; - } - - StackTop +=3D NewStackSize * NumberOfProcessors; - - // - // The default exception handlers must have been initialized. Let's just= skip - // it in this method. - // - EssData.Ia32.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.Ia32.InitDefaultHandlers =3D FALSE; - - EssData.Ia32.StackSwitchExceptions =3D FixedPcdGetPtr (PcdCpuStackS= witchExceptionList); - EssData.Ia32.StackSwitchExceptionNumber =3D ExceptionNumber; - EssData.Ia32.KnownGoodStackSize =3D FixedPcdGet32 (PcdCpuKnownGo= odStackSize); - - // - // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. - // - Gdtr.Base =3D 0; - Gdtr.Limit =3D 0; for (Index =3D 0; Index < NumberOfProcessors; ++Index) { - // - // To support stack switch, we need to re-construct GDT but not IDT. - // + SwitchStackData.Buffer =3D NULL; + BufferSize =3D 0; + if (Index =3D=3D Bsp) { - GetGdtr (&Gdtr); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { // - // AP might have different size of GDT from BSP. + // AP might need different buffer size from BSP. // - MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); - } - - // - // X64 needs only one TSS of current task working for all exceptions - // because of its IST feature. IA32 needs one TSS for each exception - // in addition to current task. Since AP is not supposed to allocate - // memory, we have to do it in BSP. To simplify the code, we allocate - // memory for IA32 case to cover both IA32 and X64 exception stack - // switch. - // - // Layout of memory to allocate for each processor: - // -------------------------------- - // | Alignment | (just in case) - // -------------------------------- - // | | - // | Original GDT | - // | | - // -------------------------------- - // | Current task descriptor | - // -------------------------------- - // | | - // | Exception task descriptors | X ExceptionNumber - // | | - // -------------------------------- - // | Current task-state segment | - // -------------------------------- - // | | - // | Exception task-state segment | X ExceptionNumber - // | | - // -------------------------------- - // - OldGdtSize =3D Gdtr.Limit + 1; - EssData.Ia32.ExceptionTssDescSize =3D sizeof (IA32_TSS_DESCRIPTOR) * - (ExceptionNumber + 1); - EssData.Ia32.ExceptionTssSize =3D sizeof (IA32_TASK_STATE_SEGMENT) * - (ExceptionNumber + 1); - NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + - OldGdtSize + - EssData.Ia32.ExceptionTssDescSize + - EssData.Ia32.ExceptionTssSize; - - Status =3D PeiServicesAllocatePool ( - NewGdtSize, - (VOID **)&GdtBuffer - ); - ASSERT (GdtBuffer !=3D NULL); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return; + MpInitLibStartupThisAP (InitializeExceptionStackSwitchHandlers, Inde= x, NULL, 0, (VOID *)&SwitchStackData, NULL); } =20 - // - // Make sure GDT table alignment - // - EssData.Ia32.GdtTable =3D ALIGN_POINTER (GdtBuffer, sizeof (IA32_T= SS_DESCRIPTOR)); - NewGdtSize -=3D ((UINT8 *)EssData.Ia32.GdtTable - GdtBuf= fer); - EssData.Ia32.GdtTableSize =3D NewGdtSize; - - EssData.Ia32.ExceptionTssDesc =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize); - EssData.Ia32.ExceptionTss =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize + - EssData.Ia32.ExceptionTssDescSize); - - EssData.Ia32.KnownGoodStackTop =3D (UINTN)StackTop; + ASSERT (BufferSize !=3D 0); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); + ASSERT (Buffer !=3D NULL); + ZeroMem (Buffer, EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (BufferSize))); + SwitchStackData.Buffer =3D Buffer; DEBUG (( DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", + "Buffer[cpu%lu] for InitializeExceptionStackSwitchHandlers: 0x%lX wi= th size 0x%x\n", (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop + (UINT64)(UINTN)Buffer, + (UINT32)BufferSize )); =20 if (Index =3D=3D Bsp) { - InitializeExceptionStackSwitchHandlers (&EssData); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { MpInitLibStartupThisAP ( InitializeExceptionStackSwitchHandlers, Index, NULL, 0, - (VOID *)&EssData, + (VOID *)&SwitchStackData, NULL ); } - - StackTop -=3D NewStackSize; } } =20 diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h index 0649c48d14..754f8901b5 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h @@ -1,7 +1,7 @@ /** @file Definitions to install Multiple Processor PPI. =20 - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -31,6 +31,14 @@ =20 extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; =20 +// +// Structure for InitializeSeparateExceptionStacks +// +typedef struct { + VOID *Buffer; + UINTN *BufferSize; +} EXCEPTION_STACK_SWITCH_CONTEXT; + /** This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index e62bb5e6c0..674029f8ac 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -104,48 +104,104 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { CPU_EXCEPTION_INIT_DATA EssData; IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Gdtr; - - if (InitData =3D=3D NULL) { + UINTN NeedBufferSize; + UINTN StackTop; + UINT8 *NewGdtTable; + + // + // X64 needs only one TSS of current task working for all exceptions + // because of its IST feature. IA32 needs one TSS for each exception + // in addition to current task. To simplify the code, we report the + // needed memory for IA32 case to cover both IA32 and X64 exception + // stack switch. + // + // Layout of memory needed for each processor: + // -------------------------------- + // | Alignment | (just in case) + // -------------------------------- + // | | + // | Original GDT | + // | | + // -------------------------------- + // | Current task descriptor | + // -------------------------------- + // | | + // | Exception task descriptors | X ExceptionNumber + // | | + // -------------------------------- + // | Current task-state segment | + // -------------------------------- + // | | + // | Exception task-state segment | X ExceptionNumber + // | | + // -------------------------------- + // + AsmReadGdtr (&Gdtr); + if ((Buffer =3D=3D NULL) && (BufferSize =3D=3D NULL)) { SetMem (mNewGdt, sizeof (mNewGdt), 0); - - AsmReadIdtr (&Idtr); - AsmReadGdtr (&Gdtr); - - EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.X64.KnownGoodStackTop =3D (UINTN)mNewStack + sizeof (= mNewStack); - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_= LIST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_= NUMBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D mNewGdt; - EssData.X64.GdtTableSize =3D sizeof (mNewGdt); - EssData.X64.ExceptionTssDesc =3D mNewGdt + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D mNewGdt + Gdtr.Limit + 1 + = CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; - - InitData =3D &EssData; + StackTop =3D (UINTN)mNewStack + sizeof (mNewStack); + NewGdtTable =3D mNewGdt; + } else { + if (BufferSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Total needed size includes stack size, new GDT table size, TSS size. + // Add another DESCRIPTOR size for alignment requiremet. + // + NeedBufferSize =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_KNOWN_GOOD_= STACK_SIZE + + CPU_TSS_DESC_SIZE + Gdtr.Limit + 1 + + CPU_TSS_SIZE + + sizeof (IA32_TSS_DESCRIPTOR); + if (*BufferSize < NeedBufferSize) { + *BufferSize =3D NeedBufferSize; + return EFI_BUFFER_TOO_SMALL; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + StackTop =3D (UINTN)Buffer + CPU_STACK_SWITCH_EXCEPTION_NUMBER * CP= U_KNOWN_GOOD_STACK_SIZE; + NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); } =20 - return ArchSetupExceptionStack (InitData); + AsmReadIdtr (&Idtr); + EssData.X64.KnownGoodStackTop =3D StackTop; + EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; + EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; + EssData.X64.IdtTable =3D (VOID *)Idtr.Base; + EssData.X64.IdtTableSize =3D Idtr.Limit + 1; + EssData.X64.GdtTable =3D NewGdtTable; + EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; + EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + + return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index f13e8e7020..fa62074023 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file IA32 CPU Exception Handler functons. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -132,7 +132,6 @@ ArchSetupExceptionStack ( EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.Revision !=3D CPU_EXCEPTION_INIT_DATA_REV) || (StackSwitchData->Ia32.KnownGoodStackTop =3D=3D 0) || (StackSwitchData->Ia32.KnownGoodStackSize =3D=3D 0) || (StackSwitchData->Ia32.StackSwitchExceptions =3D=3D NULL) || diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index 494c2ab433..fe8d02d3e4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -151,25 +151,103 @@ InitializeCpuExceptionHandlers ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { - if (InitData =3D=3D NULL) { + CPU_EXCEPTION_INIT_DATA EssData; + IA32_DESCRIPTOR Idtr; + IA32_DESCRIPTOR Gdtr; + UINTN NeedBufferSize; + UINTN StackTop; + UINT8 *NewGdtTable; + + // + // X64 needs only one TSS of current task working for all exceptions + // because of its IST feature. IA32 needs one TSS for each exception + // in addition to current task. To simplify the code, we report the + // needed memory for IA32 case to cover both IA32 and X64 exception + // stack switch. + // + // Layout of memory needed for each processor: + // -------------------------------- + // | Alignment | (just in case) + // -------------------------------- + // | | + // | Original GDT | + // | | + // -------------------------------- + // | Current task descriptor | + // -------------------------------- + // | | + // | Exception task descriptors | X ExceptionNumber + // | | + // -------------------------------- + // | Current task-state segment | + // -------------------------------- + // | | + // | Exception task-state segment | X ExceptionNumber + // | | + // -------------------------------- + // + + if ((Buffer =3D=3D NULL) && (BufferSize =3D=3D NULL)) { return EFI_UNSUPPORTED; } =20 - return ArchSetupExceptionStack (InitData); + if (BufferSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + AsmReadGdtr (&Gdtr); + // + // Total needed size includes stack size, new GDT table size, TSS size. + // Add another DESCRIPTOR size for alignment requiremet. + // + NeedBufferSize =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_KNOWN_GOOD_ST= ACK_SIZE + + CPU_TSS_DESC_SIZE + Gdtr.Limit + 1 + + CPU_TSS_SIZE + + sizeof (IA32_TSS_DESCRIPTOR); + if (*BufferSize < NeedBufferSize) { + *BufferSize =3D NeedBufferSize; + return EFI_BUFFER_TOO_SMALL; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + StackTop =3D (UINTN)Buffer + CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_= KNOWN_GOOD_STACK_SIZE; + NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); + + AsmReadIdtr (&Idtr); + EssData.X64.KnownGoodStackTop =3D StackTop; + EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; + EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; + EssData.X64.IdtTable =3D (VOID *)Idtr.Base; + EssData.X64.IdtTableSize =3D Idtr.Limit + 1; + EssData.X64.GdtTable =3D NewGdtTable; + EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; + EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + + return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index cf5bfe4083..7c2ec3b2db 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -1,7 +1,7 @@ ## @file # CPU Exception Handler library instance for PEI module. # -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -56,6 +56,8 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 4313cc5582..ad5e0e9ed4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -201,20 +201,23 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c index 1c97dab926..46a86ad2c6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c @@ -97,20 +97,23 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index cd7dccd481..ff0dde4f12 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file x64 CPU Exception Handler. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -136,7 +136,6 @@ ArchSetupExceptionStack ( UINTN GdtSize; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.Revision !=3D CPU_EXCEPTION_INIT_DATA_REV) || (StackSwitchData->X64.KnownGoodStackTop =3D=3D 0) || (StackSwitchData->X64.KnownGoodStackSize =3D=3D 0) || (StackSwitchData->X64.StackSwitchExceptions =3D=3D NULL) || --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92150): https://edk2.groups.io/g/devel/message/92150 Mute This Topic: https://groups.io/mt/92830476/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 02:47:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92151+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92151+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659681574; cv=none; d=zohomail.com; s=zohoarc; b=L/W8nYWZ4EKPhrzAd1wnrqRnIjConauVDCmRr+caeaT7Kic3z5KumcAhQox3vnVwJoSyHXTp6LQ4RoC6BFezAMMYyawEM2zP+aGC5WIFErFmJOmPHKENz2L2orOaUgytYO2IZtm5xyP4I/xqGE8iGUIn+C053BDAFxMvTLbMyv0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659681574; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vwG4sUattBf2bwj1s4T4ePPfEEhpm9NAz9pfug4FAm4=; b=X6EyPdIhtv3/tm4yBHVoqxyOhClw165oy01/YLPoebNcYshownDYlmFT1c1denfhrLQxTaufQ3L+YU2fENQ3YMWn/Ni+ZjY3h3JvNGRtwkNendlG0TIQZKghJk6yJo7xBpXc5u50yuSVf4dDcMtQnaP08ssOstD1xV+NJYfwX5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92151+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659681574919456.7469862792673; Thu, 4 Aug 2022 23:39:34 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RBlHYY1788612xYTEEWL9E85; Thu, 04 Aug 2022 23:39:34 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web08.4050.1659681568025593867 for ; Thu, 04 Aug 2022 23:39:34 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="273180950" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="273180950" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:33 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="554011604" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:30 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Dandan Bi , Liming Gao , Jian J Wang Subject: [edk2-devel] [PATCH v2 2/3] MdeModulePkg: Move CPU_EXCEPTION_INIT_DATA to UefiCpuPkg Date: Fri, 5 Aug 2022 14:39:11 +0800 Message-Id: <20220805063912.1347-3-zhiguang.liu@intel.com> In-Reply-To: <20220805063912.1347-1-zhiguang.liu@intel.com> References: <20220805063912.1347-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: CpXMfjOWfAfgCjJwzPWzg0Qax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659681574; bh=5RZ2h4Top3XSnDWhMzZIeR1xv2A6txiSai1guOLB+uA=; h=Cc:Date:From:Reply-To:Subject:To; b=B0kRYWLYQOf68QW8ZNt5kvWuaMSNEvqakx934YA16P6qAhaVSKuMsHUieFmn0f55Zk5 3vFulYKIfjGLYpZB3BeL7oTzKLtynFxFLTI7lf5gp/XGxDdCwA5TfeAk+tr3UKD9jlXJs ixfR6Z1IDxOXmRsfZJXKvSniVAN+Xien9hc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659681576625100007 Content-Type: text/plain; charset="utf-8" Since the API InitializeSeparateExceptionStacks is simplified and does't use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become a inner implementation of CpuExcetionHandlerLib. Remove it from MdeModulePkg. Also, two fields (Revision and InitDefaultHandlers)are useless, can be removed. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Dandan Bi Cc: Liming Gao Cc: Jian J Wang Signed-off-by: Zhiguang Liu --- .../Include/Library/CpuExceptionHandlerLib.h | 67 ------------------- .../CpuExceptionCommon.h | 59 +++++++++++++++- 2 files changed, 58 insertions(+), 68 deletions(-) diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 8d44ed916a..94e9b20ae1 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -13,73 +13,6 @@ #include #include =20 -#define CPU_EXCEPTION_INIT_DATA_REV 1 - -typedef union { - struct { - // - // Revision number of this structure. - // - UINT32 Revision; - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - // - // Flag to indicate if default handlers should be initialized or not. - // - BOOLEAN InitDefaultHandlers; - } Ia32, X64; -} CPU_EXCEPTION_INIT_DATA; - /** Initializes all CPU exceptions entries and provides the default exceptio= n handlers. =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index fd42c4be0f..67d81d50d2 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -1,7 +1,7 @@ /** @file Common header file for CPU Exception Handler Library. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -49,6 +49,63 @@ =20 #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) =20 +typedef union { + struct { + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; + } Ia32, X64; +} CPU_EXCEPTION_INIT_DATA; + // // Record exception handler information // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92151): https://edk2.groups.io/g/devel/message/92151 Mute This Topic: https://groups.io/mt/92830477/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 02:47:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92152+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92152+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659681577; cv=none; d=zohomail.com; s=zohoarc; b=KUZTndrHFL0ecMFfgoJWdiaOY8TTmvz8qob6nMDSm5dds+eoIKohJzFL3hdXELQ2RshOm1IpHcmd1kC2Yz71S5Xuk8Vv63pCZQIsAxIGtpxjOt/a47t+hUqd3PLqO3HcSzoTkwOS8gFxwQ+Hmi+2G92jr6wV3Uzl1522G254o3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659681577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kJ5tEiNQPn5IvMaOWLvmqhV4sL3sZj7SgW/doLrGfoU=; b=jDpGOOXAc5GBy8G0yCKe6TmloWSeEf39CtQ+5o1ZQ2OFV3WLFAPbB8AKy2BxUZF/gIA5KyCOCHmuhxgQB1g4DvlWtRzjMxZHd0HMgvJjBlDtdrnxhyfnFl3BxckmC13yVnbJa+rFz/t72RZZ2SBZ5WO3W8jlaTt2Q//bdpXqNF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92152+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659681577919703.420993819755; Thu, 4 Aug 2022 23:39:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id G1kzYY1788612xYvuB3jHwH1; Thu, 04 Aug 2022 23:39:36 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web08.4050.1659681568025593867 for ; Thu, 04 Aug 2022 23:39:35 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="273180965" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="273180965" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:35 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="554011619" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:33 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH v2 3/3] UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA Date: Fri, 5 Aug 2022 14:39:12 +0800 Message-Id: <20220805063912.1347-4-zhiguang.liu@intel.com> In-Reply-To: <20220805063912.1347-1-zhiguang.liu@intel.com> References: <20220805063912.1347-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: iUE3jk5dBkaYDRXlnVxF2wVqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659681576; bh=5VKl24CISwwWY3Kcuk86CsJTiflayrOw3GnePYKMwH4=; h=Cc:Date:From:Reply-To:Subject:To; b=UnEWuv8Vqcl2ywRcThAYM/xdualK/qQrt1Sd9grIy0nS2STxSx4UPlbf/XTe6X70n66 GmQ8MH+0dUkOBXSr/PzyrRE10s8I4nez71n53PSrUeu55+ssq7gpO8mj+rtaSZU9FGU/Z 12dWVYm9OTIwvdA8U4C+LNQFIgH71Bv+C/8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659681578636100011 Content-Type: text/plain; charset="utf-8" CPU_EXCEPTION_INIT_DATA is now an internal implementation of CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the same definition Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu --- .../CpuExceptionCommon.h | 108 +++++++++--------- .../CpuExceptionHandlerLib/DxeException.c | 24 ++-- .../Ia32/ArchExceptionHandler.c | 68 +++++------ .../CpuExceptionHandlerLib/PeiCpuException.c | 24 ++-- .../X64/ArchExceptionHandler.c | 64 +++++------ 5 files changed, 143 insertions(+), 145 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 67d81d50d2..11a5624f51 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -49,61 +49,59 @@ =20 #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) =20 -typedef union { - struct { - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - } Ia32, X64; +typedef struct { + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; } CPU_EXCEPTION_INIT_DATA; =20 // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index 674029f8ac..d90c607bd7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -190,18 +190,18 @@ InitializeSeparateExceptionStacks ( } =20 AsmReadIdtr (&Idtr); - EssData.X64.KnownGoodStackTop =3D StackTop; - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D NewGdtTable; - EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; - EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + EssData.KnownGoodStackTop =3D StackTop; + EssData.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable =3D (VOID *)Idtr.Base; + EssData.IdtTableSize =3D Idtr.Limit + 1; + EssData.GdtTable =3D NewGdtTable; + EssData.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limit + = 1; + EssData.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 + CP= U_TSS_DESC_SIZE; + EssData.ExceptionTssSize =3D CPU_TSS_SIZE; =20 return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index fa62074023..194d3a499b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -132,15 +132,15 @@ ArchSetupExceptionStack ( EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.KnownGoodStackTop =3D=3D 0) || - (StackSwitchData->Ia32.KnownGoodStackSize =3D=3D 0) || - (StackSwitchData->Ia32.StackSwitchExceptions =3D=3D NULL) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber =3D=3D 0) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NU= M) || - (StackSwitchData->Ia32.GdtTable =3D=3D NULL) || - (StackSwitchData->Ia32.IdtTable =3D=3D NULL) || - (StackSwitchData->Ia32.ExceptionTssDesc =3D=3D NULL) || - (StackSwitchData->Ia32.ExceptionTss =3D=3D NULL)) + (StackSwitchData->KnownGoodStackTop =3D=3D 0) || + (StackSwitchData->KnownGoodStackSize =3D=3D 0) || + (StackSwitchData->StackSwitchExceptions =3D=3D NULL) || + (StackSwitchData->StackSwitchExceptionNumber =3D=3D 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable =3D=3D NULL) || + (StackSwitchData->IdtTable =3D=3D NULL) || + (StackSwitchData->ExceptionTssDesc =3D=3D NULL) || + (StackSwitchData->ExceptionTss =3D=3D NULL)) { return EFI_INVALID_PARAMETER; } @@ -150,16 +150,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exce= ption // task-state segments. // - if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != =3D 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchD= ata->Ia32.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->= GdtTable)) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia3= 2.ExceptionTssDescSize > - ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.Gdt= TableSize)) + if ((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->Exceptio= nTssDescSize > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -168,20 +168,20 @@ ArchSetupExceptionStack ( // We need one descriptor and one TSS for current task and every excepti= on // specified. // - if (StackSwitchData->Ia32.ExceptionTssDescSize < - sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExc= eptionNumber + 1)) + if (StackSwitchData->ExceptionTssDescSize < + sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->StackSwitchExceptio= nNumber + 1)) { return EFI_INVALID_PARAMETER; } =20 - if (StackSwitchData->Ia32.ExceptionTssSize < - sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitc= hExceptionNumber + 1)) + if (StackSwitchData->ExceptionTssSize < + sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->StackSwitchExce= ptionNumber + 1)) { return EFI_INVALID_PARAMETER; } =20 - TssDesc =3D StackSwitchData->Ia32.ExceptionTssDesc; - Tss =3D StackSwitchData->Ia32.ExceptionTss; + TssDesc =3D StackSwitchData->ExceptionTssDesc; + Tss =3D StackSwitchData->ExceptionTss; =20 // // Initialize new GDT table and/or IDT table, if any @@ -191,20 +191,20 @@ ArchSetupExceptionStack ( =20 GdtSize =3D (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) * - (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) - - (UINTN)(StackSwitchData->Ia32.GdtTable); - if ((UINTN)StackSwitchData->Ia32.GdtTable !=3D Gdtr.Base) { - CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit= + 1); - Gdtr.Base =3D (UINTN)StackSwitchData->Ia32.GdtTable; + (StackSwitchData->StackSwitchExceptionNumber + 1) - + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; Gdtr.Limit =3D (UINT16)GdtSize - 1; } =20 - if ((UINTN)StackSwitchData->Ia32.IdtTable !=3D Idtr.Base) { - Idtr.Base =3D (UINTN)StackSwitchData->Ia32.IdtTable; + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; } =20 - if (StackSwitchData->Ia32.IdtTableSize > 0) { - Idtr.Limit =3D (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit =3D (UINT16)(StackSwitchData->IdtTableSize - 1); } =20 // @@ -226,10 +226,10 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // AsmGetTssTemplateMap (&TemplateMap); - StackTop =3D StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNME= NT; + StackTop =3D StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable =3D StackSwitchData->Ia32.IdtTable; - for (Index =3D 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumb= er; ++Index) { + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->StackSwitchExceptionNumber; += +Index) { TssDesc +=3D 1; Tss +=3D 1; =20 @@ -250,7 +250,7 @@ ArchSetupExceptionStack ( // // Fixup TSS // - Vector =3D StackSwitchData->Ia32.StackSwitchExceptions[Index]; + Vector =3D StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >=3D CPU_EXCEPTION_NUM) || (Vector >=3D (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -270,7 +270,7 @@ ArchSetupExceptionStack ( Tss->FS =3D AsmReadFs (); Tss->GS =3D AsmReadGs (); =20 - StackTop -=3D StackSwitchData->Ia32.KnownGoodStackSize; + StackTop -=3D StackSwitchData->KnownGoodStackSize; =20 // // Update IDT to use Task Gate for given exception @@ -290,7 +290,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdt= r.Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Bas= e)); =20 // // Publish IDT diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index fe8d02d3e4..5952295126 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -236,18 +236,18 @@ InitializeSeparateExceptionStacks ( NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); =20 AsmReadIdtr (&Idtr); - EssData.X64.KnownGoodStackTop =3D StackTop; - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D NewGdtTable; - EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limi= t + 1; - EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + EssData.KnownGoodStackTop =3D StackTop; + EssData.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable =3D (VOID *)Idtr.Base; + EssData.IdtTableSize =3D Idtr.Limit + 1; + EssData.GdtTable =3D NewGdtTable; + EssData.GdtTableSize =3D CPU_TSS_DESC_SIZE + Gdtr.Limit + = 1; + EssData.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 + CP= U_TSS_DESC_SIZE; + EssData.ExceptionTssSize =3D CPU_TSS_SIZE; =20 return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index ff0dde4f12..c14ac66c43 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -136,15 +136,15 @@ ArchSetupExceptionStack ( UINTN GdtSize; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->X64.KnownGoodStackTop =3D=3D 0) || - (StackSwitchData->X64.KnownGoodStackSize =3D=3D 0) || - (StackSwitchData->X64.StackSwitchExceptions =3D=3D NULL) || - (StackSwitchData->X64.StackSwitchExceptionNumber =3D=3D 0) || - (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM= ) || - (StackSwitchData->X64.GdtTable =3D=3D NULL) || - (StackSwitchData->X64.IdtTable =3D=3D NULL) || - (StackSwitchData->X64.ExceptionTssDesc =3D=3D NULL) || - (StackSwitchData->X64.ExceptionTss =3D=3D NULL)) + (StackSwitchData->KnownGoodStackTop =3D=3D 0) || + (StackSwitchData->KnownGoodStackSize =3D=3D 0) || + (StackSwitchData->StackSwitchExceptions =3D=3D NULL) || + (StackSwitchData->StackSwitchExceptionNumber =3D=3D 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable =3D=3D NULL) || + (StackSwitchData->IdtTable =3D=3D NULL) || + (StackSwitchData->ExceptionTssDesc =3D=3D NULL) || + (StackSwitchData->ExceptionTss =3D=3D NULL)) { return EFI_INVALID_PARAMETER; } @@ -154,16 +154,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exce= ption // task-state segments. // - if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != =3D 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { return EFI_INVALID_PARAMETER; } =20 - if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchDa= ta->X64.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->= GdtTable)) { return EFI_INVALID_PARAMETER; } =20 - if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64= .ExceptionTssDescSize) > - ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTa= bleSize)) + if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->Excepti= onTssDescSize) > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -171,20 +171,20 @@ ArchSetupExceptionStack ( // // One task gate descriptor and one task-state segment are needed. // - if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIP= TOR)) { + if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)= ) { return EFI_INVALID_PARAMETER; } =20 - if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGM= ENT)) { + if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)= ) { return EFI_INVALID_PARAMETER; } =20 // // Interrupt stack table supports only 7 vectors. // - TssDesc =3D StackSwitchData->X64.ExceptionTssDesc; - Tss =3D StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->I= ST)) { + TssDesc =3D StackSwitchData->ExceptionTssDesc; + Tss =3D StackSwitchData->ExceptionTss; + if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST))= { return EFI_INVALID_PARAMETER; } =20 @@ -195,19 +195,19 @@ ArchSetupExceptionStack ( AsmReadGdtr (&Gdtr); =20 GdtSize =3D (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) - - (UINTN)(StackSwitchData->X64.GdtTable); - if ((UINTN)StackSwitchData->X64.GdtTable !=3D Gdtr.Base) { - CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit = + 1); - Gdtr.Base =3D (UINTN)StackSwitchData->X64.GdtTable; + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; Gdtr.Limit =3D (UINT16)GdtSize - 1; } =20 - if ((UINTN)StackSwitchData->X64.IdtTable !=3D Idtr.Base) { - Idtr.Base =3D (UINTN)StackSwitchData->X64.IdtTable; + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; } =20 - if (StackSwitchData->X64.IdtTableSize > 0) { - Idtr.Limit =3D (UINT16)(StackSwitchData->X64.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit =3D (UINT16)(StackSwitchData->IdtTableSize - 1); } =20 // @@ -231,20 +231,20 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // ZeroMem (Tss, sizeof (*Tss)); - StackTop =3D StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMEN= T; + StackTop =3D StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable =3D StackSwitchData->X64.IdtTable; - for (Index =3D 0; Index < StackSwitchData->X64.StackSwitchExceptionNumbe= r; ++Index) { + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->StackSwitchExceptionNumber; += +Index) { // // Fixup IST // Tss->IST[Index] =3D StackTop; - StackTop -=3D StackSwitchData->X64.KnownGoodStackSize; + StackTop -=3D StackSwitchData->KnownGoodStackSize; =20 // // Set the IST field to enable corresponding IST // - Vector =3D StackSwitchData->X64.StackSwitchExceptions[Index]; + Vector =3D StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >=3D CPU_EXCEPTION_NUM) || (Vector >=3D (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -262,7 +262,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr= .Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Bas= e)); =20 // // Publish IDT --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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