From nobody Tue Apr 16 20:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92124+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92124+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659658815; cv=none; d=zohomail.com; s=zohoarc; b=mUIzvGRv51OJrT87ngwjIR3P9qYXXewRfWmWCb1dtpxf3EAO3OVNCVdOQcqUQFxRGHAmEXk75qbtpYdey3PFU9qXeY/py/eDWwP5T/4Oq7sQIi9zykgRR/Z1HN+4axuDVRYaxNe30HwhlBHtaGBztodM2ox7RAdvtYpHSBCRW2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659658815; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YjMvVknqbzHgg1SttVgOdaLunPNnOG73Mdxct3BxIww=; b=HWqauwiyZd20yewqkMbq0awRThubod/i+5dlMN69aLyg7wuuP+pFj39+8H52ixFs2CiqjpyCvuads7ycNRz4sZAJVABD9ulNTC3vEwwR+pf/SzjiLCMohE8ibFUPJ4k6+X0ePESVoEl2hPARv/xjIsrhVfnXllfO3USWwVUrEyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92124+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659658815336261.00130766750556; Thu, 4 Aug 2022 17:20:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RJjTYY1788612xC6m40usxYF; Thu, 04 Aug 2022 17:20:15 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.1465.1659658812988341838 for ; Thu, 04 Aug 2022 17:20:14 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="287647673" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287647673" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:14 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671497592" X-Received: from jwiegert-mobl1.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.235.240]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:09 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH 1/4] IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface. Date: Thu, 4 Aug 2022 17:19:48 -0700 Message-Id: <20220805001951.3687-2-chasel.chiu@intel.com> In-Reply-To: <20220805001951.3687-1-chasel.chiu@intel.com> References: <20220805001951.3687-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: C8H0AgmDoj403LALIY3ZPcZzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659658815; bh=KzBOxLhGJyPDOOxDcuTWJUh0vG5OJmgi649eWruWOyE=; h=Cc:Date:From:Reply-To:Subject:To; b=cDQ7lPwnwIY+vRNB/AxoFFd0mZR/iGIxyjJJ6RcuMxWOAJ9IweVFAmz7BewJBRGm1TY kykJvsW0Jhf7w2iiifOh//DctLoau3SqO5ilD2SkOHLXpV2aQDiJ8gE0vEWrCeakUJFmL H/3yoX2QcOq7XcoMc4XZWHQrUnpVM+TOvlw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659658817527100012 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Provide FSP 2.4 MultiPhase interface and scripts support. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c | 176 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++ IntelFsp2Pkg/Include/FspEas/FspApi.h | 62 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- IntelFsp2Pkg/Include/FspGlobalData.h | 5 += +++- IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h | 54 += +++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/IntelFsp2Pkg.dec | 12 += +++++++++-- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 4 += +++ IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf | 50 += +++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/Tools/SplitFspBin.py | 48 += ++++++++++++++++++++++++----------------------- 8 files changed, 383 insertions(+), 28 deletions(-) diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c b= /IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c new file mode 100644 index 0000000000..728ac4c2c1 --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c @@ -0,0 +1,176 @@ +/** @file + Null instance of Platform Sec Lib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +FspMultiPhaseSwitchStack ( + ) +{ + SetFspApiReturnStatus (EFI_SUCCESS); + Pei2LoaderSwitchStack (); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FspVariableRequestSwitchStack ( + IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPara= ms + ) +{ + FSP_GLOBAL_DATA *FspData; + + FspData =3D GetFspGlobalDataPointer (); + if (((UINTN)FspData =3D=3D 0) || ((UINTN)FspData =3D=3D 0xFFFFFFFF)) { + return EFI_UNSUPPORTED; + } + + FspData->VariableRequestParameterPtr =3D (VOID *)FspVariableRequestParam= s; + SetFspApiReturnStatus (FSP_STATUS_VARIABLE_REQUEST); + Pei2LoaderSwitchStack (); + + return EFI_SUCCESS; +} + +/** + This function supports FspMultiPhase implementation. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseWorker ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + FSP_MULTI_PHASE_PARAMS *FspMultiPhaseParams; + FSP_GLOBAL_DATA *FspData; + FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS *FspMultiPhaseGetNumber; + BOOLEAN FspDataValid; + + FspDataValid =3D TRUE; + FspData =3D GetFspGlobalDataPointer (); + if (((UINTN)FspData =3D=3D 0) || ((UINTN)FspData =3D=3D 0xFFFFFFFF)) { + FspDataValid =3D FALSE; + } + + // + // It is required that FspData->NumberOfPhases to be reset to 0 after + // current FSP component finished. + // The next component FspData->NumberOfPhases will only be re-initialize= d when FspData->NumberOfPhases =3D 0 + // + if ((FspDataValid =3D=3D TRUE) && (FspData->NumberOfPhases =3D=3D 0)) { + FspData->NumberOfPhases =3D PcdGet32 (PcdMultiPhaseNumberOfPhases); + FspData->PhasesExecuted =3D 0; + } + + FspMultiPhaseParams =3D (FSP_MULTI_PHASE_PARAMS *)ApiParam; + + if (FspDataValid =3D=3D FALSE) { + return EFI_DEVICE_ERROR; + } else { + switch (FspMultiPhaseParams->MultiPhaseAction) { + case EnumMultiPhaseGetNumberOfPhases: + if ((FspMultiPhaseParams->MultiPhaseParamPtr =3D=3D NULL) || (FspM= ultiPhaseParams->PhaseIndex !=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + FspMultiPhaseGetNumber =3D (FSP_MULTI_PHASE_GET_NU= MBER_OF_PHASES_PARAMS *)FspMultiPhaseParams->MultiPhaseParamPtr; + FspMultiPhaseGetNumber->NumberOfPhases =3D FspData->NumberOfPhases; + FspMultiPhaseGetNumber->PhasesExecuted =3D FspData->PhasesExecuted; + break; + + case EnumMultiPhaseExecutePhase: + if ((FspMultiPhaseParams->PhaseIndex > FspData->PhasesExecuted) &&= (FspMultiPhaseParams->PhaseIndex <=3D FspData->NumberOfPhases)) { + FspData->PhasesExecuted =3D FspMultiPhaseParams->PhaseIndex; + return Loader2PeiSwitchStack (); + } else { + return EFI_INVALID_PARAMETER; + } + + break; + + case EnumMultiPhaseGetVariableRequestInfo: + // + // return variable request info + // + FspMultiPhaseParams->MultiPhaseParamPtr =3D FspData->VariableReque= stParameterPtr; + break; + + case EnumMultiPhaseCompleteVariableRequest: + // + // retrieve complete variable request params + // + FspData->VariableRequestParameterPtr =3D FspMultiPhaseParams->Mult= iPhaseParamPtr; + return Loader2PeiSwitchStack (); + break; + + default: + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + This function handles FspMultiPhaseMemInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseMemInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + return FspMultiPhaseWorker (ApiIdx, ApiParam); +} + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandlerV2 ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + return FspMultiPhaseWorker (ApiIdx, ApiParam); +} diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 361e916b5f..af42d7f707 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -487,10 +487,38 @@ typedef struct { /// Action definition for FspMultiPhaseSiInit API /// typedef enum { - EnumMultiPhaseGetNumberOfPhases =3D 0x0, - EnumMultiPhaseExecutePhase =3D 0x1 + EnumMultiPhaseGetNumberOfPhases =3D 0x0, + EnumMultiPhaseExecutePhase =3D 0x1, + EnumMultiPhaseGetVariableRequestInfo =3D 0x2, + EnumMultiPhaseCompleteVariableRequest =3D 0x3 } FSP_MULTI_PHASE_ACTION; =20 +typedef enum { + EnumFspVariableRequestGetVariable =3D 0x0, + EnumFspVariableRequestGetNextVariableName =3D 0x1, + EnumFspVariableRequestSetVariable =3D 0x2, + EnumFspVariableRequestQueryVariableInfo =3D 0x3 +} FSP_VARIABLE_REQUEST_TYPE; + +#pragma pack(16) +typedef struct { + IN FSP_VARIABLE_REQUEST_TYPE VariableRequest; + IN OUT CHAR16 *VariableName; + IN OUT UINT64 *VariableNameSize; + IN OUT EFI_GUID *VariableGuid; + IN OUT UINT32 *Attributes; + IN OUT UINT64 *DataSize; + IN OUT VOID *Data; + OUT UINT64 *MaximumVariableStorageSize; + OUT UINT64 *RemainingVariableStorageSize; + OUT UINT64 *MaximumVariableSize; +} FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS; + +typedef struct { + EFI_STATUS VariableRequestStatus; +} FSP_MULTI_PHASE_COMPLETE_VARIABLE_REQUEST_PARAMS; +#pragma pack() + /// /// Data structure returned by FSP when bootloader calling /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) @@ -690,4 +718,34 @@ EFI_STATUS IN VOID *FspiUpdDataPtr ); =20 +/** + This FSP API provides multi-phase memory and silicon initialization, whi= ch brings greater modularity to the existing + FspMemoryInit() and FspSiliconInit() API. Increased modularity is achiev= ed by adding an extra API to FSP-M and FSP-S. + This allows the bootloader to add board specific initialization steps th= roughout the MemoryInit and SiliconInit flows as needed. + The FspMemoryInit() API is always called before FspMultiPhaseMemInit(); = it is the first phase of memory initialization. Similarly, + the FspSiliconInit() API is always called before FspMultiPhaseSiInit(); = it is the first phase of silicon initialization. + After the first phase, subsequent phases are invoked by calling the FspM= ultiPhaseMem/SiInit() API. + The FspMultiPhaseMemInit() API may only be called after the FspMemoryIni= t() API and before the FspSiliconInit() API; + or in the case that FSP-T is being used, before the TempRamExit() API. T= he FspMultiPhaseSiInit() API may only be called after + the FspSiliconInit() API and before NotifyPhase() API; or in the case th= at FSP-I is being used, before the FspSmmInit() API. + The multi-phase APIs may not be called at any other time. + + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNu= mberOfPhases: + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr will contain + how many phases supported by F= SP. + For action - EnumMultiPhaseExecu= tePhase: + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr shall be NULL. + @retval EFI_SUCCESS FSP execution environment was in= itialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were = not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIRED_* A reset is required. These statu= s codes will not be returned during S3. + @retval FSP_STATUS_VARIABLE_REQUEST A variable request has been made= by FSP that needs boot loader handling. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MULTI_PHASE_INIT)( + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseInitParamPtr + ); + #endif diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 32c6d460e4..81813df3ce 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -12,7 +12,7 @@ =20 #define FSP_IN_API_MODE 0 #define FSP_IN_DISPATCH_MODE 1 -#define FSP_GLOBAL_DATA_VERSION 0x2 +#define FSP_GLOBAL_DATA_VERSION 0x3 =20 #pragma pack(1) =20 @@ -25,6 +25,7 @@ typedef enum { FspSiliconInitApiIndex, FspMultiPhaseSiInitApiIndex, FspSmmInitApiIndex, + FspMultiPhaseMemInitApiIndex, FspApiIndexMax } FSP_API_INDEX; =20 @@ -82,6 +83,8 @@ typedef struct { VOID *FunctionParameterPtr; FSP_INFO_HEADER *FspInfoHeader; VOID *UpdDataPtr; + VOID *FspHobListPtr; + VOID *VariableRequestParameterPtr; /// /// End of UINTN and pointer section /// At this point, next field offset must be either *0h or *8h to diff --git a/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h b/IntelFsp2Pkg= /Include/Library/FspMultiPhaseLib.h new file mode 100644 index 0000000000..7ac4e197d9 --- /dev/null +++ b/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h @@ -0,0 +1,54 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_SEC_PLATFORM_LIB_H_ +#define _FSP_SEC_PLATFORM_LIB_H_ + +EFI_STATUS +EFIAPI +FspMultiPhaseSwitchStack ( + ); + +EFI_STATUS +EFIAPI +FspVariableRequestSwitchStack ( + IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPara= ms + ); + +/** + This function handles FspMultiPhaseMemInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + + @retval EFI_SUCCESS FSP execution was successful. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseMemInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandlerV2 ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +#endif diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 2d3eb708b9..d1c3d3ee7b 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -37,6 +37,9 @@ ## @libraryclass Provides FSP platform sec related actions. FspSecPlatformLib|Include/Library/FspSecPlatformLib.h =20 + ## @libraryclass Provides FSP MultiPhase service functions. + FspMultiPhaseLib|Include/Library/FspMultiPhaseLib.h + [Ppis] # # PPI to indicate FSP is ready to enter notify phase @@ -112,5 +115,10 @@ gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UI= NT32|0x10000006 =20 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx] - gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT3= 2|0x46530000 - gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT3= 2|0x46530100 + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT= 32|0x46530000 + gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT= 32|0x46530100 + # + # Different FSP Components may have different NumberOfPhases which can b= e defined + # by each FspSecCore module from DSC. + # + gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases |0x00000000|UINT= 32|0x46530101 diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index b2d7867880..0713f0028d 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -45,6 +45,7 @@ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSe= cPlatformLibNull.inf + FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiP= haseLib.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf @@ -64,12 +65,15 @@ IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.i= nf + IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf =20 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf + IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf + IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf =20 [PcdsFixedAtBuild.common] diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib= .inf b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf new file mode 100644 index 0000000000..a79f6aecda --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf @@ -0,0 +1,50 @@ +## @file +# FSP MultiPhase Lib. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseFspMultiPhaseLib + FILE_GUID =3D C128CADC-623E-4E41-97CB-A7138E627460 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspMultiPhaseLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspMultiPhaseLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + +[Pcd] + gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases # CONSUMES diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFs= pBin.py index ddabab7d8c..419e5ba985 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -103,29 +103,31 @@ class FSP_COMMON_HEADER(Structure): =20 class FSP_INFORMATION_HEADER(Structure): _fields_ =3D [ - ('Signature', ARRAY(c_char, 4)), - ('HeaderLength', c_uint32), - ('Reserved1', c_uint16), - ('SpecVersion', c_uint8), - ('HeaderRevision', c_uint8), - ('ImageRevision', c_uint32), - ('ImageId', ARRAY(c_char, 8)), - ('ImageSize', c_uint32), - ('ImageBase', c_uint32), - ('ImageAttribute', c_uint16), - ('ComponentAttribute', c_uint16), - ('CfgRegionOffset', c_uint32), - ('CfgRegionSize', c_uint32), - ('Reserved2', c_uint32), - ('TempRamInitEntryOffset', c_uint32), - ('Reserved3', c_uint32), - ('NotifyPhaseEntryOffset', c_uint32), - ('FspMemoryInitEntryOffset', c_uint32), - ('TempRamExitEntryOffset', c_uint32), - ('FspSiliconInitEntryOffset', c_uint32), - ('FspMultiPhaseSiInitEntryOffset', c_uint32), - ('ExtendedImageRevision', c_uint16), - ('Reserved4', c_uint16) + ('Signature', ARRAY(c_char, 4)), + ('HeaderLength', c_uint32), + ('Reserved1', c_uint16), + ('SpecVersion', c_uint8), + ('HeaderRevision', c_uint8), + ('ImageRevision', c_uint32), + ('ImageId', ARRAY(c_char, 8)), + ('ImageSize', c_uint32), + ('ImageBase', c_uint32), + ('ImageAttribute', c_uint16), + ('ComponentAttribute', c_uint16), + ('CfgRegionOffset', c_uint32), + ('CfgRegionSize', c_uint32), + ('Reserved2', c_uint32), + ('TempRamInitEntryOffset', c_uint32), + ('Reserved3', c_uint32), + ('NotifyPhaseEntryOffset', c_uint32), + ('FspMemoryInitEntryOffset', c_uint32), + ('TempRamExitEntryOffset', c_uint32), + ('FspSiliconInitEntryOffset', c_uint32), + ('FspMultiPhaseSiInitEntryOffset', c_uint32), + ('ExtendedImageRevision', c_uint16), + ('Reserved4', c_uint16), + ('FspMultiPhaseMemInitEntryOffset', c_uint32), + ('FspSmmInitEntryOffset', c_uint32) ] =20 class FSP_PATCH_TABLE(Structure): --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92124): https://edk2.groups.io/g/devel/message/92124 Mute This Topic: https://groups.io/mt/92826132/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 16 20:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92125+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92125+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659658815; cv=none; d=zohomail.com; s=zohoarc; b=Jf2er1cEPb7YxufljAbjMIduTtOsrkaDtpNqmRRXCd6403jhQdQwPiDULXXGkxkaOKtt5fydcc6NPCYzP/FkZWy1qhJBqlc8lkRMBJ/KmbNgv2LYDv9a7nPxmFApgawoXxt5dbao6QFB67TAkLLFU7aJgTlp0uilh23sIU+prTU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659658815; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YMVlDOhVBFYrcPMNjgb5S1LJxY/hYyuTRLByROg4AJk=; b=l9RHmikYK6yk34qmJMd+0ZM9rhc12YE9WP1cErLLlO7CjqR47CaCuyaLD5KlnbYp6wtEJbHM6Q/6XIx3NcnXoZmcvB/dv2a5c4bgdHVRi8rshCIE+ZR+uOzPYrg3XkFKuIU4Uo1jMFGIod8G1fzvBNXbPmBCswCINxDjdMY6b3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92125+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659658815928175.64547700570097; Thu, 4 Aug 2022 17:20:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2ViaYY1788612xBcxR0AmL24; Thu, 04 Aug 2022 17:20:15 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.1465.1659658812988341838 for ; Thu, 04 Aug 2022 17:20:15 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="287647676" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287647676" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:14 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671497596" X-Received: from jwiegert-mobl1.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.235.240]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:10 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH 2/4] IntelFsp2WrapperPkg: Add FSP 2.4 MultiPhase interface. Date: Thu, 4 Aug 2022 17:19:49 -0700 Message-Id: <20220805001951.3687-3-chasel.chiu@intel.com> In-Reply-To: <20220805001951.3687-1-chasel.chiu@intel.com> References: <20220805001951.3687-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: lBSmDYtipguOJBJAy3pRoAbIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659658815; bh=y+StTU5CXkmnsMGDW6I+yQOWLnNyYY/edSEq4BVsiBM=; h=Cc:Date:From:Reply-To:Subject:To; b=KxHAxYXSyXJhQinmWZnnDdJlwm16HO7GTuM+W54GcwgnUbYKuyo0GgiwhiHthvFcdIi /KnE6MfFTSkaoG2q8ISK3Sa/vvW5tT27C28cbkAazpFeZc6nBAoShOd3g1+fG32YdMq4e eCcNY9mcBj98z1jidGRNbGWbQbMhK7eg+TU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659658817480100009 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Provide FSP 2.4 MultiPhase wrapper support library. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMu= ltiPhaseProcessLib.c | 337 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2WrapperPkg/Include/Library/FspWrapperMultiPhaseProcessLib.h = | 38 ++++++++++++++++++++++++++++++++++++++ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec = | 6 +++++- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc = | 4 +++- IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/FspWrapperMulti= PhaseProcessLib.inf | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 430 insertions(+), 2 deletions(-) diff --git a/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/Pei= FspWrapperMultiPhaseProcessLib.c b/IntelFsp2WrapperPkg/Library/FspWrapperMu= ltiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c new file mode 100644 index 0000000000..25fac73bac --- /dev/null +++ b/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrap= perMultiPhaseProcessLib.c @@ -0,0 +1,337 @@ +/** @file + Support FSP MultiPhase process. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Execute 32-bit FSP API entry code. + + @param[in] Function The 32bit code entry to be executed. + @param[in] Param1 The first parameter to pass to 32bit code. + @param[in] Param2 The second parameter to pass to 32bit code. + + @return EFI_STATUS. +**/ +EFI_STATUS +Execute32BitCode ( + IN UINT64 Function, + IN UINT64 Param1, + IN UINT64 Param2 + ); + +/** + Execute 64-bit FSP API entry code. + + @param[in] Function The 64bit code entry to be executed. + @param[in] Param1 The first parameter to pass to 64bit code. + @param[in] Param2 The second parameter to pass to 64bit code. + + @return EFI_STATUS. +**/ +EFI_STATUS +Execute64BitCode ( + IN UINT64 Function, + IN UINT64 Param1, + IN UINT64 Param2 + ); + +/** + Call FspsMultiPhase API. + + @param[in] FspsMultiPhaseParams - Parameters for MultiPhase API. + + @return EFI_UNSUPPORTED - the requested FspsMultiPhase API is not suppo= rted. + @return EFI_DEVICE_ERROR - the FSP header was not found. + @return EFI status returned by FspsMultiPhase API. +**/ +EFI_STATUS +EFIAPI +CallFspMultiPhaseEntry ( + IN VOID *FspMultiPhaseParams, + IN OUT VOID **FspHobListPtr, + IN UINT8 ComponentIndex + ) +{ + FSP_INFO_HEADER *FspHeader; + // + // FSP_MULTI_PHASE_INIT and FSP_MULTI_PHASE_SI_INIT API functions having= same prototype. + // + UINTN FspMultiPhaseApiEntry; + UINTN FspMultiPhaseApiOffset; + EFI_STATUS Status; + BOOLEAN InterruptState; + + if (ComponentIndex =3D=3D FspMultiPhaseMemInitApiIndex) { + FspHeader =3D (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspmBa= seAddress)); + if (FspHeader =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + FspMultiPhaseApiOffset =3D FspHeader->FspMultiPhaseMemInitEntryOffset; + } else if (ComponentIndex =3D=3D FspMultiPhaseSiInitApiIndex) { + FspHeader =3D (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspsBa= seAddress)); + if (FspHeader =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + FspMultiPhaseApiOffset =3D FspHeader->FspMultiPhaseSiInitEntryOffset; + } + + if (FspMultiPhaseApiOffset =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + FspMultiPhaseApiEntry =3D FspHeader->ImageBase + FspMultiPhaseApiOffset; + InterruptState =3D SaveAndDisableInterrupts (); + if ((FspHeader->ImageAttribute & BIT2) =3D=3D 0) { + // BIT2: IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT + Status =3D Execute32BitCode ((UINTN)FspMultiPhaseApiEntry, (UINTN)FspM= ultiPhaseParams, (UINTN)NULL); + } else { + Status =3D Execute64BitCode ((UINTN)FspMultiPhaseApiEntry, (UINTN)FspM= ultiPhaseParams, (UINTN)NULL); + } + + SetInterruptState (InterruptState); + + DEBUG ((DEBUG_ERROR, "CallFspMultiPhaseEntry return Status %r \n", Statu= s)); + + return Status; +} + +/** + FSP Wrapper Variable Request Handler + + @retval EFI_UNSUPPORTED FSP Wrapper cannot support the specific variab= le request + @retval EFI_STATUS Return FSP returned status + +**/ +EFI_STATUS +EFIAPI +FspWrapperVariableRequestHandler ( + IN OUT VOID **FspHobListPtr, + IN UINT8 ComponentIndex + ) +{ + EFI_STATUS Status; + FSP_MULTI_PHASE_PARAMS FspMultiPhaseParams; + FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPar= ams; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariablePpi; + EDKII_PEI_VARIABLE_PPI *VariablePpi; + BOOLEAN WriteVariableSupport; + FSP_MULTI_PHASE_COMPLETE_VARIABLE_REQUEST_PARAMS CompleteVariableReques= tParams; + + WriteVariableSupport =3D TRUE; + Status =3D PeiServicesLocatePpi ( + &gEdkiiPeiVariablePpiGuid, + 0, + NULL, + (VOID **)&VariablePpi + ); + if (EFI_ERROR (Status)) { + WriteVariableSupport =3D FALSE; + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&ReadOnlyVariablePpi + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + + Status =3D FSP_STATUS_VARIABLE_REQUEST; + while (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) { + // + // Firstly querry variable request informaiton from FSP. + // + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiPhaseGetVariableRequ= estInfo; + FspMultiPhaseParams.PhaseIndex =3D 0; + Status =3D CallFspMultiPhaseEntry (&FspM= ultiPhaseParams, FspHobListPtr, ComponentIndex); + ASSERT_EFI_ERROR (Status); + // + // FSP should output this pointer for variable request information. + // + FspVariableRequestParams =3D (FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PA= RAMS *)FspMultiPhaseParams.MultiPhaseParamPtr; + switch (FspVariableRequestParams->VariableRequest) { + case EnumFspVariableRequestGetVariable: + if (WriteVariableSupport) { + Status =3D VariablePpi->GetVariable ( + VariablePpi, + FspVariableRequestParams->VariableName, + FspVariableRequestParams->VariableGuid, + FspVariableRequestParams->Attributes, + (UINTN *)FspVariableRequestParams->DataS= ize, + FspVariableRequestParams->Data + ); + } else { + Status =3D ReadOnlyVariablePpi->GetVariable ( + ReadOnlyVariablePpi, + FspVariableRequestParams->Variab= leName, + FspVariableRequestParams->Variab= leGuid, + FspVariableRequestParams->Attrib= utes, + (UINTN *)FspVariableRequestParam= s->DataSize, + FspVariableRequestParams->Data + ); + } + + CompleteVariableRequestParams.VariableRequestStatus =3D Status; + FspMultiPhaseParams.MultiPhaseParamPtr =3D (VOID *)&C= ompleteVariableRequestParams; + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiP= haseCompleteVariableRequest; + Status =3D CallFspMul= tiPhaseEntry (&FspMultiPhaseParams, FspHobListPtr, ComponentIndex); + break; + + case EnumFspVariableRequestSetVariable: + if (WriteVariableSupport) { + Status =3D VariablePpi->SetVariable ( + VariablePpi, + FspVariableRequestParams->VariableName, + FspVariableRequestParams->VariableGuid, + *FspVariableRequestParams->Attributes, + (UINTN)*FspVariableRequestParams->DataSi= ze, + FspVariableRequestParams->Data + ); + } else { + return EFI_UNSUPPORTED; + } + + CompleteVariableRequestParams.VariableRequestStatus =3D Status; + FspMultiPhaseParams.MultiPhaseParamPtr =3D (VOID *)&C= ompleteVariableRequestParams; + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiP= haseCompleteVariableRequest; + Status =3D CallFspMul= tiPhaseEntry (&FspMultiPhaseParams, FspHobListPtr, ComponentIndex); + break; + + case EnumFspVariableRequestGetNextVariableName: + if (WriteVariableSupport) { + Status =3D VariablePpi->GetNextVariableName ( + VariablePpi, + (UINTN *)FspVariableRequestParams->Varia= bleNameSize, + FspVariableRequestParams->VariableName, + FspVariableRequestParams->VariableGuid + ); + } else { + Status =3D ReadOnlyVariablePpi->NextVariableName ( + ReadOnlyVariablePpi, + (UINTN *)FspVariableRequestParam= s->VariableNameSize, + FspVariableRequestParams->Variab= leName, + FspVariableRequestParams->Variab= leGuid + ); + } + + CompleteVariableRequestParams.VariableRequestStatus =3D Status; + FspMultiPhaseParams.MultiPhaseParamPtr =3D (VOID *)&C= ompleteVariableRequestParams; + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiP= haseCompleteVariableRequest; + Status =3D CallFspMul= tiPhaseEntry (&FspMultiPhaseParams, FspHobListPtr, ComponentIndex); + break; + + case EnumFspVariableRequestQueryVariableInfo: + if (WriteVariableSupport) { + Status =3D VariablePpi->QueryVariableInfo ( + VariablePpi, + *FspVariableRequestParams->Attributes, + FspVariableRequestParams->MaximumVariabl= eStorageSize, + FspVariableRequestParams->RemainingVaria= bleStorageSize, + FspVariableRequestParams->MaximumVariabl= eSize + ); + } else { + return EFI_UNSUPPORTED; + } + + CompleteVariableRequestParams.VariableRequestStatus =3D Status; + FspMultiPhaseParams.MultiPhaseParamPtr =3D (VOID *)&C= ompleteVariableRequestParams; + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiP= haseCompleteVariableRequest; + Status =3D CallFspMul= tiPhaseEntry (&FspMultiPhaseParams, FspHobListPtr, ComponentIndex); + break; + + default: + DEBUG ((DEBUG_ERROR, "Unknown VariableRequest type!\n")); + Status =3D EFI_UNSUPPORTED; + break; + } + } + + return Status; +} + +/** + FSP Wrapper MultiPhase Handler + + @retval EFI_STATUS Always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +FspWrapperMultiPhaseHandler ( + IN OUT VOID **FspHobListPtr, + IN UINT8 ComponentIndex + ) +{ + EFI_STATUS Status; + FSP_MULTI_PHASE_PARAMS FspMultiPhaseParams; + FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS FspMultiPhaseGetNumber; + UINT32 Index; + UINT32 NumOfPhases; + + // + // Firstly querry FSP for how many phases supported. + // + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiPhaseGetNumberOfPhas= es; + FspMultiPhaseParams.PhaseIndex =3D 0; + FspMultiPhaseParams.MultiPhaseParamPtr =3D (VOID *)&FspMultiPhaseGetNumb= er; + Status =3D CallFspMultiPhaseEntry (&FspM= ultiPhaseParams, FspHobListPtr, ComponentIndex); + if (Status =3D=3D EFI_UNSUPPORTED) { + // + // MultiPhase API was not supported + // + return Status; + } else { + ASSERT_EFI_ERROR (Status); + } + + NumOfPhases =3D FspMultiPhaseGetNumber.NumberOfPhases; + + for (Index =3D 1; Index <=3D NumOfPhases; Index++) { + DEBUG ((DEBUG_ERROR, "MultiPhase Index/NumOfPhases =3D %d of %d\n", In= dex, NumOfPhases)); + // + // Platform handling can be added here to take care specific actions f= or each phase + // before returning control back to FSP. + // + FspMultiPhaseParams.MultiPhaseAction =3D EnumMultiPhaseExecutePhase; + FspMultiPhaseParams.PhaseIndex =3D Index; + FspMultiPhaseParams.MultiPhaseParamPtr =3D NULL; + Status =3D CallFspMultiPhaseEntry (&Fs= pMultiPhaseParams, FspHobListPtr, ComponentIndex); + + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) { + // + // call to Variable request handler + // + FspWrapperVariableRequestHandler (FspHobListPtr, ComponentIndex); + } + + // + // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED stat= us + // + if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_S= TATUS_RESET_REQUIRED_8)) { + DEBUG ((DEBUG_INFO, "FspMultiPhaseApi-0x%x requested reset %r\n", Co= mponentIndex, Status)); + CallFspWrapperResetSystem ((UINTN)Status); + } + + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; +} diff --git a/IntelFsp2WrapperPkg/Include/Library/FspWrapperMultiPhaseProces= sLib.h b/IntelFsp2WrapperPkg/Include/Library/FspWrapperMultiPhaseProcessLib= .h new file mode 100644 index 0000000000..9a3b6cf9e3 --- /dev/null +++ b/IntelFsp2WrapperPkg/Include/Library/FspWrapperMultiPhaseProcessLib.h @@ -0,0 +1,38 @@ +/** @file + Provide FSP wrapper MultiPhase handling functions. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FSP_WRAPPER_MULTI_PHASE_PROCESS_LIB_H__ +#define __FSP_WRAPPER_MULTI_PHASE_PROCESS_LIB_H__ + +/** + It's a reference code for how to handle FSP Variable Request API. + + @retval EFI_STATUS Always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +FspWrapperVariableRequestHandler ( + IN OUT VOID **FspHobListPtr, + IN UINT8 ComponentIndex + ); + +/** + It's a reference code for how to handle FSP MultiPhase API. + + @retval EFI_STATUS Always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +FspWrapperMultiPhaseHandler ( + IN OUT VOID **FspHobListPtr, + IN UINT8 ComponentIndex + ); + +#endif diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2Wrapper= Pkg/IntelFsp2WrapperPkg.dec index c43b0c2267..a002b1d742 100644 --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec @@ -1,7 +1,7 @@ ## @file # Provides drivers and definitions to support fsp in EDKII bios. # -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -28,6 +28,10 @@ =20 ## @libraryclass Provide FSP TPM measurement related function. FspMeasurementLib|Include/Library/FspMeasurementLib.h + + ## @libraryclass Provide MultiPhase handling related functions. + FspWrapperMultiPhaseProcessLib|Include/Library/FspWrapperMultiPhaseProce= ssLib.h + [Guids] # # GUID defined in package diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc b/IntelFsp2Wrapper= Pkg/IntelFsp2WrapperPkg.dsc index 21e089000e..a191185bea 100644 --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc @@ -1,7 +1,7 @@ ## @file # Provides drivers and definitions to support fsp in EDKII bios. # -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -48,6 +48,7 @@ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiTestLi= bNull/BaseFspWrapperApiTestLibNull.inf FspMeasurementLib|IntelFsp2WrapperPkg/Library/BaseFspMeasurementLib/Base= FspMeasurementLib.inf + FspWrapperMultiPhaseProcessLib|IntelFsp2WrapperPkg/Library/FspWrapperMul= tiPhaseProcessLib/FspWrapperMultiPhaseProcessLib.inf =20 # FSP platform sample FspWrapperPlatformLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatform= LibSample/BaseFspWrapperPlatformLibSample.inf @@ -91,6 +92,7 @@ IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/BaseFspWrapp= erPlatformLibSample.inf IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/FspWrapperMul= tiPhaseProcessLib.inf =20 [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f diff --git a/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/Fsp= WrapperMultiPhaseProcessLib.inf b/IntelFsp2WrapperPkg/Library/FspWrapperMul= tiPhaseProcessLib/FspWrapperMultiPhaseProcessLib.inf new file mode 100644 index 0000000000..6186ec6976 --- /dev/null +++ b/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/FspWrapper= MultiPhaseProcessLib.inf @@ -0,0 +1,47 @@ +## @file +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FspWrapperMultiPhaseProcessLib + FILE_GUID =3D 11E657B7-C3D8-405B-94C5-516840E67B75 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspWrapperMultiPhaseProcessLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + PeiFspWrapperMultiPhaseProcessLib.c + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PcdLib + FspWrapperPlatformLib + PeiServicesLib + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid + gEdkiiPeiVariablePpiGuid + +[Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92125): https://edk2.groups.io/g/devel/message/92125 Mute This Topic: https://groups.io/mt/92826133/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 16 20:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92126+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92126+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659658816; cv=none; d=zohomail.com; s=zohoarc; b=UYWpBjQaMo/Pha/klGsM/KkqPxcfwdJOvLVExtPMUYrqeI0STqT+gON1Rog3wgK8PtnJ99niZjzALRpSHXgQOzPUJV3d5DzyXlWRGb2V12tXntSFPYKTrsQFDhBpLcSsPYpJHIkkOkTDUjwvabr3NmvWb5m33yIkeotUtTvtTf8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659658816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=CljN/H2Ad7+STXFKs3YK2LYYGrv8eyoDsMa+iVH0NRE=; b=KI5O1pAlj+mtv54W9wG7CRdE2EE+amXjWFudv9/6Z+vaDJgS7Sz7e2FHVKliTAp4aqG5j1Bllkg2A1r+RrtsRQ0Zym8ei+OX1hVoAas8NBkDxLFz9CuhQ5Yw/CA57x2nvQyFkfgDpS+AaAsZqablbhY1I5nWOq+y6ziguW/9UuI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92126+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659658816310667.836000180885; Thu, 4 Aug 2022 17:20:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id E0eYYY1788612xtLOWWBWdoW; Thu, 04 Aug 2022 17:20:16 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.1465.1659658812988341838 for ; Thu, 04 Aug 2022 17:20:15 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="287647679" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287647679" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:15 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671497599" X-Received: from jwiegert-mobl1.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.235.240]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:11 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions. Date: Thu, 4 Aug 2022 17:19:50 -0700 Message-Id: <20220805001951.3687-4-chasel.chiu@intel.com> In-Reply-To: <20220805001951.3687-1-chasel.chiu@intel.com> References: <20220805001951.3687-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: vaZfdrpgfqWTL6WGZgpwtcJ6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659658816; bh=BftXBE0iuexZcFLPgur3SCQkpi6Je7rpu+vXnkfvuNM=; h=Cc:Date:From:Reply-To:Subject:To; b=wLg8ONz7rUFvN4bpQP7DQeGoYWdR+qiXm5oXevjsRH4oUNuMVlpq87kRFVc+RXC6URb 5WRcwQutp2/EbUTiyncNVvL7ahHG76cbJOqA+YbGkcO+cTnX+wiASnPqcweOmGgC5IB16 nsNTRx6c2j98zEV+5q/WWLD7A9cJZy3t5sU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659658817486100010 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. For backward compatibility, new INF are created for new modules. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 ++++ IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 9 +++++++++ IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 75 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf | 59 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 304 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm | 101 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 3 +++ IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 303 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm | 108 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 3 +++ 10 files changed, 969 insertions(+) diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index d9085ef51f..11be1f97ca 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -135,6 +135,10 @@ FspGlobalDataInit ( PeiFspData->CoreStack =3D BootLoaderStack; PeiFspData->PerfIdx =3D 2; PeiFspData->PerfSig =3D FSP_PERFORMANCE_DATA_SIGNATURE; + // + // Cache FspHobList pointer passed by bootloader via ApiParameter2 + // + PeiFspData->FspHobListPtr =3D (VOID **)GetFspApiParameter2 (); =20 SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY); =20 diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index 35d223a404..a44fbf2a50 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -69,8 +69,17 @@ FspApiCallingCheck ( Status =3D EFI_UNSUPPORTED; } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, = ApiParam))) { Status =3D EFI_INVALID_PARAMETER; + } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { + // + // Reset MultiPhase NumberOfPhases to zero + // + FspData->NumberOfPhases =3D 0; } } + } else if (ApiIdx =3D=3D FspMultiPhaseMemInitApiIndex) { + if ((FspData =3D=3D NULL) || ((UINTN)FspData =3D=3D MAX_ADDRESS) || ((= UINTN)FspData =3D=3D MAX_UINT32)) { + Status =3D EFI_UNSUPPORTED; + } } else if (ApiIdx =3D=3D FspSmmInitApiIndex) { // // FspSmmInitApiIndex check diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreM.inf new file mode 100644 index 0000000000..e93e176f15 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf @@ -0,0 +1,75 @@ +## @file +# Sec Core for FSP to support MultiPhase (SeparatePhase) MemInitializatio= n. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D Fsp24SecCoreM + FILE_GUID =3D C5BC0719-4A23-4F6E-94DA-05FB6A0DFA9C + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + SecMain.c + SecMain.h + SecFsp.c + SecFsp.h + SecFspApiChk.c + +[Sources.IA32] + Ia32/Stack.nasm + Ia32/Fsp24ApiEntryM.nasm + Ia32/FspApiEntryCommon.nasm + Ia32/FspHelper.nasm + Ia32/ReadEsp.nasm + +[Sources.X64] + X64/Stack.nasm + X64/Fsp24ApiEntryM.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + X64/ReadRsp.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + CpuLib + UefiCpuLib + FspMultiPhaseLib + +[Pcd] + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES + +[Ppis] + gEfiTemporaryRamSupportPpiGuid ## PRODUCES + gFspInApiModePpiGuid ## PRODUCES diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreS.inf new file mode 100644 index 0000000000..1d44fb67b5 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf @@ -0,0 +1,59 @@ +## @file +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D Fsp24SecCoreS + FILE_GUID =3D E039988B-0F21-4D95-AE34-C469B10E13F8 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + SecFspApiChk.c + SecFsp.h + +[Sources.IA32] + Ia32/Stack.nasm + Ia32/Fsp24ApiEntryS.nasm + Ia32/FspApiEntryCommon.nasm + Ia32/FspHelper.nasm + +[Sources.X64] + X64/Stack.nasm + X64/Fsp24ApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + FspMultiPhaseLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid ## PRODUCES + diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryM.nasm new file mode 100644 index 0000000000..997b9c0bff --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -0,0 +1,304 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +; +; Following are fixed PCDs +; +extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) +extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) +extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) + +struc FSPM_UPD_COMMON + ; FSP_UPD_HEADER { + .FspUpdHeader: resd 8 + ; } + ; FSPM_ARCH_UPD { + .Revision: resb 1 + .Reserved: resb 3 + .NvsBufferPtr: resd 1 + .StackBase: resd 1 + .StackSize: resd 1 + .BootLoaderTolumSize: resd 1 + .BootMode: resd 1 + .Reserved1: resb 8 + ; } + .size: +endstruc + +struc FSPM_UPD_COMMON_FSP24 + ; FSP_UPD_HEADER { + .FspUpdHeader: resd 8 + ; } + ; FSPM_ARCH2_UPD { + .Revision: resb 1 + .Reserved: resb 3 + .Length resd 1 + .StackBase: resq 1 + .StackSize: resq 1 + .BootLoaderTolumSize: resd 1 + .BootMode: resd 1 + .FspEventHandler resq 1 + .Reserved1: resb 24 + ; } + .size: +endstruc + +; +; Following functions will be provided in C +; +extern ASM_PFX(SecStartup) +extern ASM_PFX(FspApiCommon) + +; +; Following functions will be provided in PlatformSecLib +; +extern ASM_PFX(AsmGetFspBaseAddress) +extern ASM_PFX(AsmGetFspInfoHeader) +extern ASM_PFX(FspMultiPhaseMemInitApiHandler) + +STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose regis= ter * eax index +API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad += pushfd + push eax + call] +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch +FSP_HEADER_CFGREG_OFFSET EQU 24h + +;-------------------------------------------------------------------------= --- +; FspMemoryInit API +; +; This FSP API is called after TempRamInit and initializes the memory. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspMemoryInitApi) +ASM_PFX(FspMemoryInitApi): + mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspMultiPhaseMemoryInitApi API +; +; This FSP API provides multi-phase Memory initialization, which brings gr= eater +; modularity beyond the existing FspMemoryInit() API. +; Increased modularity is achieved by adding an extra API to FSP-M. +; This allows the bootloader to add board specific initialization steps th= roughout +; the MemoryInit flow as needed. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspMultiPhaseMemoryInitApi) +ASM_PFX(FspMultiPhaseMemoryInitApi): + mov eax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex + jmp ASM_PFX(FspApiCommon) +;-------------------------------------------------------------------------= --- +; TempRamExitApi API +; +; This API tears down temporary RAM +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamExitApi) +ASM_PFX(TempRamExitApi): + mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + ; + ; Handle FspMultiPhaseMemInitApiIndex API + ; + cmp eax, 8 ; FspMultiPhaseMemInitApiIndex + jnz NotMultiPhaseMemoryInitApi + + pushad + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam + push eax ; push ApiIdx + call ASM_PFX(FspMultiPhaseMemInitApiHandler) + add esp, 8 + mov dword [esp + STACK_SAVED_EAX_OFFSET], eax + popad + ret + +NotMultiPhaseMemoryInitApi: + + ; + ; FspMemoryInit API setup the initial stack frame + ; + + ; + ; Place holder to store the FspInfoHeader pointer + ; + push eax + + ; + ; Update the FspInfoHeader pointer + ; + push eax + call ASM_PFX(AsmGetFspInfoHeader) + mov [esp + 4], eax + pop eax + + ; + ; Create a Task Frame in the stack for the Boot Loader + ; + pushfd ; 2 pushf for 4 byte alignment + cli + pushad + + ; Reserve 8 bytes for IDT save/restore + sub esp, 8 + sidt [esp] + + + ; Get Stackbase and StackSize from FSPM_UPD Param + mov edx, [esp + API_PARAM1_OFFSET] + cmp edx, 0 + jnz FspStackSetup + + ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null + push eax + call ASM_PFX(AsmGetFspInfoHeader) + mov edx, [eax + FSP_HEADER_IMGBASE_OFFSET] + add edx, [eax + FSP_HEADER_CFGREG_OFFSET] + pop eax + +FspStackSetup: + mov ecx, [edx + FSPM_UPD_COMMON.Revision] + cmp ecx, 3 + jae FspmUpdCommon2 + + ; + ; StackBase =3D temp memory base, StackSize =3D temp memory size + ; + mov edi, [edx + FSPM_UPD_COMMON.StackBase] + mov ecx, [edx + FSPM_UPD_COMMON.StackSize] + jmp ChkFspHeapSize + +FspmUpdCommon2: + mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase] + mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize] + +ChkFspHeapSize: + ; + ; Keep using bootloader stack if heap size % is 0 + ; + mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))] + cmp bl, 0 + jz SkipStackSwitch + + ; + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't e= qual 0 + ; + add edi, ecx + ; + ; Switch to new FSP stack + ; + xchg edi, esp ; Exchange edi and esp, e= di will be assigned to the current esp pointer and esp will be Stack base += Stack size + +SkipStackSwitch: + ; + ; If heap size % is 0: + ; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loade= r stack pointer) + ; ECX is FSPM_UPD_COMMON.StackSize + ; ESP is boot loader stack pointer (no stack switch) + ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.= StackBase later) + ; + ; If heap size % is not 0 + ; EDI is boot loader stack pointer + ; ECX is FSPM_UPD_COMMON.StackSize + ; ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackS= ize) + ; BL is NOT 0 to indicate stack has switched + ; + cmp bl, 0 + jnz StackHasBeenSwitched + + mov ebx, edi ; Put FSPM_UPD_COMMON.Sta= ckBase to ebx as temp memory base + mov edi, esp ; Put boot loader stack p= ointer to edi + jmp StackSetupDone + +StackHasBeenSwitched: + mov ebx, esp ; Put Stack base + Stack = size in ebx + sub ebx, ecx ; Stack base + Stack size= - Stack size as temp memory base + +StackSetupDone: + + ; + ; Pass the API Idx to SecStartup + ; + push eax + + ; + ; Pass the BootLoader stack to SecStartup + ; + push edi + + ; + ; Pass entry point of the PEI core + ; + call ASM_PFX(AsmGetFspBaseAddress) + mov edi, eax + call ASM_PFX(AsmGetPeiCoreOffset) + add edi, eax + push edi + + ; + ; Pass BFV into the PEI Core + ; It uses relative address to calculate the actual boot FV base + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, + ; they are different. The code below can handle both cases. + ; + call ASM_PFX(AsmGetFspBaseAddress) + push eax + + ; + ; Pass stack base and size into the PEI Core + ; + push ebx + push ecx + + ; + ; Pass Control into the PEI Core + ; + call ASM_PFX(SecStartup) + add esp, 4 +exit: + ret + +global ASM_PFX(FspPeiCoreEntryOff) +ASM_PFX(FspPeiCoreEntryOff): + ; + ; This value will be patched by the build script + ; + DD 0x12345678 + +global ASM_PFX(AsmGetPeiCoreOffset) +ASM_PFX(AsmGetPeiCoreOffset): + mov eax, dword [ASM_PFX(FspPeiCoreEntryOff)] + ret + +;-------------------------------------------------------------------------= --- +; TempRamInit API +; +; Empty function for WHOLEARCHIVE build option +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamInitApi) +ASM_PFX(TempRamInitApi): + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryS.nasm new file mode 100644 index 0000000000..bda99cdd80 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm @@ -0,0 +1,101 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2020, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspApiCommon) +extern ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) + +STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose regis= ter * eax index + +;-------------------------------------------------------------------------= --- +; NotifyPhase API +; +; This FSP API will notify the FSP about the different phases in the boot +; process +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(NotifyPhaseApi) +ASM_PFX(NotifyPhaseApi): + mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspSiliconInit API +; +; This FSP API initializes the CPU and the chipset including the IO +; controllers in the chipset to enable normal operation of these devices. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspSiliconInitApi) +ASM_PFX(FspSiliconInitApi): + mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspMultiPhaseSiInitApi API +; +; This FSP API provides multi-phase silicon initialization, which brings g= reater +; modularity beyond the existing FspSiliconInit() API. +; Increased modularity is achieved by adding an extra API to FSP-S. +; This allows the bootloader to add board specific initialization steps th= roughout +; the SiliconInit flow as needed. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspMultiPhaseSiInitApi) +ASM_PFX(FspMultiPhaseSiInitApi): + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + ; + ; Handle FspMultiPhaseSiInitApiIndex API + ; + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex + jnz NotMultiPhaseSiInitApi + + pushad + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam + push eax ; push ApiIdx + call ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) + add esp, 8 + mov dword [esp + STACK_SAVED_EAX_OFFSET], eax + popad + ret + +NotMultiPhaseSiInitApi: + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; TempRamInit API +; +; Empty function for WHOLEARCHIVE build option +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamInitApi) +ASM_PFX(TempRamInitApi): + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp= 2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm index 8d8deba28a..87446be779 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm @@ -67,6 +67,9 @@ FspApiCommon2: cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API jz FspApiCommon3 =20 + cmp eax, 8 ; FspMultiPhaseMemInitApiIndex API + jz FspApiCommon3 + call ASM_PFX(AsmGetFspInfoHeader) jmp ASM_PFX(Loader2PeiSwitchStack) =20 diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg= /FspSecCore/X64/Fsp24ApiEntryM.nasm new file mode 100644 index 0000000000..8880721f29 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm @@ -0,0 +1,303 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +%include "PushPopRegsNasm.inc" + +; +; Following are fixed PCDs +; +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) + +struc FSPM_UPD_COMMON_FSP24 + ; FSP_UPD_HEADER { + .FspUpdHeader: resd 8 + ; } + ; FSPM_ARCH2_UPD { + .Revision: resb 1 + .Reserved: resb 3 + .Length resd 1 + .StackBase: resq 1 + .StackSize: resq 1 + .BootLoaderTolumSize: resd 1 + .BootMode: resd 1 + .FspEventHandler resq 1 + .Reserved1: resb 24 + ; } + .size: +endstruc + +; +; Following functions will be provided in C +; +extern ASM_PFX(SecStartup) +extern ASM_PFX(FspApiCommon) + +; +; Following functions will be provided in PlatformSecLib +; +extern ASM_PFX(AsmGetFspBaseAddress) +extern ASM_PFX(AsmGetFspInfoHeader) +extern ASM_PFX(FspMultiPhaseMemInitApiHandler) + +STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose regis= ter * rax index +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch +FSP_HEADER_CFGREG_OFFSET EQU 24h + +;-------------------------------------------------------------------------= --- +; FspMemoryInit API +; +; This FSP API is called after TempRamInit and initializes the memory. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspMemoryInitApi) +ASM_PFX(FspMemoryInitApi): + mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspMultiPhaseMemoryInitApi API +; +; This FSP API provides multi-phase Memory initialization, which brings gr= eater +; modularity beyond the existing FspMemoryInit() API. +; Increased modularity is achieved by adding an extra API to FSP-M. +; This allows the bootloader to add board specific initialization steps th= roughout +; the MemoryInit flow as needed. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspMultiPhaseMemoryInitApi) +ASM_PFX(FspMultiPhaseMemoryInitApi): + mov rax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex + jmp ASM_PFX(FspApiCommon) +;-------------------------------------------------------------------------= --- +; TempRamExitApi API +; +; This API tears down temporary RAM +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamExitApi) +ASM_PFX(TempRamExitApi): + mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + ; + ; Handle FspMultiPhaseMemoInitApiIndex API + ; + push rdx ; Push a QWORD data for stack alignment + + cmp rax, 8 ; FspMultiPhaseMemInitApiIndex + jnz NotMultiPhaseMemoryInitApi + + PUSHA_64 + mov rdx, rcx ; move ApiParam to rdx + mov rcx, rax ; move ApiIdx to rcx + sub rsp, 0x20 ; calling C function may need shadow space + call ASM_PFX(FspMultiPhaseMemInitApiHandler) + add rsp, 0x20 ; restore shadow space + mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax + POPA_64 + add rsp, 0x08 + ret + +NotMultiPhaseMemoryInitApi: + ; Push RDX and RCX to form CONTEXT_STACK_64 + push rdx ; Push API Parameter2 on stack + push rcx ; Push API Parameter1 on stack + + ; + ; FspMemoryInit API setup the initial stack frame + ; + + ; + ; Place holder to store the FspInfoHeader pointer + ; + push rax + + ; + ; Update the FspInfoHeader pointer + ; + push rax + call ASM_PFX(AsmGetFspInfoHeader) + mov [rsp + 8], rax + pop rax + + ; + ; Create a Task Frame in the stack for the Boot Loader + ; + pushfq + cli + PUSHA_64 + + ; Reserve 16 bytes for IDT save/restore + sub rsp, 16 + sidt [rsp] + + ; Get Stackbase and StackSize from FSPM_UPD Param + mov rdx, rcx ; Put FSPM_UPD Param to r= dx + cmp rdx, 0 + jnz FspStackSetup + + ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null + xchg rbx, rax + call ASM_PFX(AsmGetFspInfoHeader) + mov edx, [rax + FSP_HEADER_IMGBASE_OFFSET] + add edx, [rax + FSP_HEADER_CFGREG_OFFSET] + xchg rbx, rax + +FspStackSetup: + mov cl, [rdx + FSPM_UPD_COMMON_FSP24.Revision] + cmp cl, 3 + jae FspmUpdCommonFsp24 + + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER + sub rsp, 0b8h + ret + +FspmUpdCommonFsp24: + ; + ; StackBase =3D temp memory base, StackSize =3D temp memory size + ; + mov rdi, [rdx + FSPM_UPD_COMMON_FSP24.StackBase] + mov ecx, [rdx + FSPM_UPD_COMMON_FSP24.StackSize] + + ; + ; Keep using bootloader stack if heap size % is 0 + ; + mov rbx, ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) + mov bl, BYTE [rbx] + cmp bl, 0 + jz SkipStackSwitch + + ; + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't e= qual 0 + ; + add rdi, rcx + ; + ; Switch to new FSP stack + ; + xchg rdi, rsp ; Exchange rdi and rsp, r= di will be assigned to the current rsp pointer and rsp will be Stack base += Stack size + +SkipStackSwitch: + ; + ; If heap size % is 0: + ; EDI is FSPM_UPD_COMMON_FSP24.StackBase and will hold ESP later (boot= loader stack pointer) + ; ECX is FSPM_UPD_COMMON_FSP24.StackSize + ; ESP is boot loader stack pointer (no stack switch) + ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON_= FSP24.StackBase later) + ; + ; If heap size % is not 0 + ; EDI is boot loader stack pointer + ; ECX is FSPM_UPD_COMMON_FSP24.StackSize + ; ESP is new stack (FSPM_UPD_COMMON_FSP24.StackBase + FSPM_UPD_COMMON_= FSP24.StackSize) + ; BL is NOT 0 to indicate stack has switched + ; + cmp bl, 0 + jnz StackHasBeenSwitched + + mov rbx, rdi ; Put FSPM_UPD_COMMON_FSP= 24.StackBase to rbx as temp memory base + mov rdi, rsp ; Put boot loader stack p= ointer to rdi + jmp StackSetupDone + +StackHasBeenSwitched: + mov rbx, rsp ; Put Stack base + Stack = size in ebx + sub rbx, rcx ; Stack base + Stack size= - Stack size as temp memory base + +StackSetupDone: + + ; + ; Per X64 calling convention, make sure RSP is 16-byte aligned. + ; + mov rdx, rsp + and rdx, 0fh + sub rsp, rdx + + ; + ; Pass the API Idx to SecStartup + ; + push rax + + ; + ; Pass the BootLoader stack to SecStartup + ; + push rdi + + ; + ; Pass BFV into the PEI Core + ; It uses relative address to calculate the actual boot FV base + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, + ; they are different. The code below can handle both cases. + ; + call ASM_PFX(AsmGetFspBaseAddress) + mov r8, rax + + ; + ; Pass entry point of the PEI core + ; + call ASM_PFX(AsmGetPeiCoreOffset) + lea r9, [r8 + rax] + + ; + ; Pass stack base and size into the PEI Core + ; + mov rcx, rcx + mov rdx, rbx + + ; + ; Pass Control into the PEI Core + ; RCX =3D SizeOfRam, RDX =3D TempRamBase, R8 =3D BFV, R9 =3D PeiCoreEntr= y, Last 1 Stack =3D BL stack, Last 2 Stack =3D API index + ; According to X64 calling convention, caller has to allocate 32 bytes a= s a shadow store on call stack right before + ; calling the function. + ; + sub rsp, 20h + call ASM_PFX(SecStartup) + add rsp, 20h +exit: + ret + +global ASM_PFX(FspPeiCoreEntryOff) +ASM_PFX(FspPeiCoreEntryOff): + ; + ; This value will be patched by the build script + ; + DD 0x12345678 + +global ASM_PFX(AsmGetPeiCoreOffset) +ASM_PFX(AsmGetPeiCoreOffset): + push rbx + mov rbx, ASM_PFX(FspPeiCoreEntryOff) + mov eax, dword[ebx] + pop rbx + ret + +;-------------------------------------------------------------------------= --- +; TempRamInit API +; +; Empty function for WHOLEARCHIVE build option +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamInitApi) +ASM_PFX(TempRamInitApi): + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm b/IntelFsp2Pkg= /FspSecCore/X64/Fsp24ApiEntryS.nasm new file mode 100644 index 0000000000..5bbbc5d1d0 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm @@ -0,0 +1,108 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspApiCommon) +extern ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) + +STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose regis= ter * rax index + +;-------------------------------------------------------------------------= --- +; NotifyPhase API +; +; This FSP API will notify the FSP about the different phases in the boot +; process +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(NotifyPhaseApi) +ASM_PFX(NotifyPhaseApi): + mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspSiliconInit API +; +; This FSP API initializes the CPU and the chipset including the IO +; controllers in the chipset to enable normal operation of these devices. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspSiliconInitApi) +ASM_PFX(FspSiliconInitApi): + mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspMultiPhaseSiInitApi API +; +; This FSP API provides multi-phase silicon initialization, which brings g= reater +; modularity beyond the existing FspSiliconInit() API. +; Increased modularity is achieved by adding an extra API to FSP-S. +; This allows the bootloader to add board specific initialization steps th= roughout +; the SiliconInit flow as needed. +; +;-------------------------------------------------------------------------= --- + +%include "PushPopRegsNasm.inc" + +global ASM_PFX(FspMultiPhaseSiInitApi) +ASM_PFX(FspMultiPhaseSiInitApi): + mov rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + ; + ; Handle FspMultiPhaseSiInitApiIndex API + ; + push rdx ; Push a QWORD data for stack alignment + + cmp rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex + jnz NotMultiPhaseSiInitApi + + PUSHA_64 + mov rdx, rcx ; move ApiParam to rdx + mov rcx, rax ; move ApiIdx to rcx + sub rsp, 0x20 ; calling C function may need shadow space + call ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) + add rsp, 0x20 ; restore shadow space + mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax + POPA_64 + add rsp, 0x08 + ret + +NotMultiPhaseSiInitApi: + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; TempRamInit API +; +; Empty function for WHOLEARCHIVE build option +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamInitApi) +ASM_PFX(TempRamInitApi): + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm b/IntelFsp2= Pkg/FspSecCore/X64/FspApiEntryCommon.nasm index 718e672e02..dc6b8c99a1 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm @@ -68,6 +68,9 @@ FspApiCommon2: cmp rax, 6 ; FspMultiPhaseSiInitApiIndex API jz FspApiCommon3 =20 + cmp rax, 8 ; FspMultiPhaseMemInitApiIndex API + jz FspApiCommon3 + call ASM_PFX(AsmGetFspInfoHeader) jmp ASM_PFX(Loader2PeiSwitchStack) =20 --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92126): https://edk2.groups.io/g/devel/message/92126 Mute This Topic: https://groups.io/mt/92826134/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 16 20:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92127+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92127+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659658816; cv=none; d=zohomail.com; s=zohoarc; b=NQ/oxLdVuTpzdVZf6U57gQZvHbDhLOhVjAdrXeSFtCNSAsxxsJ+eqVHeJ5qYhIDsowF/dZZx6tXKfqwM6PZaFMbnv4Dk1t5KnE6MViTDSuFrEhGixoQdG6GMlBBxJGE4uQcHuFo6GWQ70jntvrkHfcFnziivlHevuwBmi1kC6aY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659658816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=q7yAJoT7Uc5bgAmqvhthaCp6oRbfNccbe3nWWJNKirk=; b=nMdLoBNxne9uM0E1+bRmX0LC7lMcjPrODPvXDFaRvQ631tjKz0N5VwgRIkcE9qj+tkuSPwK4KhT+wUeqj2yJ8FQdpmMmG75Wkg7bCJdEXaZ++ZK/gMMwGOzyrX3rFyNWJ0ouAQvIMT7nsYqwTzsTSosmkT9rXgd+UbdgKJxdwDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92127+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1659658816931285.78739281902904; Thu, 4 Aug 2022 17:20:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8uGeYY1788612x0uechvO66Y; Thu, 04 Aug 2022 17:20:16 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.1516.1659658815265618110 for ; Thu, 04 Aug 2022 17:20:16 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="287647680" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287647680" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:15 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671497603" X-Received: from jwiegert-mobl1.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.235.240]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:12 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH 4/4] IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers. Date: Thu, 4 Aug 2022 17:19:51 -0700 Message-Id: <20220805001951.3687-5-chasel.chiu@intel.com> In-Reply-To: <20220805001951.3687-1-chasel.chiu@intel.com> References: <20220805001951.3687-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: GS37xxArufFkmUhz9sOZIuZjx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659658816; bh=AlvVct6k/YN071EO4H3vzjI6TzKmcI79V1DOfqLufOA=; h=Cc:Date:From:Reply-To:Subject:To; b=G9ovVCEHHZGWVpj0u6hY9MU4UlY/MGkWczqm26qBfNRKmhDCH1v3yEkOx1JFKXiO3UN O0dyIaG3mXtBO4N5AQo0WZTIOusd6EGRqyLt3jtwJzr5HYmNNtbAJAl+uyp6nIIqfTH+O hOsmiAXBrnvKHm81sFdwzScOmJ+jMra4lJE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659658817514100011 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Implement MultiPhase wrapper handlers and only call to MultiPhase handlers when FSP supports. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 33 +++++++++++++= ++++++++++++-------- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 27 +++++++++++++= ++++++++------ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- 4 files changed, 49 insertions(+), 15 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelF= sp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c index ac27524d08..ea206a7960 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include =20 @@ -35,6 +36,8 @@ #include #include #include +#include +#include =20 extern EFI_GUID gFspHobGuid; =20 @@ -119,25 +122,39 @@ PeiFspMemoryInit ( =20 TimeStampCounterStart =3D AsmReadTsc (); Status =3D CallFspMemoryInit (FspmUpdDataPtr, &FspHobList= Ptr); - // Create hobs after memory initialization and not in temp RAM. Hence pa= ssing the recorded timestamp here - PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCount= erStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_ST= ATUS_CODE_API_ENTRY); - PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); - DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d mil= lisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCount= erStart), 1000000))); =20 // // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { - DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status)= ); + DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset %r\n", Status)); CallFspWrapperResetSystem (Status); } =20 - if (EFI_ERROR (Status)) { + if ((Status !=3D FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspMemoryInitApi(), St= atus =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); } =20 - DEBUG ((DEBUG_INFO, "FspMemoryInit status: 0x%x\n", Status)); - ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "FspMemoryInit status: %r\n", Status)); + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) { + // + // call to Variable request handler + // + FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseMemInit= ApiIndex); + } + + // + // See if MultiPhase process is required or not + // + FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseMemInitApiInde= x); // FspM MultiPhase + + // + // Create hobs after memory initialization and not in temp RAM. Hence pa= ssing the recorded timestamp here + // + PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCount= erStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_ST= ATUS_CODE_API_ENTRY); + PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); + DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d mil= lisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCount= erStart), 1000000))); =20 Status =3D TestFspMemoryInitApiOutput (FspmUpdDataPtr, &FspHobListPtr); if (EFI_ERROR (Status)) { diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelF= sp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index ee48dd69d3..a41c809c62 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include #include +#include =20 extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc; extern EFI_GUID gFspHobGuid; @@ -318,23 +320,36 @@ PeiMemoryDiscoveredNotify ( TimeStampCounterStart =3D AsmReadTsc (); PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_= CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY= ); Status =3D CallFspSiliconInit ((VOID *)FspsUpdDataPtr); - PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); - DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d mi= llisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCoun= terStart), 1000000))); =20 // // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { - DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status= )); + DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset %r\n", Status)); CallFspWrapperResetSystem (Status); } =20 - if (EFI_ERROR (Status)) { + if ((Status !=3D FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspSiliconInitApi(), S= tatus =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); } =20 - DEBUG ((DEBUG_INFO, "FspSiliconInit status: 0x%x\n", Status)); - ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status)); + + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) { + // + // call to Variable request handler + // + FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseMemInit= ApiIndex); + } + + // + // See if MultiPhase process is required or not + // + FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseSiInitApiIndex= ); // FspS MultiPhase + + PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); + DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d mi= llisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCoun= terStart), 1000000))); =20 Status =3D TestFspSiliconInitApiOutput ((VOID *)NULL); if (RETURN_ERROR (Status)) { diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/Inte= lFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf index e2262d693c..332509e0bc 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf @@ -46,6 +46,7 @@ FspWrapperApiLib FspWrapperApiTestLib FspMeasurementLib + FspWrapperMultiPhaseProcessLib =20 [Packages] MdePkg/MdePkg.dec diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/Inte= lFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf index 0598f85ab3..f9c2ffca1c 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf @@ -6,7 +6,7 @@ # register TemporaryRamDonePpi to call TempRamExit API, and register Memor= yDiscoveredPpi # notify to call FspSiliconInit API. # -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -46,6 +46,7 @@ FspWrapperApiLib FspWrapperApiTestLib FspMeasurementLib + FspWrapperMultiPhaseProcessLib =20 [Packages] MdePkg/MdePkg.dec --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92127): https://edk2.groups.io/g/devel/message/92127 Mute This Topic: https://groups.io/mt/92826135/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-