From nobody Sat Apr 27 00:55:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91965+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91965+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1659075963; cv=none; d=zohomail.com; s=zohoarc; b=BEYcv1UmcrPdYoAw0rRsBVsw5qP2WF6bstnPeyI+iuSz1lb86qYDFrqDdcKPHQLGUs9pqi0W4aaifnC/tkX/711GAInPg4lEm+rg3u6sV1Mo1mcC3KmLuZ8o7O0C0+qvViRbONABik+AtsLT8Z27jReOEOGMlQlnUm7Zr9eNPVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659075963; h=Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=cDzGQEF73CaoPDzzJl7a5snSRWxdXUIhEGn0B2qfSfg=; b=BUTtlvtAF/355RhSIDwdV4hZikAugV94OWx/68h4AybUVLuElbt9GOudC9MvWMLBIkwRPPAHhBa/kw49nuWUmWRVxIa1UsWasU/kuNpTR3Dz2RotfQhX0Rb0E3EK/VYBsO/UfX17lNYfnG4bXI5T+G2lNrr+0upwW9CYAcf5rRs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91965+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165907596366237.30534592933452; Thu, 28 Jul 2022 23:26:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cqdsYY1788612xTFyTL00tII; Thu, 28 Jul 2022 23:26:03 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web08.5066.1659075961926526278 for ; Thu, 28 Jul 2022 23:26:02 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10422"; a="289472876" X-IronPort-AV: E=Sophos;i="5.93,200,1654585200"; d="scan'208";a="289472876" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2022 23:26:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,200,1654585200"; d="scan'208";a="629257911" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 28 Jul 2022 23:25:59 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Star Zeng , Michael D Kinney Subject: [edk2-devel] [PATCH v1] UefiCpuPkg: Add PCD to control SMRR enable & SmmFeatureControl support Date: Fri, 29 Jul 2022 14:25:55 +0800 Message-Id: <20220729062555.6272-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: toZAZvuPfGFHEa2pqFMp8T4Xx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1659075963; bh=YY1cMSGl0rtkZON8JLsNUop6FbGPc+P+2emaKHFvt/A=; h=Cc:Date:From:Reply-To:Subject:To; b=X6uB3SuaGRuTwiYjfX2SimngqShvRfMkZdpv0zNHTChGnwJQYkkSyMlNE2e7X/qBqh2 m5Hw5UtYUnUcK0wNP2TKyUwMNXm8yxSUaMEUEHS2koUk5qQJyZw3MyAAwlhhwpQpgZNw3 ja2FLKgzGMnr8Tm/RM3PETv9YfovtFGPqiI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1659075965238100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3962 Two SMM variables (mSmrrSupported & mSmmFeatureControlSupported) are global variables, they control whether the SMRR and SMM Feature Control MSR will be restored respectively. To avoid the TOCTOU, add PCD to control SMRR & SmmFeatureControl enable. Change-Id: I6835e4b0e12c5e6f52effb60fd9224e3eb97fc0d Cc: Eric Dong Cc: Ray Ni Cc: Star Zeng Cc: Michael D Kinney Signed-off-by: Jiaxin Wu --- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 +++ .../SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c | 35 ++++++++----------= ---- .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 4 +++ .../StandaloneMmCpuFeaturesLib.inf | 4 +++ UefiCpuPkg/UefiCpuPkg.dec | 12 ++++++++ UefiCpuPkg/UefiCpuPkg.uni | 12 ++++++++ 6 files changed, 48 insertions(+), 23 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 35292dac31..7b5cef9700 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -33,5 +33,9 @@ MemoryAllocationLib DebugLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c= b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c index 78de7f8407..75a0ec8e94 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c @@ -35,20 +35,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // MSRs required for configuration of SMM Code Access Check // #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D #define SMM_CODE_ACCESS_CHK_BIT BIT58 =20 -// -// Set default value to assume SMRR is not supported -// -BOOLEAN mSmrrSupported =3D FALSE; - -// -// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported -// -BOOLEAN mSmmFeatureControlSupported =3D FALSE; - // // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; @@ -96,11 +86,11 @@ CpuFeaturesLibInitialization ( if ((RegEdx & BIT12) !=3D 0) { // // Check MTRR_CAP MSR bit 11 for SMRR support // if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) !=3D 0) { - mSmrrSupported =3D TRUE; + ASSERT (FeaturePcdGet (PcdSmrrEnable)); } } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual @@ -109,11 +99,11 @@ CpuFeaturesLibInitialization ( // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then // SMRR Physical Base and SMM Physical Mask MSRs are not available. // if (FamilyId =3D=3D 0x06) { if ((ModelId =3D=3D 0x1C) || (ModelId =3D=3D 0x26) || (ModelId =3D=3D = 0x27) || (ModelId =3D=3D 0x35) || (ModelId =3D=3D 0x36)) { - mSmrrSupported =3D FALSE; + ASSERT (!FeaturePcdGet (PcdSmrrEnable)); } } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual @@ -214,17 +204,16 @@ SmmCpuFeaturesInitializeProcessor ( // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used,= then // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set b= efore // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL = MSR(0x3A) // is set, then the MSR is locked and can not be modified. // - if (mSmrrSupported && (mSmrrPhysBaseMsr =3D=3D SMM_FEATURES_LIB_IA32_COR= E_SMRR_PHYSBASE)) { + if ((FeaturePcdGet (PcdSmrrEnable)) && (mSmrrPhysBaseMsr =3D=3D SMM_FEAT= URES_LIB_IA32_CORE_SMRR_PHYSBASE)) { FeatureControl =3D AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL= ); if ((FeatureControl & BIT3) =3D=3D 0) { + ASSERT ((FeatureControl & BIT0) =3D=3D 0); if ((FeatureControl & BIT0) =3D=3D 0) { AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureContr= ol | BIT3); - } else { - mSmrrSupported =3D FALSE; } } } =20 // @@ -232,11 +221,11 @@ SmmCpuFeaturesInitializeProcessor ( // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first norma= l SMI. // The code that initializes SMM environment is running in normal mode // from SMRAM region. If SMRR is enabled here, then the SMRAM region // is protected and the normal mode code execution will fail. // - if (mSmrrSupported) { + if (FeaturePcdGet (PcdSmrrEnable)) { // // SMRR size cannot be less than 4-KBytes // SMRR size must be of length 2^n // SMRR base alignment cannot be less than SMRR length // @@ -285,11 +274,11 @@ SmmCpuFeaturesInitializeProcessor ( // // Check to see if the CPU supports the SMM Code Access Check feature // Do not access this MSR unless the CPU supports the SmmRegFeatureC= ontrol // if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_= CHK_BIT) !=3D 0) { - mSmmFeatureControlSupported =3D TRUE; + ASSERT (FeaturePcdGet (PcdSmmFeatureControlEnable)); } } } =20 // @@ -381,11 +370,11 @@ VOID EFIAPI SmmCpuFeaturesDisableSmrr ( VOID ) { - if (mSmrrSupported && mNeedConfigureMtrrs) { + if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) { AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EF= I_MSR_SMRR_PHYS_MASK_VALID); } } =20 /** @@ -396,11 +385,11 @@ VOID EFIAPI SmmCpuFeaturesReenableSmrr ( VOID ) { - if (mSmrrSupported && mNeedConfigureMtrrs) { + if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) { AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI= _MSR_SMRR_PHYS_MASK_VALID); } } =20 /** @@ -417,11 +406,11 @@ SmmCpuFeaturesRendezvousEntry ( ) { // // If SMRR is supported and this is the first normal SMI, then enable SM= RR // - if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) { + if (FeaturePcdGet (PcdSmrrEnable) && !mSmrrEnabled[CpuIndex]) { AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI= _MSR_SMRR_PHYS_MASK_VALID); mSmrrEnabled[CpuIndex] =3D TRUE; } } =20 @@ -458,11 +447,11 @@ EFIAPI SmmCpuFeaturesIsSmmRegisterSupported ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && (RegName =3D=3D SmmRegFeatureControl)= ) { + if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName =3D=3D SmmReg= FeatureControl)) { return TRUE; } =20 return FALSE; } @@ -484,11 +473,11 @@ EFIAPI SmmCpuFeaturesGetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && (RegName =3D=3D SmmRegFeatureControl)= ) { + if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName =3D=3D SmmReg= FeatureControl)) { return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); } =20 return 0; } @@ -510,11 +499,11 @@ SmmCpuFeaturesSetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName, IN UINT64 Value ) { - if (mSmmFeatureControlSupported && (RegName =3D=3D SmmRegFeatureControl)= ) { + if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName =3D=3D SmmReg= FeatureControl)) { AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); } } =20 /** diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 022351f593..85214ee31c 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -68,7 +68,11 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES =20 +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES + [Depex] gEfiMpServiceProtocolGuid diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLi= b.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index ec97041d8b..3eacab48db 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -34,5 +34,9 @@ MemoryAllocationLib PcdLib =20 [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 1951eb294c..55cbe7605f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -153,10 +153,22 @@ # TRUE - SMM Feature Control MSR will be locked.
# FALSE - SMM Feature Control MSR will not be locked.
# @Prompt Lock SMM Feature Control MSR. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x= 3213210B =20 + ## Indicates if SMRR will be enabled.

+ # TRUE - SMRR will be enabled.
+ # FALSE - SMRR will not be enabled.
+ # @Prompt Enable SMRR. + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D + + ## Indicates if SmmFeatureControl will be enabled.

+ # TRUE - SmmFeatureControl will be enabled.
+ # FALSE - SmmFeatureControl will not be enabled.
+ # @Prompt Support SmmFeatureControl. + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x3213= 2110 + [PcdsFixedAtBuild] ## List of exception vectors which need switching stack. # This PCD will only take into effect if PcdCpuStackGuard is enabled. # By default exception #DD(8), #PF(14) are supported. # @Prompt Specify exception vectors which need switching stack. diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index 219c1963bf..d17bcfd10c 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -98,10 +98,22 @@ =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmFeatureControlMsrLock_HELP = #language en-US "Lock SMM Feature Control MSR?

\n" = "TRUE - locked.
\n" = "FALSE - unlocked.
" =20 +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSmrrEnable_PROMPT #language en-U= S "Indicates if SMRR will be enabled." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSmrrEnable_HELP #language en-US = "Indicates if SMRR will be enabled.

\n" + = "TRUE - SMRR will be enabled.
\n" + = "FALSE - SMRR will not be enabled.
" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSmmFeatureControlEnable_PROMPT #= language en-US "Indicates if SmmFeatureControl will be enabled." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSmmFeatureControlEnable_HELP #la= nguage en-US "Indicates if SmmFeatureControl will be enabled.

\n" + = "TRUE - SmmFeatureControl will be enabled.
\n" + = "FALSE - SmmFeatureControl will not be enabled.
" + #string STR_gUefiCpuPkgTokenSpaceGuid_PcdPeiTemporaryRamStackSize_PROMPT = #language en-US "Stack size in the temporary RAM" =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdPeiTemporaryRamStackSize_HELP #l= anguage en-US "Specifies stack size in the temporary RAM. 0 means half of T= emporaryRamSize." =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmProfileSize_PROMPT #langua= ge en-US "SMM profile data buffer size" --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91965): https://edk2.groups.io/g/devel/message/91965 Mute This Topic: https://groups.io/mt/92685826/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-