From nobody Sat May 4 03:45:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91690+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91690+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658476681; cv=none; d=zohomail.com; s=zohoarc; b=G+ShSH0u0l738IdBK3q5fvfQz4JOWQO62lrby1hoUSev8XRjdS5VYENWTVFrNSH3xZA3TiIvC/VXpJiBEEEjTrFTFoHD2CiTPfJ6lTS/w2SC723s1TI91CeHeVDYcvt/qtKcJgMsdCSixn5iGzo70Xy9JNMBqMxzY1hiFZnIq/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658476681; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jmN+2fu+8CtbuzgoYBdP8I12j7NgfBw9e0e68ez6fsI=; b=D7lUzXhZVtGgnUWne/1kTIDjxJLidEJsWCN1ySkkVdB3I6FR98/pHWWv8bnRyUMRt1DEamz7QNuWzhFzVPXG9B01Ja+lJNE37+Ql00vTtayLB7JuHWiLlq4YyOLdbg6IULQlGI5U+sH6dnF777vBnrB3PYJbFsbxRUjX1Dus240= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91690+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658476681569565.6724256871559; Fri, 22 Jul 2022 00:58:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QVA7YY1788612x8cfrRKs8Ar; Fri, 22 Jul 2022 00:58:00 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web10.5439.1658476676550625421 for ; Fri, 22 Jul 2022 00:57:59 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10415"; a="351257848" X-IronPort-AV: E=Sophos;i="5.93,185,1654585200"; d="scan'208";a="351257848" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2022 00:57:59 -0700 X-IronPort-AV: E=Sophos;i="5.93,185,1654585200"; d="scan'208";a="626468579" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.141]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2022 00:57:56 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Dandan Bi , Liming Gao , Jian J Wang , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH 1/2] UefiCpuPkg: Simplify InitializeSeparateExceptionStacks Date: Fri, 22 Jul 2022 15:57:36 +0800 Message-Id: <20220722075737.897-2-zhiguang.liu@intel.com> In-Reply-To: <20220722075737.897-1-zhiguang.liu@intel.com> References: <20220722075737.897-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: PokGOhOwptEQerH07T23dfsGx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658476680; bh=4aO/6jOTGZn9cJw6oidORfYoDbe5ql4fdVS5iVAk0Fc=; h=Cc:Date:From:Reply-To:Subject:To; b=dTWtof17TsXztLLltmFzoNEWjqUyZ4NE/559O5QD4O2Qwx0QkipVamyvKpf/HzsoP5f VzKCKSt5iKQPL2pYLTocbJl0h4v3RdWioH3I6JGcRkMxutXzW3x1qdB26Vnb+v7Hu7/18 05TpHCq0wKf1bABqB4ew9ouNmr26whva9ZE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658476682603100005 Content-Type: text/plain; charset="utf-8" Hide the Exception implementation details in CpuExcetionHandlerLib and caller only need to provide buffer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Dandan Bi Cc: Liming Gao Cc: Jian J Wang Cc: Ard Biesheuvel Cc: Sami Mujawar Signed-off-by: Zhiguang Liu Reviewed-by: Sami Mujawar --- .../Library/ArmExceptionLib/ArmExceptionLib.c | 15 +- MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 4 +- .../Include/Library/CpuExceptionHandlerLib.h | 15 +- .../CpuExceptionHandlerLibNull.c | 15 +- UefiCpuPkg/CpuDxe/CpuMp.c | 157 +++------------- UefiCpuPkg/CpuDxe/CpuMp.h | 10 +- UefiCpuPkg/CpuMpPei/CpuMpPei.c | 174 ++++-------------- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 10 +- .../CpuExceptionHandlerLib/DxeException.c | 77 +++++--- .../Ia32/ArchExceptionHandler.c | 3 +- .../CpuExceptionHandlerLib/PeiCpuException.c | 62 ++++++- .../PeiCpuExceptionHandlerLib.inf | 4 +- .../SecPeiCpuException.c | 15 +- .../CpuExceptionHandlerLib/SmmException.c | 15 +- .../X64/ArchExceptionHandler.c | 3 +- 15 files changed, 231 insertions(+), 348 deletions(-) diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c b/ArmPkg/Libr= ary/ArmExceptionLib/ArmExceptionLib.c index 2c7bc66aa7..a521c33f32 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c @@ -288,20 +288,23 @@ CommonCExceptionHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_SUCCESS; diff --git a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c b/MdeModulePkg/Core/Dx= e/DxeMain/DxeMain.c index 0a1f3d79e2..5733f0c8ec 100644 --- a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c +++ b/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c @@ -1,7 +1,7 @@ /** @file DXE Core Main Entry Point =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -260,7 +260,7 @@ DxeMain ( // Setup Stack Guard // if (PcdGetBool (PcdCpuStackGuard)) { - Status =3D InitializeSeparateExceptionStacks (NULL); + Status =3D InitializeSeparateExceptionStacks (NULL, NULL); ASSERT_EFI_ERROR (Status); } =20 diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 9a495081f7..8d44ed916a 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -104,20 +104,23 @@ InitializeCpuExceptionHandlers ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ); =20 /** diff --git a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHa= ndlerLibNull.c b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExcepti= onHandlerLibNull.c index 8aeedcb4d1..74908a379b 100644 --- a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi= bNull.c +++ b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi= bNull.c @@ -83,20 +83,23 @@ DumpCpuContext ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c index e385f585c7..286ef2d3fd 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.c +++ b/UefiCpuPkg/CpuDxe/CpuMp.c @@ -596,24 +596,6 @@ CollectBistDataFromHob ( } } =20 -/** - Get GDT register value. - - This function is mainly for AP purpose because AP may have different GDT - table than BSP. - - @param[in,out] Buffer The pointer to private data buffer. - -**/ -VOID -EFIAPI -GetGdtr ( - IN OUT VOID *Buffer - ) -{ - AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); -} - /** Initializes CPU exceptions handlers for the sake of stack switch require= ment. =20 @@ -629,27 +611,17 @@ InitializeExceptionStackSwitchHandlers ( IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + SWITCH_STACK_DATA *SwitchStackData; =20 - EssData =3D Buffer; - // - // We don't plan to replace IDT table with a new one, but we should not = assume - // the AP's IDT is the same as BSP's IDT either. - // - AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable =3D (VOID *)Idtr.Base; - EssData->Ia32.IdtTableSize =3D Idtr.Limit + 1; - Status =3D InitializeSeparateExceptionStacks (EssDat= a); - ASSERT_EFI_ERROR (Status); + SwitchStackData =3D (SWITCH_STACK_DATA *)Buffer; + InitializeSeparateExceptionStacks (SwitchStackData->Buffer, SwitchStackD= ata->BufferSize); } =20 /** Initializes MP exceptions handlers for the sake of stack switch requirem= ent. =20 This function will allocate required resources required to setup stack s= witch - and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor. + and pass them through SwitchStackData to each logic processor. =20 **/ VOID @@ -657,129 +629,52 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - - ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * Exception= Number; - - StackTop =3D AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors= ); - ASSERT (StackTop !=3D NULL); - StackTop +=3D NewStackSize * mNumberOfProcessors; + UINTN Index; + UINTN Bsp; + UINT8 *Buffer; + SWITCH_STACK_DATA SwitchStackData; + UINTN BufferSize; =20 - // - // The default exception handlers must have been initialized. Let's just= skip - // it in this method. - // - EssData.Ia32.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.Ia32.InitDefaultHandlers =3D FALSE; - - EssData.Ia32.StackSwitchExceptions =3D FixedPcdGetPtr (PcdCpuStackS= witchExceptionList); - EssData.Ia32.StackSwitchExceptionNumber =3D ExceptionNumber; - EssData.Ia32.KnownGoodStackSize =3D FixedPcdGet32 (PcdCpuKnownGo= odStackSize); - - // - // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. - // - Gdtr.Base =3D 0; - Gdtr.Limit =3D 0; + SwitchStackData.BufferSize =3D &BufferSize; MpInitLibWhoAmI (&Bsp); + for (Index =3D 0; Index < mNumberOfProcessors; ++Index) { - // - // To support stack switch, we need to re-construct GDT but not IDT. - // + SwitchStackData.Buffer =3D NULL; + BufferSize =3D 0; + if (Index =3D=3D Bsp) { - GetGdtr (&Gdtr); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { // - // AP might have different size of GDT from BSP. + // AP might need different buffer size from BSP. // - MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); + MpInitLibStartupThisAP (InitializeExceptionStackSwitchHandlers, Inde= x, NULL, 0, (VOID *)&SwitchStackData, NULL); } =20 - // - // X64 needs only one TSS of current task working for all exceptions - // because of its IST feature. IA32 needs one TSS for each exception - // in addition to current task. Since AP is not supposed to allocate - // memory, we have to do it in BSP. To simplify the code, we allocate - // memory for IA32 case to cover both IA32 and X64 exception stack - // switch. - // - // Layout of memory to allocate for each processor: - // -------------------------------- - // | Alignment | (just in case) - // -------------------------------- - // | | - // | Original GDT | - // | | - // -------------------------------- - // | Current task descriptor | - // -------------------------------- - // | | - // | Exception task descriptors | X ExceptionNumber - // | | - // -------------------------------- - // | Current task-state segment | - // -------------------------------- - // | | - // | Exception task-state segment | X ExceptionNumber - // | | - // -------------------------------- - // - OldGdtSize =3D Gdtr.Limit + 1; - EssData.Ia32.ExceptionTssDescSize =3D sizeof (IA32_TSS_DESCRIPTOR) * - (ExceptionNumber + 1); - EssData.Ia32.ExceptionTssSize =3D sizeof (IA32_TASK_STATE_SEGMENT) * - (ExceptionNumber + 1); - NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + - OldGdtSize + - EssData.Ia32.ExceptionTssDescSize + - EssData.Ia32.ExceptionTssSize; - - GdtBuffer =3D AllocateRuntimeZeroPool (NewGdtSize); - ASSERT (GdtBuffer !=3D NULL); - - // - // Make sure GDT table alignment - // - EssData.Ia32.GdtTable =3D ALIGN_POINTER (GdtBuffer, sizeof (IA32_T= SS_DESCRIPTOR)); - NewGdtSize -=3D ((UINT8 *)EssData.Ia32.GdtTable - GdtBuf= fer); - EssData.Ia32.GdtTableSize =3D NewGdtSize; - - EssData.Ia32.ExceptionTssDesc =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize); - EssData.Ia32.ExceptionTss =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize + - EssData.Ia32.ExceptionTssDescSize); - - EssData.Ia32.KnownGoodStackTop =3D (UINTN)StackTop; + ASSERT (BufferSize !=3D 0); + Buffer =3D AllocateRuntimeZeroPool (BufferSize); + ASSERT (Buffer !=3D NULL); + SwitchStackData.Buffer =3D Buffer; DEBUG (( DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", + "Buffer[cpu%lu] for InitializeExceptionStackSwitchHandlers: 0x%lX wi= th size 0x%x\n", (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop + (UINT64)(UINTN)Buffer, + (UINT32)BufferSize )); =20 if (Index =3D=3D Bsp) { - InitializeExceptionStackSwitchHandlers (&EssData); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { MpInitLibStartupThisAP ( InitializeExceptionStackSwitchHandlers, Index, NULL, 0, - (VOID *)&EssData, + (VOID *)&SwitchStackData, NULL ); } - - StackTop -=3D NewStackSize; } } =20 diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h index b461753510..c545a711b8 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.h +++ b/UefiCpuPkg/CpuDxe/CpuMp.h @@ -1,7 +1,7 @@ /** @file CPU DXE MP support =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -9,6 +9,14 @@ #ifndef _CPU_MP_H_ #define _CPU_MP_H_ =20 +// +// Structure for InitializeSeparateExceptionStacks +// +typedef struct { + VOID *Buffer; + UINTN *BufferSize; +} SWITCH_STACK_DATA; + /** Initialize Multi-processor support. =20 diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c index d4786979fa..dfc0128361 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.c +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.c @@ -1,7 +1,7 @@ /** @file CPU PEI Module installs CPU Multiple Processor PPI. =20 - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -411,24 +411,6 @@ PeiWhoAmI ( return MpInitLibWhoAmI (ProcessorNumber); } =20 -/** - Get GDT register value. - - This function is mainly for AP purpose because AP may have different GDT - table than BSP. - - @param[in,out] Buffer The pointer to private data buffer. - -**/ -VOID -EFIAPI -GetGdtr ( - IN OUT VOID *Buffer - ) -{ - AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); -} - /** Initializes CPU exceptions handlers for the sake of stack switch require= ment. =20 @@ -444,27 +426,17 @@ InitializeExceptionStackSwitchHandlers ( IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + SWITCH_STACK_DATA *SwitchStackData; =20 - EssData =3D Buffer; - // - // We don't plan to replace IDT table with a new one, but we should not = assume - // the AP's IDT is the same as BSP's IDT either. - // - AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable =3D (VOID *)Idtr.Base; - EssData->Ia32.IdtTableSize =3D Idtr.Limit + 1; - Status =3D InitializeSeparateExceptionStacks (EssDat= a); - ASSERT_EFI_ERROR (Status); + SwitchStackData =3D (SWITCH_STACK_DATA *)Buffer; + InitializeSeparateExceptionStacks (SwitchStackData->Buffer, SwitchStackD= ata->BufferSize); } =20 /** Initializes MP exceptions handlers for the sake of stack switch requirem= ent. =20 This function will allocate required resources required to setup stack s= witch - and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor. + and pass them through SwitchStackData to each logic processor. =20 **/ VOID @@ -472,18 +444,14 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - EFI_STATUS Status; - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - UINTN NumberOfProcessors; + UINTN Index; + UINTN Bsp; + UINT8 *Buffer; + SWITCH_STACK_DATA SwitchStackData; + UINTN BufferSize; + + SwitchStackData.BufferSize =3D &BufferSize; + UINTN NumberOfProcessors; =20 if (!PcdGetBool (PcdCpuStackGuard)) { return; @@ -492,128 +460,48 @@ InitializeMpExceptionStackSwitchHandlers ( MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL); MpInitLibWhoAmI (&Bsp); =20 - ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * Exception= Number; - - StackTop =3D AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfPr= ocessors)); - ASSERT (StackTop !=3D NULL); - if (StackTop =3D=3D NULL) { - return; - } - - StackTop +=3D NewStackSize * NumberOfProcessors; - - // - // The default exception handlers must have been initialized. Let's just= skip - // it in this method. - // - EssData.Ia32.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.Ia32.InitDefaultHandlers =3D FALSE; - - EssData.Ia32.StackSwitchExceptions =3D FixedPcdGetPtr (PcdCpuStackS= witchExceptionList); - EssData.Ia32.StackSwitchExceptionNumber =3D ExceptionNumber; - EssData.Ia32.KnownGoodStackSize =3D FixedPcdGet32 (PcdCpuKnownGo= odStackSize); - - // - // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. - // - Gdtr.Base =3D 0; - Gdtr.Limit =3D 0; for (Index =3D 0; Index < NumberOfProcessors; ++Index) { - // - // To support stack switch, we need to re-construct GDT but not IDT. - // + SwitchStackData.Buffer =3D NULL; + BufferSize =3D 0; + if (Index =3D=3D Bsp) { - GetGdtr (&Gdtr); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { // - // AP might have different size of GDT from BSP. + // AP might need different buffer size from BSP. // - MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); + MpInitLibStartupThisAP (InitializeExceptionStackSwitchHandlers, Inde= x, NULL, 0, (VOID *)&SwitchStackData, NULL); } =20 - // - // X64 needs only one TSS of current task working for all exceptions - // because of its IST feature. IA32 needs one TSS for each exception - // in addition to current task. Since AP is not supposed to allocate - // memory, we have to do it in BSP. To simplify the code, we allocate - // memory for IA32 case to cover both IA32 and X64 exception stack - // switch. - // - // Layout of memory to allocate for each processor: - // -------------------------------- - // | Alignment | (just in case) - // -------------------------------- - // | | - // | Original GDT | - // | | - // -------------------------------- - // | Current task descriptor | - // -------------------------------- - // | | - // | Exception task descriptors | X ExceptionNumber - // | | - // -------------------------------- - // | Current task-state segment | - // -------------------------------- - // | | - // | Exception task-state segment | X ExceptionNumber - // | | - // -------------------------------- - // - OldGdtSize =3D Gdtr.Limit + 1; - EssData.Ia32.ExceptionTssDescSize =3D sizeof (IA32_TSS_DESCRIPTOR) * - (ExceptionNumber + 1); - EssData.Ia32.ExceptionTssSize =3D sizeof (IA32_TASK_STATE_SEGMENT) * - (ExceptionNumber + 1); - NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + - OldGdtSize + - EssData.Ia32.ExceptionTssDescSize + - EssData.Ia32.ExceptionTssSize; - - Status =3D PeiServicesAllocatePool ( - NewGdtSize, - (VOID **)&GdtBuffer - ); - ASSERT (GdtBuffer !=3D NULL); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return; + if (BufferSize =3D=3D 0 ) { + continue; } =20 - // - // Make sure GDT table alignment - // - EssData.Ia32.GdtTable =3D ALIGN_POINTER (GdtBuffer, sizeof (IA32_T= SS_DESCRIPTOR)); - NewGdtSize -=3D ((UINT8 *)EssData.Ia32.GdtTable - GdtBuf= fer); - EssData.Ia32.GdtTableSize =3D NewGdtSize; - - EssData.Ia32.ExceptionTssDesc =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize); - EssData.Ia32.ExceptionTss =3D ((UINT8 *)EssData.Ia32.GdtTable + Ol= dGdtSize + - EssData.Ia32.ExceptionTssDescSize); - - EssData.Ia32.KnownGoodStackTop =3D (UINTN)StackTop; + ASSERT (BufferSize !=3D 0); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); + ASSERT (Buffer !=3D NULL); + ZeroMem (Buffer, EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (BufferSize))); + SwitchStackData.Buffer =3D Buffer; DEBUG (( DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", + "Buffer[cpu%lu] for InitializeExceptionStackSwitchHandlers: 0x%lX wi= th size 0x%x\n", (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop + (UINT64)(UINTN)Buffer, + (UINT32)BufferSize )); =20 if (Index =3D=3D Bsp) { - InitializeExceptionStackSwitchHandlers (&EssData); + InitializeExceptionStackSwitchHandlers (&SwitchStackData); } else { MpInitLibStartupThisAP ( InitializeExceptionStackSwitchHandlers, Index, NULL, 0, - (VOID *)&EssData, + (VOID *)&SwitchStackData, NULL ); } - - StackTop -=3D NewStackSize; } } =20 diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h index 0649c48d14..f4fe7a3d39 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h @@ -1,7 +1,7 @@ /** @file Definitions to install Multiple Processor PPI. =20 - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -31,6 +31,14 @@ =20 extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; =20 +// +// Structure for InitializeSeparateExceptionStacks +// +typedef struct { + VOID *Buffer; + UINTN *BufferSize; +} SWITCH_STACK_DATA; + /** This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index e62bb5e6c0..4b75c42f1e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -104,48 +104,71 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { CPU_EXCEPTION_INIT_DATA EssData; IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Gdtr; + UINTN NeedBufferSize; + UINTN StackTop; + UINT8 *NewGdtTable; =20 - if (InitData =3D=3D NULL) { + AsmReadGdtr (&Gdtr); + if ((Buffer =3D=3D NULL) && (BufferSize =3D=3D NULL)) { SetMem (mNewGdt, sizeof (mNewGdt), 0); - - AsmReadIdtr (&Idtr); - AsmReadGdtr (&Gdtr); - - EssData.X64.Revision =3D CPU_EXCEPTION_INIT_DATA_REV; - EssData.X64.KnownGoodStackTop =3D (UINTN)mNewStack + sizeof (= mNewStack); - EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_= LIST; - EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_= NUMBER; - EssData.X64.IdtTable =3D (VOID *)Idtr.Base; - EssData.X64.IdtTableSize =3D Idtr.Limit + 1; - EssData.X64.GdtTable =3D mNewGdt; - EssData.X64.GdtTableSize =3D sizeof (mNewGdt); - EssData.X64.ExceptionTssDesc =3D mNewGdt + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss =3D mNewGdt + Gdtr.Limit + 1 + = CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; - - InitData =3D &EssData; + StackTop =3D (UINTN)mNewStack + sizeof (mNewStack); + NewGdtTable =3D mNewGdt; + } else { + if (BufferSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + NeedBufferSize =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_KNOWN_GOOD_= STACK_SIZE + // Stack size + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE + Gdtr.Limit + 1 + = // GDT size + sizeof (IA32_TSS_DESCRIPTOR); = // Make sure GDT table alignment + if (*BufferSize < NeedBufferSize) { + *BufferSize =3D NeedBufferSize; + return EFI_BUFFER_TOO_SMALL; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + StackTop =3D (UINTN)Buffer + CPU_STACK_SWITCH_EXCEPTION_NUMBER * CP= U_KNOWN_GOOD_STACK_SIZE; + NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); } =20 - return ArchSetupExceptionStack (InitData); + AsmReadIdtr (&Idtr); + EssData.X64.KnownGoodStackTop =3D StackTop; + EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; + EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; + EssData.X64.IdtTable =3D (VOID *)Idtr.Base; // Won't c= hange IDT table in this function + EssData.X64.IdtTableSize =3D Idtr.Limit + 1; + EssData.X64.GdtTable =3D NewGdtTable; + EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + CPU_TSS_S= IZE + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + + return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index f13e8e7020..fa62074023 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file IA32 CPU Exception Handler functons. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -132,7 +132,6 @@ ArchSetupExceptionStack ( EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.Revision !=3D CPU_EXCEPTION_INIT_DATA_REV) || (StackSwitchData->Ia32.KnownGoodStackTop =3D=3D 0) || (StackSwitchData->Ia32.KnownGoodStackSize =3D=3D 0) || (StackSwitchData->Ia32.StackSwitchExceptions =3D=3D NULL) || diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index 494c2ab433..2868560855 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -151,25 +151,71 @@ InitializeCpuExceptionHandlers ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { - if (InitData =3D=3D NULL) { + CPU_EXCEPTION_INIT_DATA EssData; + IA32_DESCRIPTOR Idtr; + IA32_DESCRIPTOR Gdtr; + UINTN NeedBufferSize; + UINTN StackTop; + UINT8 *NewGdtTable; + + if ((Buffer =3D=3D NULL) && (BufferSize =3D=3D NULL)) { return EFI_UNSUPPORTED; } =20 - return ArchSetupExceptionStack (InitData); + if (BufferSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + AsmReadGdtr (&Gdtr); + + NeedBufferSize =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_KNOWN_GOOD_ST= ACK_SIZE + // Stack size + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE + Gdtr.Limit + 1 + = // GDT size + sizeof (IA32_TSS_DESCRIPTOR); = // Make sure GDT table alignment + + if (*BufferSize < NeedBufferSize) { + *BufferSize =3D NeedBufferSize; + return EFI_BUFFER_TOO_SMALL; + } + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + StackTop =3D (UINTN)Buffer + CPU_STACK_SWITCH_EXCEPTION_NUMBER * CPU_= KNOWN_GOOD_STACK_SIZE; + NewGdtTable =3D ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); + + AsmReadIdtr (&Idtr); + EssData.X64.KnownGoodStackTop =3D StackTop; + EssData.X64.KnownGoodStackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions =3D CPU_STACK_SWITCH_EXCEPTION_LI= ST; + EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NU= MBER; + EssData.X64.IdtTable =3D (VOID *)Idtr.Base; // Won't c= hange IDT table in this function + EssData.X64.IdtTableSize =3D Idtr.Limit + 1; + EssData.X64.GdtTable =3D NewGdtTable; + EssData.X64.GdtTableSize =3D CPU_TSS_DESC_SIZE + CPU_TSS_S= IZE + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDesc =3D NewGdtTable + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss =3D NewGdtTable + Gdtr.Limit + 1 = + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE; + + return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index cf5bfe4083..7c2ec3b2db 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -1,7 +1,7 @@ ## @file # CPU Exception Handler library instance for PEI module. # -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -56,6 +56,8 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 4313cc5582..ad5e0e9ed4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -201,20 +201,23 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c index 1c97dab926..46a86ad2c6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c @@ -97,20 +97,23 @@ RegisterCpuInterruptHandler ( =20 /** Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. =20 - InitData is optional and processor arch dependent. - - @param[in] InitData Pointer to data optional for information about= how - to assign stacks for certain exception handler= s. + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. =20 @retval EFI_SUCCESS The stacks are assigned successfully. @retval EFI_UNSUPPORTED This function is not supported. - + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. **/ EFI_STATUS EFIAPI InitializeSeparateExceptionStacks ( - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN VOID *Buffer, + IN OUT UINTN *BufferSize ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index cd7dccd481..ff0dde4f12 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file x64 CPU Exception Handler. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -136,7 +136,6 @@ ArchSetupExceptionStack ( UINTN GdtSize; =20 if ((StackSwitchData =3D=3D NULL) || - (StackSwitchData->Ia32.Revision !=3D CPU_EXCEPTION_INIT_DATA_REV) || (StackSwitchData->X64.KnownGoodStackTop =3D=3D 0) || (StackSwitchData->X64.KnownGoodStackSize =3D=3D 0) || (StackSwitchData->X64.StackSwitchExceptions =3D=3D NULL) || --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91690): https://edk2.groups.io/g/devel/message/91690 Mute This Topic: https://groups.io/mt/92543320/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 03:45:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91691+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91691+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658476683; cv=none; d=zohomail.com; s=zohoarc; b=UzsUZHOrSv+wVXl+HOutfPJy7mggPfbqlOodLWT99LNGs9GjQsG8guekv3j+XXpBea+ItD4XqvMCLvbWn+LDiti7gmaLT4E4ZRYOv+iKOw3D998PwCFHWjdEtYcZTMQUj3Btp/EsYF0Xo9b5cqRWNtZhKPWe5QwO1pu+juYiORo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658476683; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rg4Ufw+n1qfZC5zB/9tGZ1B2/SNbmSJlkcYzfLbM4B8=; b=MhZIAUqzRt4ywfIjOBCVBLUgqiOLGNmDYTzbBPTdwjb2mdXLFOn5RPB2xS8or/Td3PPWTDvDFPclL8SI2AZzp08Jk/6XYJiN933a8aWrV8Y9iQZOFLq6YehbdVfGAu1bNsopJoSXfPwUaU6oG7Utmk4y/SIoTjuTayZTx0g2Vr0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91691+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658476683699454.24700651142234; Fri, 22 Jul 2022 00:58:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sFH3YY1788612xOuDpDIqSoE; Fri, 22 Jul 2022 00:58:03 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web10.5439.1658476676550625421 for ; Fri, 22 Jul 2022 00:58:02 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10415"; a="351257873" X-IronPort-AV: E=Sophos;i="5.93,185,1654585200"; d="scan'208";a="351257873" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2022 00:58:02 -0700 X-IronPort-AV: E=Sophos;i="5.93,185,1654585200"; d="scan'208";a="626468609" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.141]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2022 00:57:59 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Dandan Bi , Liming Gao , Jian J Wang , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH 2/2] MdeModulePkg: Move CPU_EXCEPTION_INIT_DATA to UefiCpuPkg Date: Fri, 22 Jul 2022 15:57:37 +0800 Message-Id: <20220722075737.897-3-zhiguang.liu@intel.com> In-Reply-To: <20220722075737.897-1-zhiguang.liu@intel.com> References: <20220722075737.897-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: hWTRHLgBpdZVHJH0u4T3UdS7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658476683; bh=NfNUW8fkxpfloAubsmSXNiTzbgnz6xYruBd8PSEv0Is=; h=Cc:Date:From:Reply-To:Subject:To; b=cOY7sBz7/2YoAeT1Mv+Ul18FVJPAKnShhHEYiTh1D7QOiYOphQyMfpHSOzvgDeTJKM9 g0rIpZgS6nqd2guO2D80bmXTg5t8rEMAyb2vXc0OjYUPF+E53UCLTKNGKQWtPUEnSc06S hJ5XqVGjSsAFgdfVbmIeHUg7BZJxfLisOTw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658476684591100009 Content-Type: text/plain; charset="utf-8" Since the API InitializeSeparateExceptionStacks is simplified and does't use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become a inner implementation of CpuExcetionHandlerLib. Remove it from MdeModulePkg. Also, two fields (Revision and InitDefaultHandlers)are useless, can be removed. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Dandan Bi Cc: Liming Gao Cc: Jian J Wang Cc: Ard Biesheuvel Cc: Sami Mujawar Signed-off-by: Zhiguang Liu --- .../Include/Library/CpuExceptionHandlerLib.h | 67 ------------------- .../CpuExceptionCommon.h | 59 +++++++++++++++- 2 files changed, 58 insertions(+), 68 deletions(-) diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 8d44ed916a..94e9b20ae1 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -13,73 +13,6 @@ #include #include =20 -#define CPU_EXCEPTION_INIT_DATA_REV 1 - -typedef union { - struct { - // - // Revision number of this structure. - // - UINT32 Revision; - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - // - // Flag to indicate if default handlers should be initialized or not. - // - BOOLEAN InitDefaultHandlers; - } Ia32, X64; -} CPU_EXCEPTION_INIT_DATA; - /** Initializes all CPU exceptions entries and provides the default exceptio= n handlers. =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 0f012bccde..a42e19b54a 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -1,7 +1,7 @@ /** @file Common header file for CPU Exception Handler Library. =20 - Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -49,6 +49,63 @@ =20 #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) =20 +typedef union { + struct { + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; + } Ia32, X64; +} CPU_EXCEPTION_INIT_DATA; + // // Record exception handler information // --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91691): https://edk2.groups.io/g/devel/message/91691 Mute This Topic: https://groups.io/mt/92543321/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-