From nobody Sat May 4 06:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91613+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91613+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658370556; cv=none; d=zohomail.com; s=zohoarc; b=gDWQYn3ul6LFbokOuFzinWENof91+P+qWtbYZRDG+cMyfWNN9RrhyZYmkSLa919FSZ00uBnfUPwb6tI7Rk6PF0c70SXNwBDytp9SBO/hoXNihvWQ4K9SWKkjFkYR+AGsbxR1xdODzQiy0MAC43hr5qA0hJGV4D5WGFg6jkRd2pY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658370556; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=SiwJf1HLwO14agGA7OBotewfldcO5JONxAYa4TRasxs=; b=P5ht2qyfcAYUq1xJh8uc/hZGQHvKSsmTmtKsc5Oa/VjUcHlsSA6mgEZ4sHfqvR+4UWAhGVArlrT6D+2LgmqqI9vW8ycGVB3JHMx8D/BAi2kRtn+km0jiM7XboAwGaj190T2HMwj8gLj4maCP1lyUkuvxSApTlNvLl7YF47s0R3M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91613+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658370556461151.85392075127845; Wed, 20 Jul 2022 19:29:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dBJIYY1788612xVJMP9dqgmx; Wed, 20 Jul 2022 19:29:16 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web08.1491.1658370554937471591 for ; Wed, 20 Jul 2022 19:29:15 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10414"; a="284489787" X-IronPort-AV: E=Sophos;i="5.92,288,1650956400"; d="scan'208";a="284489787" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2022 19:29:06 -0700 X-IronPort-AV: E=Sophos;i="5.92,288,1650956400"; d="scan'208";a="656538938" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.255.228.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2022 19:29:06 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. Date: Wed, 20 Jul 2022 19:28:37 -0700 Message-Id: <20220721022837.4137-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: zRY3RtVh7ezhsHFPWle1eJyUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658370556; bh=N92mhTikLt76aULybsT6sx1UsnzNKlLDVlzEeWXUiLo=; h=Cc:Date:From:Reply-To:Subject:To; b=sA/o8+B7uTjXsC8GXCNi1+DSNPUpveCnKIhqpYPmY4lSlefYqxowfoJQEnHsU9ChlcV DyplyybhauojohDhfaZjIIdCNtMBzNLWELUL7KmEq01NenHf8w/0xXTxg17rHuk6CxFqA NREgEh+Ig/6tMe1+k5GBTQ26BhMoFLH1/Fw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658370558131100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3993 Adding the missing FSPI_ARCH_UPD, FSP_GLOBAL_DATA_VERSION bumpping up, and some comments for clarification. Also fixed a bug in SplitFspBin.py for FSP-I support. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/Include/FspEas/FspApi.h | 71 +++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++------- IntelFsp2Pkg/Include/FspGlobalData.h | 2 +- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 21 +++++++++++++++++++-- IntelFsp2Pkg/Tools/SplitFspBin.py | 2 +- 4 files changed, 85 insertions(+), 11 deletions(-) diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index bf46f13f73..3f368574e8 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -1,6 +1,6 @@ /** @file Intel FSP API definition from Intel Firmware Support Package External - Architecture Specification v2.0 - v2.2 + Architecture Specification v2.0 and above. =20 Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -100,13 +100,14 @@ typedef struct { /// "XXXXXX_T" for FSP-T /// "XXXXXX_M" for FSP-M /// "XXXXXX_S" for FSP-S + /// "XXXXXX_I" for FSP-I /// Where XXXXXX is an unique signature /// UINT64 Signature; /// /// Revision of the Data structure. - /// For FSP spec 2.0/2.1 value is 1. - /// For FSP spec 2.2 value is 2. + /// For FSP spec 2.0/2.1, this value is 1 and only FSPM_UPD having ARC= H_UPD. + /// For FSP spec 2.2 and above, this value is 2 and ARCH_UPD present i= n all UPD structures. /// UINT8 Revision; UINT8 Reserved[23]; @@ -134,7 +135,7 @@ typedef struct { } FSPT_ARCH_UPD; =20 /// -/// FSPT_ARCH2_UPD Configuration. +/// FSPT_ARCH2_UPD Configuration for FSP 2.4 and above. /// typedef struct { /// @@ -196,7 +197,7 @@ typedef struct { } FSPM_ARCH_UPD; =20 /// -/// FSPM_ARCH2_UPD Configuration. +/// FSPM_ARCH2_UPD Configuration for FSP 2.4 and above. /// typedef struct { /// @@ -209,6 +210,13 @@ typedef struct { /// UINT32 Length; /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// This value is deprecated starting with v2.4 of the FSP specification, + /// and will be removed in an upcoming version of the FSP specification. + /// + EFI_PHYSICAL_ADDRESS NvsBufferPtr; + /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// @@ -232,7 +240,7 @@ typedef struct { /// This value is only valid if Revision is >=3D 2. /// EFI_PHYSICAL_ADDRESS FspEventHandler; - UINT8 Reserved1[24]; + UINT8 Reserved1[16]; } FSPM_ARCH2_UPD; =20 /// @@ -265,7 +273,7 @@ typedef struct { } FSPS_ARCH_UPD; =20 /// -/// FSPS_ARCH2_UPD Configuration. +/// FSPS_ARCH2_UPD Configuration for FSP 2.4 and above. /// typedef struct { /// @@ -285,6 +293,40 @@ typedef struct { UINT8 Reserved1[16]; } FSPS_ARCH2_UPD; =20 +/// +/// FSPI_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length of the structure in bytes. The current value for this field i= s 32. + /// + UINT32 Length; + /// + /// The physical memory-mapped base address of the bootloader SMM firmwa= re volume (FV). + /// + EFI_PHYSICAL_ADDRESS BootloaderSmmFvBaseAddress; + /// + /// The length in bytes of the bootloader SMM firmware volume (FV). + /// + UINT64 BootloaderSmmFvLength; + /// + /// The physical memory-mapped base address of the bootloader SMM FV con= text data. + /// This data is provided to bootloader SMM drivers through a HOB by the= FSP MM Foundation. + /// + EFI_PHYSICAL_ADDRESS BootloaderSmmFvContextData; + /// + /// The length in bytes of the bootloader SMM FV context data. + /// This data is provided to bootloader SMM drivers through a HOB by the= FSP MM Foundation. + /// + UINT16 BootloaderSmmFvContextDataLength; + UINT8 Reserved1[24]; +} FSPI_ARCH_UPD; + /// /// FSPT_UPD_COMMON Configuration. /// @@ -393,6 +435,21 @@ typedef struct { FSPS_ARCH2_UPD FspsArchUpd; } FSPS_UPD_COMMON_FSP24; =20 +/// +/// FSPI_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPI_ARCH_UPD Configuration. + /// + FSPI_ARCH_UPD FspiArchUpd; +} FSPI_UPD_COMMON; + /// /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. /// diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 697b20ed4c..cf94f7b6a5 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -12,7 +12,7 @@ =20 #define FSP_IN_API_MODE 0 #define FSP_IN_DISPATCH_MODE 1 -#define FSP_GLOBAL_DATA_VERSION 1 +#define FSP_GLOBAL_DATA_VERSION 0x2 =20 #pragma pack(1) =20 diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Inclu= de/Guid/FspHeaderFile.h index c7fb63168f..5381716d81 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -52,7 +52,7 @@ typedef struct { UINT8 Reserved1[2]; /// /// Byte 0x0A: Indicates compliance with a revision of this specificatio= n in the BCD format. - /// For revision v2.3 the value will be 0x23. + /// For revision v2.4 the value will be 0x24. /// UINT8 SpecVersion; /// @@ -93,11 +93,28 @@ typedef struct { /// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Grap= hics Display. /// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the opti= onal Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid= if FSP HeaderRevision is >=3D 4. /// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-= bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode int= erfaces. This bit is only valid if FSP HeaderRevision is >=3D 7. - /// Bits 15:3 - Reserved + /// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP ut= ilizes the FSP Variable Services defined in Section 9.6 to store non-volati= le data. This bit is only valid if FSP HeaderRevision is >=3D 7. + /// Bits 15:4 - Reserved /// UINT16 ImageAttribute; /// /// Byte 0x22: Attributes of the FSP Component. + /// Bit 0 - Build Type + /// 0 - Debug Build + /// 1 - Release Build + /// Bit 1 - Release Type + /// 0 - Test Release + /// 1 - Official Release + /// Bit 11:2 - Reserved + /// Bits 15:12 - Component Type + /// 0000 - Reserved + /// 0001 - FSP-T + /// 0010 - FSP-M + /// 0011 - FSP-S + /// 0100 - FSP-I (FSP SMM) + /// 0101 to 0111 - Reserved + /// 1000 - FSP-O + /// 1001 to 1111 - Reserved /// UINT16 ComponentAttribute; /// diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFs= pBin.py index 317d9c1fa0..ddabab7d8c 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -492,7 +492,7 @@ class FspImage: self.FihOffset =3D fihoff self.Offset =3D offset self.FvIdxList =3D [] - self.Type =3D "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> = 12) & 0x0F] + self.Type =3D "XTMSIXXXOXXXXXXX"[(fih.ComponentAttribute >> 1= 2) & 0x0F] self.PatchList =3D patch self.PatchList.append(fihoff + 0x1C) =20 --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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