From nobody Sat May 4 20:16:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91544+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91544+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658250586; cv=none; d=zohomail.com; s=zohoarc; b=DIdhjxDyz5bxxbgSjXdvFoRu8HZmdzO+WMgFUZ7eImwh7LBMd8IfSXwCoEUWRDN7M2ljk24Ac7XqDajWgcusTIdey1V7BTenOinFQIY7P5PblKFHGm7DfxwcaIAfzuxuKCwEQJqxwP/3ElaPzOOoGv3nbuVcTDO4fa5Ry8z7K6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658250586; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=mDIAO/443lxPgFEEe68O8lPgmPUySBBLloSWEfbE/Uk=; b=H1kbhx8oMzL4yqEwao6aEHpwIvLOTvQ9iPXpe9PRvNf8SNkyXmMM3b6smGX5X5xaUlan/llvJrnaCom6MfwhSwCxWzPCK0K2ZYJDvLKNOjvSLX+bndcEi18P7DCvBlCOMFc+fbCdhgIF22pnzqk5dCP6P9JsOfnHastdpD27o94= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91544+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165825058594662.09420054118664; Tue, 19 Jul 2022 10:09:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VwXcYY1788612xAHvSjOon2V; Tue, 19 Jul 2022 10:09:45 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web08.43290.1658250584292997082 for ; Tue, 19 Jul 2022 10:09:44 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10413"; a="266947141" X-IronPort-AV: E=Sophos;i="5.92,284,1650956400"; d="scan'208";a="266947141" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2022 10:09:27 -0700 X-IronPort-AV: E=Sophos;i="5.92,284,1650956400"; d="scan'208";a="700530220" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.209.104.23]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2022 10:09:27 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Hongbin1 Zhang , Nate DeSimone , Star Zeng , Chasel Chiu Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support. Date: Tue, 19 Jul 2022 10:09:15 -0700 Message-Id: <20220719170916.3060-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: va5NHjluKJXOxlGXJhiGz7VHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658250585; bh=bx2uGqO7IXPCvzBY6AQORbMV6+G+HCpk9svAqjun2VI=; h=Cc:Date:From:Reply-To:Subject:To; b=gukREIU1/XWMYMpeewLSu/jQH3zg+xxa4YXL0s/lUOBU/0leEYI20BYTeTdHpxdUPwp gyAyswQ0q3rffOuk+J6ESAERxdC/m6UNNxFY3r/RXUbxCJdQG6DKBgGvpkXeWdO9292tU 3G0xy2vKc1d3rfgC7fd0t0npDOErLqa1m1g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658250588105100001 Content-Type: text/plain; charset="utf-8" From: Hongbin1 Zhang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3993 Add FSP-I API entry point for SMM support. Also update 64bit API entry code to assign ApiIdx to RAX to avoid confusion. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Signed-off-by: Hongbin1 Zhang Reviewed-by: Nate DeSimone --- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 13 +++++++++++++ IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf | 54 +++++++++++++++++++++= +++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm | 44 +++++++++++++++++++++= +++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm | 8 ++++---- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm | 44 +++++++++++++++++++++= +++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 4 ++-- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 4 ++-- IntelFsp2Pkg/Include/FspEas/FspApi.h | 57 +++++++++++++++++++++= +++++++++++++++++------------------- IntelFsp2Pkg/Include/FspGlobalData.h | 53 +++++++++++++++++++++= +++++++------------------------- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 22 +++++++++++++++------- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 1 + IntelFsp2Pkg/Tools/GenCfgOpt.py | 26 ++++++++++++++++-----= ----- IntelFsp2Pkg/Tools/SplitFspBin.py | 6 +++--- 13 files changed, 264 insertions(+), 72 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index e22a88cc84..35d223a404 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -71,6 +71,19 @@ FspApiCallingCheck ( Status =3D EFI_INVALID_PARAMETER; } } + } else if (ApiIdx =3D=3D FspSmmInitApiIndex) { + // + // FspSmmInitApiIndex check + // + if ((FspData =3D=3D NULL) || ((UINTN)FspData =3D=3D MAX_ADDRESS) || ((= UINTN)FspData =3D=3D MAX_UINT32)) { + Status =3D EFI_UNSUPPORTED; + } else { + if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { + Status =3D EFI_UNSUPPORTED; + } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiP= aram))) { + Status =3D EFI_INVALID_PARAMETER; + } + } } else { Status =3D EFI_UNSUPPORTED; } diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreI.inf new file mode 100644 index 0000000000..d31576c00b --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf @@ -0,0 +1,54 @@ +## @file +# Sec Core for FSP +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FspSecCoreI + FILE_GUID =3D 558782b5-782d-415e-ab9e-0ceb79dc3425 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + SecFspApiChk.c + SecFsp.h + +[Sources.X64] + X64/FspApiEntryI.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + +[Sources.IA32] + Ia32/FspApiEntryI.nasm + Ia32/FspApiEntryCommon.nasm + Ia32/FspHelper.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + + diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryI.nasm new file mode 100644 index 0000000000..e9365d6832 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm @@ -0,0 +1,44 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + jmp $ + +;-------------------------------------------------------------------------= --- +; FspSmmInit API +; +; This FSP API will notify the FSP about the different phases in the boot +; process +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspSmmInitApi) +ASM_PFX(FspSmmInitApi): + mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + ; Add reference to APIs so that it will not be optimized by compiler + jmp ASM_PFX(FspSmmInitApi) diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm b/IntelFsp2Pkg= /FspSecCore/X64/Fsp22ApiEntryS.nasm index c739793a39..4202925701 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm @@ -24,7 +24,7 @@ STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a gene= ral purpose register * ;-------------------------------------------------------------------------= --- global ASM_PFX(NotifyPhaseApi) ASM_PFX(NotifyPhaseApi): - mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex + mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- @@ -36,7 +36,7 @@ ASM_PFX(NotifyPhaseApi): ;-------------------------------------------------------------------------= --- global ASM_PFX(FspSiliconInitApi) ASM_PFX(FspSiliconInitApi): - mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex + mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- @@ -54,7 +54,7 @@ ASM_PFX(FspSiliconInitApi): =20 global ASM_PFX(FspMultiPhaseSiInitApi) ASM_PFX(FspMultiPhaseSiInitApi): - mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex + mov rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- @@ -68,7 +68,7 @@ ASM_PFX(FspApiCommonContinue): ; ; Handle FspMultiPhaseSiInitApiIndex API ; - cmp eax, 6 + cmp rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex jnz NotMultiPhaseSiInitApi =20 PUSHA_64 diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryI.nasm new file mode 100644 index 0000000000..e74bf0a26b --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm @@ -0,0 +1,44 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + jmp $ + +;-------------------------------------------------------------------------= --- +; FspSmmInit API +; +; This FSP API will notify the FSP about the different phases in the boot +; process +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspSmmInitApi) +ASM_PFX(FspSmmInitApi): + mov rax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + ; Add reference to APIs so that it will not be optimized by compiler + jmp ASM_PFX(FspSmmInitApi) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryM.nasm index 4d965e14a7..dacf515845 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm @@ -55,7 +55,7 @@ FSP_HEADER_CFGREG_OFFSET EQU 24h ;-------------------------------------------------------------------------= --- global ASM_PFX(FspMemoryInitApi) ASM_PFX(FspMemoryInitApi): - mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex + mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- @@ -66,7 +66,7 @@ ASM_PFX(FspMemoryInitApi): ;-------------------------------------------------------------------------= --- global ASM_PFX(TempRamExitApi) ASM_PFX(TempRamExitApi): - mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex + mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryS.nasm index f863ef0078..7e211fb207 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm @@ -21,7 +21,7 @@ extern ASM_PFX(FspApiCommon) ;-------------------------------------------------------------------------= --- global ASM_PFX(NotifyPhaseApi) ASM_PFX(NotifyPhaseApi): - mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex + mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- @@ -33,7 +33,7 @@ ASM_PFX(NotifyPhaseApi): ;-------------------------------------------------------------------------= --- global ASM_PFX(FspSiliconInitApi) ASM_PFX(FspSiliconInitApi): - mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex + mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex jmp ASM_PFX(FspApiCommon) =20 ;-------------------------------------------------------------------------= --- diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index b36bc2b9ae..1d6c2fb63d 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -135,18 +135,18 @@ typedef struct { /// /// Revision of the structure is 2 for this version of the specification. /// - UINT8 Revision; - UINT8 Reserved[3]; + UINT8 Revision; + UINT8 Reserved[3]; /// /// Length of the structure in bytes. The current value for this field i= s 32. /// - UINT32 Length; + UINT32 Length; /// /// FspDebugHandler Optional debug handler for the bootloader to receive= debug messages /// occurring during FSP execution. /// - EFI_PHYSICAL_ADDRESS FspDebugHandler; - UINT8 Reserved1[16]; + EFI_PHYSICAL_ADDRESS FspDebugHandler; + UINT8 Reserved1[16]; } FSPT_ARCH2_UPD; =20 /// @@ -197,37 +197,37 @@ typedef struct { /// /// Revision of the structure is 3 for this version of the specification. /// - UINT8 Revision; - UINT8 Reserved[3]; + UINT8 Revision; + UINT8 Reserved[3]; /// /// Length of the structure in bytes. The current value for this field i= s 64. /// - UINT32 Length; + UINT32 Length; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - EFI_PHYSICAL_ADDRESS StackBase; + EFI_PHYSICAL_ADDRESS StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. /// - UINT64 StackSize; + UINT64 StackSize; /// /// Size of memory to be reserved by FSP below "top /// of low usable memory" for bootloader usage. /// - UINT32 BootLoaderTolumSize; + UINT32 BootLoaderTolumSize; /// /// Current boot mode. /// - UINT32 BootMode; + UINT32 BootMode; /// /// Optional event handler for the bootloader to be informed of events o= ccurring during FSP execution. /// This value is only valid if Revision is >=3D 2. /// - EFI_PHYSICAL_ADDRESS FspEventHandler; - UINT8 Reserved1[24]; + EFI_PHYSICAL_ADDRESS FspEventHandler; + UINT8 Reserved1[24]; } FSPM_ARCH2_UPD; =20 /// @@ -266,18 +266,18 @@ typedef struct { /// /// Revision of the structure is 2 for this version of the specification. /// - UINT8 Revision; - UINT8 Reserved[3]; + UINT8 Revision; + UINT8 Reserved[3]; /// /// Length of the structure in bytes. The current value for this field i= s 32. /// - UINT32 Length; + UINT32 Length; /// /// FspEventHandler Optional event handler for the bootloader to be info= rmed of events /// occurring during FSP execution. /// - EFI_PHYSICAL_ADDRESS FspEventHandler; - UINT8 Reserved1[16]; + EFI_PHYSICAL_ADDRESS FspEventHandler; + UINT8 Reserved1[16]; } FSPS_ARCH2_UPD; =20 /// @@ -609,4 +609,23 @@ EFI_STATUS IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr ); =20 +/** + This FSP API initializes SMM and provide any OS runtime silicon services, + including Reliability, Availability, and Serviceability (RAS) features i= mplemented by the CPU. + + @param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure. + If NULL, FSP will use the default paramete= rs. + + @retval EFI_SUCCESS FSP execution environment was initia= lized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status co= des will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_SMM_INIT)( + IN VOID *FspiUpdDataPtr + ); + #endif diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 445540abfa..697b20ed4c 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -10,9 +10,9 @@ =20 #include =20 -#define FSP_IN_API_MODE 0 -#define FSP_IN_DISPATCH_MODE 1 -#define FSP_GLOBAL_DATA_VERSION 1 +#define FSP_IN_API_MODE 0 +#define FSP_IN_DISPATCH_MODE 1 +#define FSP_GLOBAL_DATA_VERSION 1 =20 #pragma pack(1) =20 @@ -24,16 +24,17 @@ typedef enum { TempRamExitApiIndex, FspSiliconInitApiIndex, FspMultiPhaseSiInitApiIndex, + FspSmmInitApiIndex, FspApiIndexMax } FSP_API_INDEX; =20 typedef struct { - VOID *DataPtr; - UINTN MicrocodeRegionBase; - UINTN MicrocodeRegionSize; - UINTN CodeRegionBase; - UINTN CodeRegionSize; - UINTN Reserved; + VOID *DataPtr; + UINTN MicrocodeRegionBase; + UINTN MicrocodeRegionSize; + UINTN CodeRegionBase; + UINTN CodeRegionSize; + UINTN Reserved; } FSP_PLAT_DATA; =20 #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') @@ -41,28 +42,28 @@ typedef struct { #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF =20 typedef struct { - UINT32 Signature; - UINT8 Version; - UINT8 Reserved1[3]; + UINT32 Signature; + UINT8 Version; + UINT8 Reserved1[3]; /// /// Offset 0x08 /// - UINTN CoreStack; - UINTN Reserved2; + UINTN CoreStack; + UINTN Reserved2; /// /// IA32: Offset 0x10; X64: Offset 0x18 /// - UINT32 StatusCode; - UINT8 ApiIdx; + UINT32 StatusCode; + UINT8 ApiIdx; /// /// 0: FSP in API mode; 1: FSP in DISPATCH mode /// - UINT8 FspMode; - UINT8 OnSeparateStack; - UINT8 Reserved3; - UINT32 NumberOfPhases; - UINT32 PhasesExecuted; - UINT32 Reserved4[8]; + UINT8 FspMode; + UINT8 OnSeparateStack; + UINT8 Reserved3; + UINT32 NumberOfPhases; + UINT32 PhasesExecuted; + UINT32 Reserved4[8]; /// /// IA32: Offset 0x40; X64: Offset 0x48 /// Start of UINTN and pointer section @@ -75,21 +76,23 @@ typedef struct { VOID *TempRamInitUpdPtr; VOID *MemoryInitUpdPtr; VOID *SiliconInitUpdPtr; + VOID *SmmInitUpdPtr; /// - /// IA32: Offset 0x64; X64: Offset 0x90 + /// IA32: Offset 0x68; X64: Offset 0x98 /// To store function parameters pointer /// so it can be retrieved after stack switched. /// VOID *FunctionParameterPtr; FSP_INFO_HEADER *FspInfoHeader; VOID *UpdDataPtr; + UINTN Reserved5; /// /// End of UINTN and pointer section /// - UINT8 Reserved5[16]; + UINT8 Reserved6[16]; UINT32 PerfSig; UINT16 PerfLen; - UINT16 Reserved6; + UINT16 Reserved7; UINT32 PerfIdx; UINT64 PerfData[32]; } FSP_GLOBAL_DATA; diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Inclu= de/Guid/FspHeaderFile.h index c660defac3..c7fb63168f 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -26,13 +26,13 @@ =20 #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') =20 -#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0 -#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1 -#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2 -#define FSP_IA32 0 -#define FSP_X64 1 +#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0 +#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1 +#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2 +#define FSP_IA32 0 +#define FSP_X64 1 =20 -#pragma pack(1) + #pragma pack(1) =20 /// /// FSP Information Header as described in FSP v2.0 Spec section 5.1.1. @@ -159,6 +159,14 @@ typedef struct { /// Byte 0x4E: Reserved4. /// UINT16 Reserved4; + /// + /// Byte 0x50: Offset for the API for the Multi-Phase memory initializat= ion. + /// + UINT32 FspMultiPhaseMemInitEntryOffset; + /// + /// Byte 0x54: Offset for the API to initialize SMM. + /// + UINT32 FspSmmInitEntryOffset; } FSP_INFO_HEADER; =20 /// @@ -240,7 +248,7 @@ typedef struct { // UINT32 PatchData[]; } FSP_PATCH_TABLE; =20 -#pragma pack() + #pragma pack() =20 extern EFI_GUID gFspHeaderFileGuid; =20 diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index 7cf7e88245..b2d7867880 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -68,6 +68,7 @@ IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf + IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf =20 diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt= .py index c4fb1f1bb2..128b896592 100644 --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -953,8 +953,8 @@ EndList return NoFileChange =20 def CreateSplitUpdTxt (self, UpdTxtFile): - GuidList =3D ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_U= PD_TOOL_GUID'] - SignatureList =3D ['0x545F', '0x4D5F','0x535F'] # _T, _M, = and _S signature for FSPT, FSPM, FSPS + GuidList =3D ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_U= PD_TOOL_GUID','FSP_I_UPD_TOOL_GUID'] + SignatureList =3D ['0x545F', '0x4D5F','0x535F','0x495F'] # = _T, _M, _S and _I signature for FSPT, FSPM, FSPS, FSPI for Index in range(len(GuidList)): UpdTxtFile =3D '' FvDir =3D self._FvDir @@ -1288,19 +1288,21 @@ EndList Chars.append(chr(Value & 0xFF)) Value =3D Value >> 8 SignatureStr =3D ''.join(Chars) - # Signature will be _T / _M / _S for FSPT / FSPM / FSPS acc= ordingly + # Signature will be _T / _M / _S / _I for FSPT / FSPM / FSP= S /FSPI accordingly if '_T' in SignatureStr[6:6+2]: TxtBody.append("#define FSPT_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) elif '_M' in SignatureStr[6:6+2]: TxtBody.append("#define FSPM_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) elif '_S' in SignatureStr[6:6+2]: TxtBody.append("#define FSPS_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) + elif '_I' in SignatureStr[6:6+2]: + TxtBody.append("#define FSPI_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) TxtBody.append("\n") =20 for Region in ['UPD']: UpdOffsetTable =3D [] - UpdSignature =3D ['0x545F', '0x4D5F', '0x535F'] #['_T', '_M'= , '_S'] signature for FSPT, FSPM, FSPS - UpdStructure =3D ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD'] + UpdSignature =3D ['0x545F', '0x4D5F', '0x535F', '0x495F'] #[= '_T', '_M', '_S', '_I'] signature for FSPT, FSPM, FSPS, FSPI + UpdStructure =3D ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD', 'FSPI_UP= D'] for Item in self._CfgItemList: if Item["cname"] =3D=3D 'Signature' and Item["value"][0:6]= in UpdSignature: Item["offset"] =3D 0 # re-initialize offset to 0 when = new UPD structure starting @@ -1393,11 +1395,12 @@ EndList HeaderTFileName =3D 'FsptUpd.h' HeaderMFileName =3D 'FspmUpd.h' HeaderSFileName =3D 'FspsUpd.h' + HeaderIFileName =3D 'FspiUpd.h' =20 - UpdRegionCheck =3D ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION - UpdConfigCheck =3D ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FS= P_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG - UpdSignatureCheck =3D ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE',= 'FSPS_UPD_SIGNATURE'] - ExcludedSpecificUpd =3D ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_A= RCH_UPD'] + UpdRegionCheck =3D ['FSPT', 'FSPM', 'FSPS', 'FSPI'] # FSPX_UPD= _REGION + UpdConfigCheck =3D ['FSP_T', 'FSP_M', 'FSP_S', 'FSP_I'] # FSP_X_C= ONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG + UpdSignatureCheck =3D ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE',= 'FSPS_UPD_SIGNATURE', 'FSPI_UPD_SIGNATURE'] + ExcludedSpecificUpd =3D ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_A= RCH_UPD', 'FSPI_ARCH_UPD'] ExcludedSpecificUpd1 =3D ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSP= S_ARCH2_UPD'] =20 IncLines =3D [] @@ -1420,6 +1423,9 @@ EndList elif UpdRegionCheck[item] =3D=3D 'FSPS': HeaderFd =3D open(os.path.join(FvDir, HeaderSFileName), "w= ") FileBase =3D os.path.basename(os.path.join(FvDir, HeaderSF= ileName)) + elif UpdRegionCheck[item] =3D=3D 'FSPI': + HeaderFd =3D open(os.path.join(FvDir, HeaderIFileName), "w= ") + FileBase =3D os.path.basename(os.path.join(FvDir, HeaderIF= ileName)) FileName =3D FileBase.replace(".", "_").upper() HeaderFd.write("%s\n" % (__copyright_h__ % date.today().year= )) HeaderFd.write("#ifndef __%s__\n" % FileName) @@ -1696,7 +1702,7 @@ EndList =20 =20 def Usage(): - print ("GenCfgOpt Version 0.57") + print ("GenCfgOpt Version 0.58") print ("Usage:") print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir = [-D Macros]") print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile = [-D Macros]") diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFs= pBin.py index f9151b5afd..317d9c1fa0 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -1,6 +1,6 @@ ## @ SplitFspBin.py # -# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -492,7 +492,7 @@ class FspImage: self.FihOffset =3D fihoff self.Offset =3D offset self.FvIdxList =3D [] - self.Type =3D "XTMSXXXXOXXXXXXX"[(fih.ComponentAttribute >> 1= 2) & 0x0F] + self.Type =3D "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> = 12) & 0x0F] self.PatchList =3D patch self.PatchList.append(fihoff + 0x1C) =20 @@ -869,7 +869,7 @@ def main (): parser_rebase =3D subparsers.add_parser('rebase', help=3D'rebase a F= SP into a new base address') parser_rebase.set_defaults(which=3D'rebase') parser_rebase.add_argument('-f', '--fspbin' , dest=3D'FspBinary', ty= pe=3Dstr, help=3D'FSP binary file path', required =3D True) - parser_rebase.add_argument('-c', '--fspcomp', choices=3D['t','m','s',= 'o'], nargs=3D'+', dest=3D'FspComponent', type=3Dstr, help=3D'FSP componen= t to rebase', default =3D "['t']", required =3D True) + parser_rebase.add_argument('-c', '--fspcomp', choices=3D['t','m','s',= 'o','i'], nargs=3D'+', dest=3D'FspComponent', type=3Dstr, help=3D'FSP comp= onent to rebase', default =3D "['t']", required =3D True) parser_rebase.add_argument('-b', '--newbase', dest=3D'FspBase', nargs= =3D'+', type=3Dstr, help=3D'Rebased FSP binary file name', default =3D '', = required =3D True) parser_rebase.add_argument('-o', '--outdir' , dest=3D'OutputDir', ty= pe=3Dstr, help=3D'Output directory path', default =3D '.') parser_rebase.add_argument('-n', '--outfile', dest=3D'OutputFile', ty= pe=3Dstr, help=3D'Rebased FSP binary file name', default =3D '') --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91544): https://edk2.groups.io/g/devel/message/91544 Mute This Topic: https://groups.io/mt/92487212/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-