From nobody Sun Feb 8 19:38:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91457+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91457+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658150333; cv=none; d=zohomail.com; s=zohoarc; b=JzK+bIxcQXAJkZODvEW1brU7AmbjGiQndwEiujl1ONNwNtt86xBf1tT33EXRORKD2wRZWO3rnB8mctbGC4mYMd+gDiS2BL9T4NFWJ6c+4Nl3vbX/a1FB6SFFzao5o9DOgqIAarOQXstZz55T3Pm8/AFKxZKLtPJ7OUlLefyzkvE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658150333; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pu6EjbWf7ypMo+Bo/RkZOOqBCoRrb3UrtMzdPNyxDAs=; b=nOOEvHw4BOd+QPytBZjcfv5r2vDN0ynR1csxQuJjGLi/myWu/UvP3l3CQy+HaUoDKoht0G3h+/PjCQq3dAheIlcG0sme5ZSbLmqKWvGQUv0PyWALahICQMPmweRViKN45HHH1RZjR9JajsghnFEUP8xFKKp4eZnizfAQNpiwDTk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91457+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658150333776351.97202724486226; Mon, 18 Jul 2022 06:18:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 21VtYY1788612xhogeqcJ0d2; Mon, 18 Jul 2022 06:18:52 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.27105.1658150328221476289 for ; Mon, 18 Jul 2022 06:18:51 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10411"; a="287363967" X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="287363967" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 06:18:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="624725005" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga008.jf.intel.com with ESMTP; 18 Jul 2022 06:18:49 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong Subject: [edk2-devel] [PATCH 08/10] CpuPageTableLib: Fix a bug to avoid unnecessary changing to page table Date: Mon, 18 Jul 2022 21:18:29 +0800 Message-Id: <20220718131831.660-9-ray.ni@intel.com> In-Reply-To: <20220718131831.660-1-ray.ni@intel.com> References: <20220718131831.660-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: COQZgOcP5QhoXibHcotZZo9px1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658150332; bh=dPnlKJ22Sx7+UqNKX8xRaKB3AbF1yrPSVuMNvsOb6QQ=; h=Cc:Date:From:Reply-To:Subject:To; b=rnF48pfZLLEO23sxF8o4wJ8kbhoSrpcwbchqA9ddvFLTR7iP6Q1VnBewvPL2+4Ajo/l +ZoKaI8vU5uLumbHCth8L9MtyGk4oA8NYaNZ7Fp7AyKCDVcAItkhFE+BpLgjirCuJb95p OAH3tgNJ5En7e+LUmm/vT64J+T1ijrt5EDU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658150335588100042 Content-Type: text/plain; charset="utf-8" With the following paging structure that maps [0, 2G] with ReadWrite bit set. PML4[0] --> PDPTE[0] --> PDE[0-255] \-> PDPTE[1] --> PDE[0-255] If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called to change [0, 2M] as read-only, today's logic unnecessarily changes the paging structure in 2 aspects: 1. When setting PageTableBaseAddress in the entry, the code clears all attributes. 2. Even the ReadWrite bit in parent entry is not set, the code clears the ReadWrite bit in the leaf entry. First change is wrong. It should not change other attributes when setting the PA. Second change is unnecessary. Because the parent entry already declares the whole region as read-only, there is no need to clear ReadWrite bit in the leaf entry again. Signed-off-by: Zhiguang Liu Signed-off-by: Ray Ni Cc: Eric Dong --- .../Library/CpuPageTableLib/CpuPageTableMap.c | 41 +++++++++++++++---- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index ac5d1c79f4..1205119fc8 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -27,10 +27,7 @@ PageTableLibSetPte4K ( ) { if (Mask->Bits.PageTableBaseAddress) { - // - // Reset all attributes when the physical address is changed. - // - Pte4K->Uint64 =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) + Offset; + Pte4K->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribu= te) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40); } =20 if (Mask->Bits.Present) { @@ -97,10 +94,7 @@ PageTableLibSetPleB ( ) { if (Mask->Bits.PageTableBaseAddress) { - // - // Reset all attributes when the physical address is changed. - // - PleB->Uint64 =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute= ) + Offset; + PleB->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39); } =20 PleB->Bits.MustBeOne =3D 1; @@ -277,6 +271,7 @@ PageTableLibMapInLevel ( IA32_PAGING_ENTRY OneOfPagingEntry; IA32_MAP_ATTRIBUTE ChildAttribute; IA32_MAP_ATTRIBUTE ChildMask; + IA32_MAP_ATTRIBUTE CurrentMask; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -464,7 +459,35 @@ PageTableLibMapInLevel ( // Create one entry mapping the entire region (1G, 2M or 4K). // if (Modify) { - PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = Mask); + // + // When the inheritable attributes in parent entry could override = the child attributes, + // e.g.: Present/ReadWrite/UserSupervisor is 0 in parent entry, or + // Nx is 1 in parent entry, + // we just skip setting any value to these attributes in child. + // We add assertion to make sure the requested settings don't conf= lict with parent attributes in this case. + // + CurrentMask.Uint64 =3D Mask->Uint64; + if (ParentAttribute->Bits.Present =3D=3D 0) { + CurrentMask.Bits.Present =3D 0; + ASSERT (CreateNew || (Mask->Bits.Present =3D=3D 0) || (Attribute= ->Bits.Present =3D=3D 0)); + } + + if (ParentAttribute->Bits.ReadWrite =3D=3D 0) { + CurrentMask.Bits.ReadWrite =3D 0; + ASSERT (CreateNew || (Mask->Bits.ReadWrite =3D=3D 0) || (Attribu= te->Bits.ReadWrite =3D=3D 0)); + } + + if (ParentAttribute->Bits.UserSupervisor =3D=3D 0) { + CurrentMask.Bits.UserSupervisor =3D 0; + ASSERT (CreateNew || (Mask->Bits.UserSupervisor =3D=3D 0) || (At= tribute->Bits.UserSupervisor =3D=3D 0)); + } + + if (ParentAttribute->Bits.Nx =3D=3D 1) { + CurrentMask.Bits.Nx =3D 0; + ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->Bit= s.Nx =3D=3D 1)); + } + + PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = &CurrentMask); } } else { // --=20 2.35.1.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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