From nobody Tue May 7 09:09:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90783+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90783+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1656313697248314.77872527464194; Mon, 27 Jun 2022 00:08:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id B741YY1788612xBNfTXYBha5; Mon, 27 Jun 2022 00:08:16 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.38794.1656313696151732675 for ; Mon, 27 Jun 2022 00:08:16 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10390"; a="261792947" X-IronPort-AV: E=Sophos;i="5.92,225,1650956400"; d="scan'208";a="261792947" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 00:08:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,225,1650956400"; d="scan'208";a="692489774" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by fmsmga002.fm.intel.com with ESMTP; 27 Jun 2022 00:08:14 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Jenny Huang , Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Fix VTd Queued Invalidation IOTLB descriptor Date: Mon, 27 Jun 2022 15:08:11 +0800 Message-Id: <20220627070811.722-1-w.sheng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: KEtI8FI3eld6cvIRUESXucDgx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1656313696; bh=i3wRbQWMqxEarC7zL78kt2v30VlwL5wgINz6DJ+L4uw=; h=Cc:Date:From:Reply-To:Subject:To; b=Vb8gi8CV5oLKPM1gTQ11pmY6b5ldQOD+YG/UcWayil612OYiy97fxBzuB0R/DqHpCQn /T2ClgyGSOF5sNyPKjiuOXExJAXE7MjD0zs8M+1/FW8rN43yE0bc7jV68edJVe3euEvzI 6WLKEsRRYwVp5P/ZUGYaChhZEr+k1ixV4D4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1656313697743100001 Content-Type: text/plain; charset="utf-8" VTd Queued Invalidation IOTLB descriptor need to use CAP_REG.DWD and CAP_REG.DRD. Queued Invalidation descriptor is a 128 bits value. Register-based invalidation interface supported by hardware implementations of this architecture with Major Version 5 or lower (VER_REG). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3964 Signed-off-by: Sheng Wei Cc: Jenny Huang Cc: Ray Ni Cc: Rangasai V Chaganty --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 32 +++++++++---------- .../VTd/IntelVTdDmarPei/IntelVTdDmarPei.h | 2 +- .../Feature/VTd/IntelVTdDxe/VtdReg.c | 2 +- 3 files changed, 17 insertions(+), 19 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index 0d372f6c..b5b78f77 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -79,7 +79,7 @@ PerpareCacheInvalidationInterface ( IN VTD_UNIT_INFO *VTdUnitInfo ) { - UINT16 QiDescLength; + UINT16 QueueSize; UINT64 Reg64; UINT32 Reg32; VTD_ECAP_REG ECapReg; @@ -122,18 +122,18 @@ PerpareCacheInvalidationInterface ( // Setup the IQ address, size and descriptor width through the Invalidat= ion Queue Address Register // if (VTdUnitInfo->QiDesc =3D=3D NULL) { - VTdUnitInfo->QueueSize =3D 0; - QiDescLength =3D 1 << (VTdUnitInfo->QueueSize + 8); - VTdUnitInfo->QiDesc =3D (QI_DESC *) AllocatePages (EFI_SIZE_TO_PAGES(s= izeof(QI_DESC) * QiDescLength)); + QueueSize =3D 0; + VTdUnitInfo->QiDescLength =3D 1 << (QueueSize + 8); + VTdUnitInfo->QiDesc =3D (QI_DESC *) AllocatePages (EFI_SIZE_TO_PAGES (= sizeof (QI_DESC) * VTdUnitInfo->QiDescLength)); if (VTdUnitInfo->QiDesc =3D=3D NULL) { DEBUG ((DEBUG_ERROR,"Could not Alloc Invalidation Queue Buffer.\n")); return EFI_OUT_OF_RESOURCES; } } =20 - DEBUG ((DEBUG_INFO, "Invalidation Queue Length : %d\n", QiDescLength)); + DEBUG ((DEBUG_INFO, "Invalidation Queue Length : %d\n", VTdUnitInfo->QiD= escLength)); Reg64 =3D (UINT64) (UINTN) VTdUnitInfo->QiDesc; - Reg64 |=3D VTdUnitInfo->QueueSize; + Reg64 |=3D QueueSize; MmioWrite64 (VtdUnitBaseAddress + R_IQA_REG, Reg64); =20 // @@ -164,7 +164,6 @@ DisableQueuedInvalidationInterface ( ) { UINT32 Reg32; - UINT16 QiDescLength; =20 if (VTdUnitInfo->EnableQueuedInvalidation !=3D 0) { Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG); @@ -176,10 +175,9 @@ DisableQueuedInvalidationInterface ( } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0); =20 if (VTdUnitInfo->QiDesc !=3D NULL) { - QiDescLength =3D 1 << (VTdUnitInfo->QueueSize + 8); - FreePages(VTdUnitInfo->QiDesc, EFI_SIZE_TO_PAGES(sizeof(QI_DESC) * Q= iDescLength)); + FreePages(VTdUnitInfo->QiDesc, EFI_SIZE_TO_PAGES (sizeof (QI_DESC) *= VTdUnitInfo->QiDescLength)); VTdUnitInfo->QiDesc =3D NULL; - VTdUnitInfo->QueueSize =3D 0; + VTdUnitInfo->QiDescLength =3D 0; } =20 VTdUnitInfo->EnableQueuedInvalidation =3D 0; @@ -239,10 +237,10 @@ SubmitQueuedInvalidationDescriptor ( return EFI_INVALID_PARAMETER; } =20 - QiDescLength =3D 1 << (VTdUnitInfo->QueueSize + 8); + QiDescLength =3D VTdUnitInfo->QiDescLength; BaseDesc =3D VTdUnitInfo->QiDesc; =20 - DEBUG((DEBUG_INFO, "[0x%x] Submit QI Descriptor [0x%08x, 0x%08x]\n", VTd= UnitInfo->VtdUnitBaseAddress, Desc->Low, Desc->High)); + DEBUG((DEBUG_INFO, "[0x%x] Submit QI Descriptor [0x%016lx, 0x%016lx]\n",= VTdUnitInfo->VtdUnitBaseAddress, Desc->Low, Desc->High)); =20 BaseDesc[VTdUnitInfo->QiFreeHead].Low =3D Desc->Low; BaseDesc[VTdUnitInfo->QiFreeHead].High =3D Desc->High; @@ -251,7 +249,6 @@ SubmitQueuedInvalidationDescriptor ( DEBUG((DEBUG_INFO,"QI Free Head=3D0x%x\n", VTdUnitInfo->QiFreeHead)); VTdUnitInfo->QiFreeHead =3D (VTdUnitInfo->QiFreeHead + 1) % QiDescLength; =20 - Reg64Iqh =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_IQH_REG); // // Update the HW tail register indicating the presence of new descriptor= s. // @@ -328,6 +325,7 @@ InvalidateIOTLB ( { UINT64 Reg64; VTD_ECAP_REG ECapReg; + VTD_CAP_REG CapReg; QI_DESC QiDesc; =20 if (VTdUnitInfo->EnableQueuedInvalidation =3D=3D 0) { @@ -353,8 +351,8 @@ InvalidateIOTLB ( // // Queued Invalidation // - ECapReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_ECA= P_REG); - QiDesc.Low =3D QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(ECapReg.Ui= nt64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(ECapReg.Uint64)) | QI_IOTLB_GRAN(1) | = QI_IOTLB_TYPE; + CapReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_CAP_= REG); + QiDesc.Low =3D QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(CapReg.Uin= t64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(CapReg.Uint64)) | QI_IOTLB_GRAN(1) | QI= _IOTLB_TYPE; QiDesc.High =3D QI_IOTLB_ADDR(0) | QI_IOTLB_IH(0) | QI_IOTLB_AM(0); =20 return SubmitQueuedInvalidationDescriptor(VTdUnitInfo, &QiDesc); @@ -364,7 +362,7 @@ InvalidateIOTLB ( } =20 /** - Enable DMAR translation inpre-mem phase. + Enable DMAR translation in pre-mem phase. =20 @param[in] VtdUnitBaseAddress The base address of the VTd engine. @param[in] RtaddrRegValue The value of RTADDR_REG. @@ -400,7 +398,7 @@ EnableDmarPreMem ( Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG); =20 // - // Write Buffer Flush before invalidation + // Write Buffer Flush // FlushWriteBuffer (VtdUnitBaseAddress); =20 diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmarPei.h b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/I= ntelVTdDmarPei.h index 7bed0a53..5ade9ec3 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.h +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.h @@ -21,7 +21,7 @@ typedef struct { VTD_ECAP_REG ECapReg; BOOLEAN Is5LevelPaging; UINT8 EnableQueuedInvalidation; - UINT16 QueueSize; + UINT16 QiDescLength; QI_DESC *QiDesc; UINT16 QiFreeHead; UINTN FixedSecondLevelPagingEntry; diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 61be2dcc..c7a56cf5 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -72,7 +72,7 @@ PerpareCacheInvalidationInterface ( UINT64 Reg64; UINT32 Reg32; =20 - if (mVtdUnitInformation[VtdIndex].VerReg.Bits.Major <=3D 6) { + if (mVtdUnitInformation[VtdIndex].VerReg.Bits.Major <=3D 5) { mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation =3D 0; DEBUG ((DEBUG_INFO, "Use Register-based Invalidation Interface for eng= ine [%d]\n", VtdIndex)); return EFI_SUCCESS; --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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