From nobody Sun May 5 10:41:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90776+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90776+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165631202325955.08246272405097; Sun, 26 Jun 2022 23:40:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HqJAYY1788612xlb2DT1SlPz; Sun, 26 Jun 2022 23:40:22 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.38620.1656312022043211959 for ; Sun, 26 Jun 2022 23:40:22 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D58D7175A; Sun, 26 Jun 2022 23:40:21 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.162.16.33]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 771FD3F5A1; Sun, 26 Jun 2022 23:40:20 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 1/5] Platform/Sgi: Add a new PCD for defining addressable bits per chip Date: Mon, 27 Jun 2022 12:10:07 +0530 Message-Id: <20220627064011.542820-2-pranav.madhu@arm.com> In-Reply-To: <20220627064011.542820-1-pranav.madhu@arm.com> References: <20220627064011.542820-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: GHDbboQdm9LgUQzsRNNax60rx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1656312022; bh=vMM4oGi3Y/1yie9yWLlB+7VPvbkZv87wA9A8tyOk1fA=; h=Cc:Date:From:Reply-To:Subject:To; b=On/SErI5ZWo5ExR4W+5h6kBw9qoBUMCeR7O26JAH7bpVDmt2Uzrq10dRA/cDtQ205Y7 D7KxdEBeh2WaQ4loRqE01MwNPdJAOhq1230gUbX3mwHkn695F1rUQyLL7Folov8Elks4n cje59Xyw6DmMC+jPitSjrNWaRZHjvhoTj1c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1656312025092100008 Content-Type: text/plain; charset="utf-8" From: Vijayenthiran Subramaniam Add a new PCD to define the maximum number of address bits used for addresses within a chip. The value of this PCD can be used to derive the maximum addressable memory region for each chip and to calculate the address space offset of a remote chip on multi-chip platform. In preparation of adding a multi-chip variant of the RD-N2 platform, use this new PCD to allow maximum address space of 64TB per chip for all RD-N2 platform variants. Signed-off-by: Vijayenthiran Subramaniam Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++++- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 5 ++++- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 5 ++++- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 ++- Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 ++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 3 ++- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++++--- 7 files changed, 22 insertions(+), 9 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiP= latform.dec index 8cd818a9bf64..b9be5c9060b6 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -90,5 +90,8 @@ gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025 gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026 =20 + # Address bus width + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|0x0|UINT64|0x00000027 + [Ppis] gNtFwConfigDtInfoPpiGuid =3D { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0= x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } } diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg= /SgiMemoryMap.dsc.inc index 5d4b6ae726f6..0cffff577c42 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -45,6 +45,9 @@ gArmTokenSpaceGuid.PcdPciMmio64Size|0x3000000000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x60000000 =20 + # Address bus width - 4TB address space + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|42 + # Timer & Watchdog interrupts gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|92 gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|91 diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPk= g/SgiMemoryMap2.dsc.inc index 1e9cd0982f5c..78ee48e354a8 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -45,6 +45,9 @@ gArmTokenSpaceGuid.PcdPciMmio64Size|0x4000000000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x1010000000 =20 + # Address bus width - 64TB address space + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46 + # Timer & Watchdog interrupts gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109 gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Plat= form/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf index 1999bc1553e9..c96d0e40d2cd 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020-2021, ARM Ltd. All rights reserved. +# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -66,6 +66,7 @@ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf index deaca3719ae4..61a2f3a2452b 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. +# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -66,6 +66,7 @@ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Plat= form/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index 22e247ea4fae..1ca7679b4191 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +41,7 @@ gArmPlatformTokenSpaceGuid.PcdCoreCount gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase =20 + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdDramBlock2Base gArmSgiTokenSpaceGuid.PcdDramBlock2Size gArmSgiTokenSpaceGuid.PcdGicSize diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPk= g/Include/SgiPlatform.h index dddb58832d73..04390d6dcc20 100644 --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2021, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -54,8 +54,9 @@ #define MULTI_CHIP_MODE_DISABLED 0x0 #define MULTI_CHIP_MODE_ENABLED 0x1 =20 -// Remote chip address offset (4TB per chip) -#define SGI_REMOTE_CHIP_MEM_OFFSET(n) ((1ULL << 42) * (n)) +// Remote chip address offset +#define SGI_REMOTE_CHIP_MEM_OFFSET(n) \ + ((1ULL << FixedPcdGet64 (PcdMaxAddressBitsPerChip)) * (n)) =20 // Base address of the DRAM1 block in a remote chip #define SYSTEM_MEMORY_BASE_REMOTE(ChipId) \ --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90776): https://edk2.groups.io/g/devel/message/90776 Mute This Topic: https://groups.io/mt/92015420/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:41:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90777+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90777+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1656312024553624.6592430081729; Sun, 26 Jun 2022 23:40:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id M70bYY1788612xURrOyiwgif; Sun, 26 Jun 2022 23:40:24 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.38621.1656312023658545455 for ; Sun, 26 Jun 2022 23:40:23 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 799021758; Sun, 26 Jun 2022 23:40:23 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.162.16.33]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1B2F83F5A1; Sun, 26 Jun 2022 23:40:21 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 2/5] Platform/Sgi: Add ProductId lookup values for RD-N2-Cfg2 Platform Date: Mon, 27 Jun 2022 12:10:08 +0530 Message-Id: <20220627064011.542820-3-pranav.madhu@arm.com> In-Reply-To: <20220627064011.542820-1-pranav.madhu@arm.com> References: <20220627064011.542820-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: hZ5JqmthNEH9zqyYkUBNVbz3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1656312024; bh=g5+VcjRuCNAIrMzWhCf+WrVM8Hmzr+DlSWB9RxwVBkA=; h=Cc:Date:From:Reply-To:Subject:To; b=eSuj1nYKZ8fUmGr6+0C77HDXyz60ugu/f3d9wE/s37QNJlwRvOvK9YnJJosTweTYasV luEJCKPj0ptow8auevr+1kkChhJK3LjhlSuhT0R7mPRhhO380FSug6AKr6gW8pXr2qWBV K7eG0I06HLzGbymRFXjfS3g4IWUMdtG9dPg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1656312025046100007 Content-Type: text/plain; charset="utf-8" From: Vijayenthiran Subramaniam The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform but with reduced core count, that is, each instance of the RD-N2 chip has four cores. This platform shares the same product and config ID as the RD-N2 platform. As a preparatory step towards adding support for RD-N2-Cfg2 Platfrom, add the Product ID lookup values for GetProductID API. Signed-off-by: Vijayenthiran Subramaniam Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 3 ++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPk= g/Include/SgiPlatform.h index 04390d6dcc20..e83853664c4c 100644 --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -83,7 +83,8 @@ typedef enum { RdV1, RdV1Mc, RdN2, - RdN2Cfg1 + RdN2Cfg1, + RdN2Cfg2, } ARM_RD_PRODUCT_ID; =20 // Arm ProductId look-up table diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platfo= rm/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c index a982e3d403fa..fa006320025b 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2021, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -73,6 +73,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = =3D { RD_N2_CFG1_CONF_ID, 0 }, + { + RdN2Cfg2, + RD_N2_PART_NUM, + RD_N2_CONF_ID, + 1 + }, }; =20 EFI_BOOT_MODE --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90777): https://edk2.groups.io/g/devel/message/90777 Mute This Topic: https://groups.io/mt/92015421/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:41:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90778+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90778+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1656312026639913.1777492652445; Sun, 26 Jun 2022 23:40:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id xmBzYY1788612xYLdmKLNlQJ; Sun, 26 Jun 2022 23:40:26 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.39276.1656312025515031344 for ; Sun, 26 Jun 2022 23:40:25 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56FAC1758; Sun, 26 Jun 2022 23:40:25 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.162.16.33]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B39123F5A1; Sun, 26 Jun 2022 23:40:23 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 3/5] Platform/Sgi: Add ACPI tables for RD-N2-Cfg2 platform Date: Mon, 27 Jun 2022 12:10:09 +0530 Message-Id: <20220627064011.542820-4-pranav.madhu@arm.com> In-Reply-To: <20220627064011.542820-1-pranav.madhu@arm.com> References: <20220627064011.542820-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 73KkJ05ijSeHTrjoydU1q2cTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1656312026; bh=YMHfK/fwkIsm1gUG7ASZ4ft36htfcS28sOx8UWvnatU=; h=Cc:Date:From:Reply-To:Subject:To; b=B2SSa9z7NODUnFVrkU3JqiIpQjbqg1PfKOKqrpzZsmaY1oJMmLmcpjwRAPDTDE20CRG iyN95M+/NEaGBsfPK4ho2nMGnd20vkkdafISXuYACvZjIEs3hff4iAmDdIIQf8YrvMEDH W0v1ePHaLUiA3hlVontIladImz129j0+SHk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1656312027116100013 Content-Type: text/plain; charset="utf-8" From: Vijayenthiran Subramaniam Add MADT, DSDT and SRAT ACPI tables that are specific for RD-N2-Cfg2 platform. The rest of the ACPI tables are reused from the shared ACPI tables in SgiPkg. Signed-off-by: Vijayenthiran Subramaniam Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf | 71 +++ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl | 532 ++++++++++++++= ++++++ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc | 145 ++++++ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc | 172 +++++++ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc | 117 +++++ 5 files changed, 1037 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf new file mode 100644 index 000000000000..2354f2dc65eb --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf @@ -0,0 +1,71 @@ +## @file +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D RdN2Cfg2AcpiTables + FILE_GUID =3D c712719a-0aaf-438c-9cdd-35ab4d60207d = # gArmSgiAcpiTablesGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dbg2.aslc + Fadt.aslc + Gtdt.aslc + RdN2Cfg2/Dsdt.asl + RdN2Cfg2/Madt.aslc + RdN2Cfg2/Pptt.aslc + RdN2Cfg2/Srat.aslc + Spcr.aslc + SsdtRos.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/SgiPkg/SgiPlatform.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmSgiTokenSpaceGuid.PcdChipCount + gArmSgiTokenSpaceGuid.PcdDramBlock2Base + gArmSgiTokenSpaceGuid.PcdDramBlock2Size + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip + gArmSgiTokenSpaceGuid.PcdOscLpiEnable + gArmSgiTokenSpaceGuid.PcdOscCppcEnable + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioNetSize + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl b/Platform/AR= M/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl new file mode 100644 index 000000000000..94d65fbbda2c --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl @@ -0,0 +1,532 @@ +/** @file + Differentiated System Description Table (DSDT) for RD-N2-Cfg2 platform + + This file describes the peripheral devices, system hardware features and= the + information about supported power events. + + Copyright (c) 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.11.1, Differentiated System Descrip= tion + Table (DSDT) +**/ + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", + EFI_ACPI_ARM_OEM_REVISION) { + + Scope (_SB) { + + /* _OSC: Operating System Capabilities */ + Method (_OSC, 4, Serialized) { + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + + /* Platform-wide Capabilities */ + If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) { + /* OSC rev 1 supported, for other version, return failure */ + If (LEqual (Arg1, One)) { + And (STS0, Not (OSC_STS_MASK), STS0) + + If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) { + /* OS initiated LPI not supported */ + And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) { + if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) { + And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + + If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) { + /* CPPC revision 1 and below not supported */ + And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) { + if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) { + And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0) + } + + Return (Arg3) + } + + Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */ + 0, // Version + 0, // Level Index + 2, // Count + Package () { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context lost Flags (no loss) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0xFFFFFFFF, // Address + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI1-Core" + }, + Package () { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context lost Flags (Core context los= t) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn) + 3, // Access Size + ) }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI3-Core" + }, + }) + + Device (CL00) { // Cluster 0 + Name (_HID, "ACPI0010") + Name (_UID, 0) + + Device (CP00) { // Neoverse N2 core 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 11= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (0) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL01) { // Cluster 1 + Name (_HID, "ACPI0010") + Name (_UID, 1) + + Device (CP01) { // Neoverse N2 core 1 + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 11= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (1) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL02) { // Cluster 2 + Name (_HID, "ACPI0010") + Name (_UID, 2) + + Device (CP02) { // Neoverse N2 core 2 + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 11= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (2) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL03) { // Cluster 3 + Name (_HID, "ACPI0010") + Name (_UID, 3) + + Device (CP03) { // Neoverse N2 core 3 + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 11= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (3) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL04) { // Cluster 4 + Name (_HID, "ACPI0010") + Name (_UID, 4) + + Device (CP04) { // Neoverse N2 core 4 + Name (_HID, "ACPI0007") + Name (_UID, 4) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x400006000500, 0x400006000504, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (4) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL05) { // Cluster 5 + Name (_HID, "ACPI0010") + Name (_UID, 5) + + Device (CP05) { // Neoverse N2 core 5 + Name (_HID, "ACPI0007") + Name (_UID, 5) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x400006000518, 0x40000600051C, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (5) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL06) { // Cluster 6 + Name (_HID, "ACPI0010") + Name (_UID, 6) + + Device (CP06) { // Neoverse N2 core 6 + Name (_HID, "ACPI0007") + Name (_UID, 6) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x400006000530, 0x400006000534, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (6) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL07) { // Cluster 7 + Name (_HID, "ACPI0010") + Name (_UID, 7) + + Device (CP07) { // Neoverse N2 core 7 + Name (_HID, "ACPI0007") + Name (_UID, 7) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x400006000548, 0x40000600054C, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (7) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL08) { // Cluster 8 + Name (_HID, "ACPI0010") + Name (_UID, 8) + + Device (CP08) { // Neoverse N2 core 8 + Name (_HID, "ACPI0007") + Name (_UID, 8) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x800006000500, 0x800006000504, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (8) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL09) { // Cluster 9 + Name (_HID, "ACPI0010") + Name (_UID, 9) + + Device (CP09) { // Neoverse N2 core 9 + Name (_HID, "ACPI0007") + Name (_UID, 9) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x800006000518, 0x80000600051C, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (9) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL10) { // Cluster 10 + Name (_HID, "ACPI0010") + Name (_UID, 10) + + Device (CP10) { // Neoverse N2 core 10 + Name (_HID, "ACPI0007") + Name (_UID, 10) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x800006000530, 0x800006000534, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (10) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL11) { // Cluster 11 + Name (_HID, "ACPI0010") + Name (_UID, 11) + + Device (CP11) { // Neoverse N2 core 11 + Name (_HID, "ACPI0007") + Name (_UID, 11) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x800006000548, 0x80000600054C, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (11) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + + } + } + + Device (CL12) { // Cluster 12 + Name (_HID, "ACPI0010") + Name (_UID, 12) + + Device (CP12) { // Neoverse N2 core 12 + Name (_HID, "ACPI0007") + Name (_UID, 12) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0xC00006000500, 0xC00006000504, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (12) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + } + } + + Device (CL13) { // Cluster 13 + Name (_HID, "ACPI0010") + Name (_UID, 13) + + Device (CP13) { // Neoverse N2 core 13 + Name (_HID, "ACPI0007") + Name (_UID, 13) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0xC00006000518, 0xC0000600051C, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (13) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + } + } + + Device (CL14) { // Cluster 14 + Name (_HID, "ACPI0010") + Name (_UID, 14) + + Device (CP14) { // Neoverse N2 core 14 + Name (_HID, "ACPI0007") + Name (_UID, 14) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0xC00006000530, 0xC00006000534, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (14) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + } + } + + Device (CL15) { // Cluster 15 + Name (_HID, "ACPI0010") + Name (_UID, 15) + + Device (CP15) { // Neoverse N2 core 15 + Name (_HID, "ACPI0007") + Name (_UID, 15) + Name (_STA, 0xF) + + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0xC00006000548, 0xC0000600054C, 20, 160, 160,= 115, + 115, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (15) + }) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } + } + } + + } // Scope(_SB) +} diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc new file mode 100644 index 000000000000..044d8d9b690b --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc @@ -0,0 +1,145 @@ +/** @file + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the RD-N2-Cf= g2 + platform is included in this table. + + Copyright (c) 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table +**/ + +#include +#include +#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ + FixedPcdGet32 (PcdCoreCount)) +#define CHIP_CNT (FixedPcdGet32 (PcdChipCount)) + +// Multiple APIC Description Table +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT * CHIP_CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[C= HIP_CNT]; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // MADT specific fields + 0, // LocalApicAddress + 0 // Flags + }, + { + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase, + // Efficiency, + // SpeOverflowInterrupt) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see chapter 5.2.12.14 GICC Structure of ACPI v6.4). + + // Chip 0 + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + + // Chip 1 + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0 + 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1 + 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2 + 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3 + 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + + // Chip 2 + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0 + 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1 + 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2 + 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3 + 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + + // Chip 3 + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0 + 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1 + 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2 + 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3 + 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + }, + // GIC Distributor Entry + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + 0, 3), + { + // GIC Redistributor + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + SGI_REMOTE_CHIP_MEM_OFFSET(0), SIZE_16MB), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_16MB), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + SGI_REMOTE_CHIP_MEM_OFFSET(2), SIZE_16MB), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + SGI_REMOTE_CHIP_MEM_OFFSET(3), SIZE_16MB) + }, + // GIC ITS + { + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000), + EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000), + }, +}; + +// +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Madt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc new file mode 100644 index 000000000000..3f37243a9d8a --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc @@ -0,0 +1,172 @@ +/** @file + Processor Properties Topology Table (PPTT) for RD-N2-Cfg2 platform + + This file describes the topological structure of the processor block on = the + RD-N2-Cfg2 platform in the form as defined by ACPI PPTT table. The RD-N2= -Cfg2 + platform is composed of four identical chips connected over cache cohere= nt + interconnect. Each of the chip on the platform includes four single thre= ad + CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction c= ache + and 1MB L2 cache. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +#define CHIP_COUNT FixedPcdGet32 (PcdChipCount) + +/** Define helper macro for populating processor core information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. + @param [in] CpuId CPU instance number. +**/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[PackageId].Cluster[ClusterId]), /* Parent */ = \ + ((PackageId << 2) | ClusterId), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) = \ + /* Cache id */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) = \ + /* Cache id */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) = \ + /* Cache id */ = \ + ), = \ + } + +/** Define helper macro for populating processor container information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. +**/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[PackageId]), /* Parent */ = \ + ((PackageId << 2) | ClusterId), /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) = \ + } = \ + } + +/** Define helper macro for populating SoC package information. + + @param [in] PackageId Package instance number. +**/ +#define PPTT_PACKAGE_INIT(PackageId) = \ + { = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), /* Length */ = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ + 0, /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + { = \ + PPTT_CLUSTER_INIT (PackageId, 0), = \ + PPTT_CLUSTER_INIT (PackageId, 1), = \ + PPTT_CLUSTER_INIT (PackageId, 2), = \ + PPTT_CLUSTER_INIT (PackageId, 3), = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_PACKAGE Package[CHIP_CO= UNT]; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + PPTT_PACKAGE_INIT (0), + PPTT_PACKAGE_INIT (1), + PPTT_PACKAGE_INIT (2), + PPTT_PACKAGE_INIT (3) + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc new file mode 100644 index 000000000000..6bdad7004fb6 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc @@ -0,0 +1,117 @@ +/** @file + Static Resource Affinity Table (SRAT) + + SRAT table provides information that allows OSPM to associate devices su= ch as + processors with system locality / proximity domains and clock domains. T= he + memory attached to the two chips on this platform and its affinity to the + chips on its respective chips is listed in this table. + + Copyright (c) 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table +**/ + +#include +#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +// +// Static Resource Affinity Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[8]; + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16]; +} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; + +#pragma pack () + +EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D { + // Header + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE, + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION + ), + 0x00000001, + EFI_ACPI_RESERVED_QWORD + }, + // Memory Affinity + { + // Chip 0 (2GB and 6GB) + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( + 0x0, FixedPcdGet64 (PcdSystemMemoryBase), + FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( + 0x0, FixedPcdGet64 (PcdDramBlock2Base), + FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), + + // Chip 1 (2GB and 6GB) + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( + 0x1, SYSTEM_MEMORY_BASE_REMOTE(1), + FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( + 0x1, DRAM_BLOCK2_BASE_REMOTE(1), + FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), + + // Chip 2 (2GB and 6GB) + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( + 0x2, SYSTEM_MEMORY_BASE_REMOTE(2), + FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( + 0x2, DRAM_BLOCK2_BASE_REMOTE(2), + FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), + + // Chip 3 (2GB and 6GB) + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT( + 0x3, SYSTEM_MEMORY_BASE_REMOTE(3), + FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT( + 0x3, DRAM_BLOCK2_BASE_REMOTE(3), + FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), + }, + // Processor Affinity + { + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x0, 0x00000000, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x0, 0x00000001, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x0, 0x00000002, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x0, 0x00000003, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x1, 0x00000004, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x1, 0x00000005, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x1, 0x00000006, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x1, 0x00000007, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x2, 0x00000008, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x2, 0x00000009, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x2, 0x0000000A, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x2, 0x0000000B, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x3, 0x0000000C, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x3, 0x0000000D, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x3, 0x0000000E, 0x00000001, 0x00000000), + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( + 0x3, 0x0000000F, 0x00000001, 0x00000000), + }, +}; + +VOID* CONST ReferenceAcpiTable =3D &Srat; --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90778): https://edk2.groups.io/g/devel/message/90778 Mute This Topic: https://groups.io/mt/92015423/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:41:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90779+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90779+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1656312028203968.5041582527009; Sun, 26 Jun 2022 23:40:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id I21OYY1788612xh4Z6QwMBAw; Sun, 26 Jun 2022 23:40:27 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.39277.1656312027161983559 for ; Sun, 26 Jun 2022 23:40:27 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F00D9175A; Sun, 26 Jun 2022 23:40:26 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.162.16.33]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 915373F5A1; Sun, 26 Jun 2022 23:40:25 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 4/5] Platform/Sgi: Add support for RD-N2-Cfg2 Platform Date: Mon, 27 Jun 2022 12:10:10 +0530 Message-Id: <20220627064011.542820-5-pranav.madhu@arm.com> In-Reply-To: <20220627064011.542820-1-pranav.madhu@arm.com> References: <20220627064011.542820-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 9VZCc9GadSN8hZnaqSdBgtLox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1656312027; bh=L4Aspd8AZKe2IJ6mzKzGYi/TMWCJHiYQnOP9EE/T/+8=; h=Cc:Date:From:Reply-To:Subject:To; b=ZfFaVzjcisdiRPpwhIDGCnhzuJVUx2KLMiBEMMy3/qa5wC0CfBqvPc4XbXfAagoCchk vYyLJqFhO8diUfl1ZSW+exowBuFdR15UWyLnUW6hpn4s/jeaC19UMFIKtoIniCtnFQarM ANYKckLmLsGHm/7G2sm8Ux75ER6rOjeb4HQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1656312029068100017 Content-Type: text/plain; charset="utf-8" From: Vijayenthiran Subramaniam The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform. Each chip has reduced core count of four Neoverse N2 CPUs when compared to the single-chip RD-N2 platform. Enable support for the RD-N2-Cfg2 platform. Signed-off-by: Vijayenthiran Subramaniam Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc | 58 ++++++++++++++++++++ Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc | 10 ++++ 2 files changed, 68 insertions(+) diff --git a/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc b/Platform/ARM/SgiPk= g/RdN2Cfg2/RdN2Cfg2.dsc new file mode 100644 index 000000000000..0a7991e77b78 --- /dev/null +++ b/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc @@ -0,0 +1,58 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D RdN2Cfg2 + PLATFORM_GUID =3D fd272907-b48e-4148-b6e5-fe762f20653d + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/ARM/SgiPkg/SgiPlatform.fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2= .fdf.inc + BUILD_NUMBER =3D 1 + +# include common definitions from SgiPlatform.dsc +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc + +# include common/basic libraries from MdePkg. +!include MdePkg/MdeLibs.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFixedAtBuild.common] + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x301C0000 + gArmSgiTokenSpaceGuid.PcdGicSize|0x200000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmPlatformTokenSpaceGuid.PcdClusterCount|4 + + # Number of chips in the multi-chip package + gArmSgiTokenSpaceGuid.PcdChipCount|4 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### + +[Components.common] + Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf diff --git a/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc b/Platform/ARM/S= giPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc new file mode 100644 index 000000000000..89df6d905811 --- /dev/null +++ b/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc @@ -0,0 +1,10 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-platform additional content of the DXE phase firmware volume + + # ACPI support + INF RuleOverride=3DACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2Acpi= Tables.inf --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90779): https://edk2.groups.io/g/devel/message/90779 Mute This Topic: https://groups.io/mt/92015425/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:41:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90780+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90780+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1656312029703981.9515807228054; Sun, 26 Jun 2022 23:40:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id R8VjYY1788612x0kVfVsJADG; Sun, 26 Jun 2022 23:40:29 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.38701.1656312028743144778 for ; Sun, 26 Jun 2022 23:40:28 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 952F71758; Sun, 26 Jun 2022 23:40:28 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.162.16.33]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 35FCB3F5A1; Sun, 26 Jun 2022 23:40:26 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 5/5] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg2 Date: Mon, 27 Jun 2022 12:10:11 +0530 Message-Id: <20220627064011.542820-6-pranav.madhu@arm.com> In-Reply-To: <20220627064011.542820-1-pranav.madhu@arm.com> References: <20220627064011.542820-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: rhDdrF2K6KEjTJZV9SEKZRcbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1656312029; bh=G/+V7Mt+J/9hLLBiD21t+KDnC+K2yYo/yLg1lt29mx0=; h=Cc:Date:From:Reply-To:Subject:To; b=I8db9h6SVcZZNSAtvWrxLWE66VEYr2wqk3dMkXDzBdDNX241Q8mhy7ot7RWObTb3yfJ 8Y1gH1Ziyic3uKhmTmzMrzN8MnWkpDdPz1UYafAeFjYkGVfPWCqwBeLVwCHqztXZKxvpj VRAbOjGr/8eZ6rdaVepu+RBh3xKMPPmsCwM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1656312031083100019 Content-Type: text/plain; charset="utf-8" Extend the SMBIOS support for RD-N2-Cfg2 platform which is a quad-chip variant of the RD-N2 platform. Most the SMBIOS information is shared with the RD-N2 platform except for the number of the CPUs supported on the RD-N2-Cfg2 platform. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c = | 7 +++++-- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c = | 15 ++++++++++++--- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c = | 3 ++- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInfor= mation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInforma= tion.c index 17361f63359b..b7e2238fb39c 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c @@ -5,7 +5,7 @@ Reference Design platforms. Type 1 table defines attributes of the overall system such as manufacturer, product name, UUID etc. =20 - Copyright (c) 2021, ARM Limited. All rights reserved. + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: @@ -32,7 +32,8 @@ "RdV1\0" \ "RdV1Mc\0" \ "RdN2\0" \ - "RdN2Cfg1\0" + "RdN2Cfg1\0" \ + "RdN2Cfg2\0" =20 typedef enum { ManufacturerName =3D 1, @@ -68,6 +69,8 @@ STATIC GUID mSmbiosUid[] =3D { {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, = 0x49}}, /* Rd-N2-Cfg1 */ {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, = 0xda}}, + /* Rd-N2-Cfg2 */ + {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, = 0x60}}, }; =20 /* System information */ diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorIn= formation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorI= nformation.c index b554ee6dea58..b59172cf1cb9 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformati= on.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformati= on.c @@ -6,7 +6,7 @@ family, processor id, maximum operating frequency, and other information related to the processor. =20 - Copyright (c) 2021, ARM Limited. All rights reserved. + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: @@ -27,7 +27,7 @@ #define SOCKET_TYPE_BASE 3 #define SOCKET_TYPE_NUM 1 #define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM) -#define PROCESSOR_VERSION_NUM 9 +#define PROCESSOR_VERSION_NUM 10 #define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE + PROCESSOR_VERSIO= N_NUM) #define TYPE4_STRINGS \ "0x000\0" /* Part Number */ \ @@ -42,6 +42,7 @@ "Neoverse-V1\0" \ "Neoverse-N2\0" \ "Neoverse-N2\0" \ + "Neoverse-N2\0" \ "000-0\0" /* Serial number */ \ "783-3\0" \ "786-1\0" \ @@ -50,7 +51,8 @@ "78A-1\0" \ "78A-2\0" \ "7B7-1\0" \ - "7B6-1\0" + "7B6-1\0" \ + "7B7-1\0" =20 typedef enum { PartNumber =3D 1, @@ -188,6 +190,13 @@ InstallType4ProcessorInformation ( mArmRdSmbiosType4.Base.EnabledCoreCount =3D CoreCount * FixedPcdGet32 = (PcdChipCount); mArmRdSmbiosType4.Base.ThreadCount =3D CoreCount * FixedPcdGet32 (PcdC= hipCount); break; + case RdN2Cfg2: + mArmRdSmbiosType4.Base.CoreCount =3D CoreCount * FixedPcdGet32 (PcdChi= pCount); + mArmRdSmbiosType4.Base.EnabledCoreCount =3D CoreCount * FixedPcdGet32 = (PcdChipCount); + mArmRdSmbiosType4.Base.ThreadCount =3D CoreCount * FixedPcdGet32 (PcdC= hipCount); + mArmRdSmbiosType4.Base.MaxSpeed =3D 3200; // Frequency in MHz + mArmRdSmbiosType4.Base.CurrentSpeed =3D 3200; // Frequency in MHz + break; case RdE1Edge: mArmRdSmbiosType4.Base.CoreCount =3D CoreCount / NEOVERSE_E1_THREADS_P= ER_CORE; mArmRdSmbiosType4.Base.EnabledCoreCount =3D CoreCount / NEOVERSE_E1_TH= READS_PER_CORE; diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInform= ation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformati= on.c index 02cfa6334deb..b71ce721e2e8 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c @@ -6,7 +6,7 @@ implemented, cache configuration, ways of associativity and other information related to cache memory installed. =20 - Copyright (c) 2021, ARM Limited. All rights reserved. + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: @@ -298,6 +298,7 @@ InstallType7CacheInformation ( mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; break; case RdN2: + case RdN2Cfg2: /* L1 instruction cache */ mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90780): https://edk2.groups.io/g/devel/message/90780 Mute This Topic: https://groups.io/mt/92015426/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-