From nobody Sat May 4 00:27:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90675+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90675+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1655897585; cv=none; d=zohomail.com; s=zohoarc; b=GyLqTe556ex2anMKr155QHh0nvvbT5CqAigIzBh5K8YExdh/bhfAzZVUXXZLaPusqvEoc20Nbp+F1VqoO8H1q75OAqpcPys4T+mF8uSgBUkCmAc1KDS9U14AWlVpAlL+mA5x+TaRCHUS8k4jnQ17aYHUHwlctZtQMdR9bZ4E2O4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1655897585; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=a5ed92/zDY/4ig8O8QLFK2tfPd7RlDqJZjuKPF1tSso=; b=oK8pjgxJyYO2r84i0SlUb6JAYKTcXwWEwdyyck8w3D8i660T4NkfhMjRtvSVS6IqEBIQ17VaJEk8weiFoCo3xVMyMzwwP22+KUsxVUT5jIXF270tJcQynqnl60h3B4cIa75HF1YoKizCwcIApX8QKhzwRuhfysIbUJx+dH7oGbg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90675+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1655897585128508.05171099453526; Wed, 22 Jun 2022 04:33:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id llpfYY1788612xozejmcqldT; Wed, 22 Jun 2022 04:33:04 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.6002.1655897583775077070 for ; Wed, 22 Jun 2022 04:33:03 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10385"; a="260823034" X-IronPort-AV: E=Sophos;i="5.92,212,1650956400"; d="scan'208";a="260823034" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2022 04:33:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,212,1650956400"; d="scan'208";a="562941775" X-Received: from jliu28x-desk3.gar.corp.intel.com ([10.5.215.163]) by orsmga006.jf.intel.com with ESMTP; 22 Jun 2022 04:33:01 -0700 From: ian.chiu@intel.com To: devel@edk2.groups.io Cc: Ian Chiu , Jenny Huang , More Shih , Hao A Wu , Ray Ni Subject: [edk2-devel] [PATCH v3] MdeModulePkg/XhciDxe: Add access xHCI Extended Capabilities Pointer Date: Wed, 22 Jun 2022 19:32:53 +0800 Message-Id: <20220622113253.1459-1-ian.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ian.chiu@intel.com X-Gm-Message-State: p36k0mR7fhSnHSz5umo6Gxfnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1655897584; bh=S7Qe2oNGtkuajv65icHSiqC6iUSTJnsPhj8Vdv4X8u4=; h=Cc:Date:From:Reply-To:Subject:To; b=FxfGdn74cKwfQiXAIfxycPTV9qI4G8Pq4NmrPacZ7vFI1XxZzU1Ojtgw7kYIgpdQZaX MfDVgeJ8KKcdL39odvrzjo6BraPBD1YUCMfcO2bNkW198xUTP7nvZxo657L7nXgT17irO wJOJ+6c5q8JyXsPhuIcUwUXJaxM7LgnY49w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1655897586115100001 Content-Type: text/plain; charset="utf-8" From: Ian Chiu Add support process Port Speed field value of PORTSC according to Supported Protocol Capability (define in xHCI spec 1.1) REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3914 The value of Port Speed field in PORTSC bit[10:13] (xHCI spec 1.1 section 5.4.8) should be change to use this value to query thru Protocol Speed ID (PSI) (xHCI spec 1.1 section 7.2.1) in xHCI Supported Protocol Capability and return the value according the Protocol Speed ID (PSIV) Dword. With this mechanism may able to detect more kind of Protocol Speed in USB3 and also compatiable with three kind of speed of USB2. Cc: Jenny Huang Cc: More Shih Cc: Hao A Wu Cc: Ray Ni Signed-off-by: Ian Chiu Reviewed-by: Hao A Wu --- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 41 +++-- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h | 2 + MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 178 ++++++++++++++++++++ MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 92 +++++++++- 4 files changed, 296 insertions(+), 17 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/Xhc= iDxe/Xhci.c index 381d7a9536..446f88bd60 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -398,25 +398,32 @@ XhcGetRootHubPortStatus ( State =3D XhcReadOpReg (Xhc, Offset); =20 // - // According to XHCI 1.1 spec November 2017, - // bit 10~13 of the root port status register identifies the speed of th= e attached device. + // According to XHCI 1.1 spec November 2019, + // Section 7.2 xHCI Support Protocol Capability // - switch ((State & XHC_PORTSC_PS) >> 10) { - case 2: - PortStatus->PortStatus |=3D USB_PORT_STAT_LOW_SPEED; - break; + PortStatus->PortStatus =3D XhcCheckUsbPortSpeedUsedPsic (Xhc, ((State & = XHC_PORTSC_PS) >> 10)); + if (PortStatus->PortStatus =3D=3D 0) { + // + // According to XHCI 1.1 spec November 2017, + // bit 10~13 of the root port status register identifies the speed of = the attached device. + // + switch ((State & XHC_PORTSC_PS) >> 10) { + case 2: + PortStatus->PortStatus |=3D USB_PORT_STAT_LOW_SPEED; + break; =20 - case 3: - PortStatus->PortStatus |=3D USB_PORT_STAT_HIGH_SPEED; - break; + case 3: + PortStatus->PortStatus |=3D USB_PORT_STAT_HIGH_SPEED; + break; =20 - case 4: - case 5: - PortStatus->PortStatus |=3D USB_PORT_STAT_SUPER_SPEED; - break; + case 4: + case 5: + PortStatus->PortStatus |=3D USB_PORT_STAT_SUPER_SPEED; + break; =20 - default: - break; + default: + break; + } } =20 // @@ -1826,6 +1833,8 @@ XhcCreateUsbHc ( Xhc->ExtCapRegBase =3D ExtCapReg << 2; Xhc->UsbLegSupOffset =3D XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY= ); Xhc->DebugCapSupOffset =3D XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG); + Xhc->Usb2SupOffset =3D XhcGetSupportedProtocolCapabilityAddr (Xhc, X= HC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2); + Xhc->Usb3SupOffset =3D XhcGetSupportedProtocolCapabilityAddr (Xhc, X= HC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3); =20 DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->Ca= pLength)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams= 1)); @@ -1835,6 +1844,8 @@ XhcCreateUsbHc ( DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbL= egSupOffset)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->De= bugCapSupOffset)); + DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb2SupOffset 0x%x\n", Xhc->Usb2Su= pOffset)); + DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb3SupOffset 0x%x\n", Xhc->Usb3Su= pOffset)); =20 // // Create AsyncRequest Polling Timer diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/Xhc= iDxe/Xhci.h index 5054d796b1..ca223bd20c 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h @@ -227,6 +227,8 @@ struct _USB_XHCI_INSTANCE { UINT32 ExtCapRegBase; UINT32 UsbLegSupOffset; UINT32 DebugCapSupOffset; + UINT32 Usb2SupOffset; + UINT32 Usb3SupOffset; UINT64 *DCBAA; VOID *DCBAAMap; UINT32 MaxSlotsEn; diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/= XhciDxe/XhciReg.c index 80be3311d4..e11db59871 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -575,6 +575,184 @@ XhcGetCapabilityAddr ( return 0xFFFFFFFF; } =20 +/** + Calculate the offset of the xHCI Supported Protocol Capability. + + @param Xhc The XHCI Instance. + @param MajorVersion The USB Major Version in xHCI Support Protocol Cap= ability Field + + @return The offset of xHCI Supported Protocol capability register. + +**/ +UINT32 +XhcGetSupportedProtocolCapabilityAddr ( + IN USB_XHCI_INSTANCE *Xhc, + IN UINT8 MajorVersion + ) +{ + UINT32 ExtCapOffset; + UINT8 NextExtCapReg; + UINT32 Data; + UINT32 NameString; + XHC_SUPPORTED_PROTOCOL_DW0 UsbSupportDw0; + + if (Xhc =3D=3D NULL) { + return 0; + } + + ExtCapOffset =3D 0; + + do { + // + // Check if the extended capability register's capability id is USB Le= gacy Support. + // + Data =3D XhcReadExtCapReg (Xhc, ExtCapOffset); + UsbSupportDw0.Dword =3D Data; + if ((Data & 0xFF) =3D=3D XHC_CAP_USB_SUPPORTED_PROTOCOL) { + if (UsbSupportDw0.Data.RevMajor =3D=3D MajorVersion) { + NameString =3D XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED= _PROTOCOL_NAME_STRING_OFFSET); + if (NameString =3D=3D XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE) { + // + // Ensure Name String field is xHCI supported protocols in xHCI = Supported Protocol Capability Offset 04h + // + return ExtCapOffset; + } + } + } + + // + // If not, then traverse all of the ext capability registers till find= ing out it. + // + NextExtCapReg =3D (UINT8)((Data >> 8) & 0xFF); + ExtCapOffset +=3D (NextExtCapReg << 2); + } while (NextExtCapReg !=3D 0); + + return 0xFFFFFFFF; +} + +/** + Find PortSpeed value match Protocol Speed ID Value (PSIV). + + @param Xhc The XHCI Instance. + @param ExtCapOffset The USB Major Version in xHCI Support Protocol Ca= pability Field + @param PortSpeed The Port Speed Field in USB PortSc register + + @return The Protocol Speed ID (PSI) from xHCI Supported Protocol capabil= ity register. + +**/ +UINT32 +XhciPsivGetPsid ( + IN USB_XHCI_INSTANCE *Xhc, + IN UINT32 ExtCapOffset, + IN UINT8 PortSpeed + ) +{ + XHC_SUPPORTED_PROTOCOL_DW2 PortId; + XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Reg; + UINT32 Count; + + if ((Xhc =3D=3D NULL) || (ExtCapOffset =3D=3D 0xFFFFFFFF)) { + return 0; + } + + // + // According to XHCI 1.1 spec November 2019, + // Section 7.2 xHCI Supported Protocol Capability + // 1. Get the PSIC(Protocol Speed ID Count) value. + // 2. The PSID register boundary should be Base address + PSIC * 0x04 + // + PortId.Dword =3D XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PRO= TOCOL_DW2_OFFSET); + + for (Count =3D 0; Count < PortId.Data.Psic; Count++) { + Reg.Dword =3D XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROT= OCOL_PSI_OFFSET + (Count << 2)); + if (Reg.Data.Psiv =3D=3D PortSpeed) { + return Reg.Dword; + } + } + + return 0; +} + +/** + Find PortSpeed value match case in XHCI Supported Protocol Capability + + @param Xhc The XHCI Instance. + @param PortSpeed The Port Speed Field in USB PortSc register + + @return The USB Port Speed. + +**/ +UINT16 +XhcCheckUsbPortSpeedUsedPsic ( + IN USB_XHCI_INSTANCE *Xhc, + IN UINT8 PortSpeed + ) +{ + XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID SpField; + UINT16 UsbSpeedIdMap; + + if (Xhc =3D=3D NULL) { + return 0; + } + + SpField.Dword =3D 0; + UsbSpeedIdMap =3D 0; + + // + // Check xHCI Supported Protocol Capability which Revision Major number = is 03h + // and find the PSIV field to match PortSpeed. + // + if (Xhc->Usb3SupOffset !=3D 0xFFFFFFFF) { + SpField.Dword =3D XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed); + if (SpField.Dword !=3D 0) { + // + // Found the corresponding PORTSC value in PSIV field of USB3 offset. + // + UsbSpeedIdMap =3D USB_PORT_STAT_SUPER_SPEED; + } + } + + // + // Check xHCI Supported Protocol Capability which Revision Major number = is 02h + // and find the PSIV field to match PortSpeed. + // + if ((UsbSpeedIdMap =3D=3D 0) && (Xhc->Usb2SupOffset !=3D 0xFFFFFFFF)) { + SpField.Dword =3D XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed); + if (SpField.Dword !=3D 0) { + // + // Found the corresponding PORTSC value in PSIV field of USB2 offset. + // + if (SpField.Data.Psie =3D=3D 2) { + // + // According to XHCI 1.1 spec November 2019, + // Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field defin= ition, + // PSIE value shall be applied to Protocol Speed ID Mantissa when = calculating, value 2 shall represent bit rate is Mb/s + // + if (SpField.Data.Psim =3D=3D XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEE= D_PSIM) { + // + // PSIM shows as default High-speed protocol, apply to High-spee= d mapping + // + UsbSpeedIdMap =3D USB_PORT_STAT_HIGH_SPEED; + } + } else if (SpField.Data.Psie =3D=3D 1) { + // + // According to XHCI 1.1 spec November 2019, + // Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field defin= ition, + // PSIE value shall be applied to Protocol Speed ID Mantissa when = calculating, value 1 shall represent bit rate is Kb/s + // + if (SpField.Data.Psim =3D=3D XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED= _PSIM) { + // + // PSIM shows as default Low-speed protocol, apply to Low-speed = mapping + // + UsbSpeedIdMap =3D USB_PORT_STAT_LOW_SPEED; + } + } + } + } + + return UsbSpeedIdMap; +} + /** Whether the XHCI host controller is halted. =20 diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/= XhciDxe/XhciReg.h index 4950eed272..94b53c8335 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -25,8 +25,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define USB_HUB_CLASS_CODE 0x09 #define USB_HUB_SUBCLASS_CODE 0x00 =20 -#define XHC_CAP_USB_LEGACY 0x01 -#define XHC_CAP_USB_DEBUG 0x0A +#define XHC_CAP_USB_LEGACY 0x01 +#define XHC_CAP_USB_DEBUG 0x0A +#define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02 =20 // =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D// // XHCI register offset // @@ -74,6 +75,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore =20 +// +// xHCI Supported Protocol Capability +// +#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02 +#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03 +#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04 +#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355 +#define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08 +#define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10 +#define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480 +#define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500 + #pragma pack (1) typedef struct { UINT8 MaxSlots; // Number of Device Slots @@ -130,6 +143,52 @@ typedef union { HCCPARAMS Data; } XHC_HCCPARAMS; =20 +// +// xHCI Supported Protocol Cabability +// +typedef struct { + UINT8 CapId; + UINT8 NextExtCapReg; + UINT8 RevMinor; + UINT8 RevMajor; +} SUPPORTED_PROTOCOL_DW0; + +typedef union { + UINT32 Dword; + SUPPORTED_PROTOCOL_DW0 Data; +} XHC_SUPPORTED_PROTOCOL_DW0; + +typedef struct { + UINT32 NameString; +} XHC_SUPPORTED_PROTOCOL_DW1; + +typedef struct { + UINT8 CompPortOffset; + UINT8 CompPortCount; + UINT16 ProtocolDef : 12; + UINT16 Psic : 4; +} SUPPORTED_PROTOCOL_DW2; + +typedef union { + UINT32 Dword; + SUPPORTED_PROTOCOL_DW2 Data; +} XHC_SUPPORTED_PROTOCOL_DW2; + +typedef struct { + UINT16 Psiv : 4; + UINT16 Psie : 2; + UINT16 Plt : 2; + UINT16 Pfd : 1; + UINT16 RsvdP : 5; + UINT16 Lp : 2; + UINT16 Psim; +} SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID; + +typedef union { + UINT32 Dword; + SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data; +} XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID; + #pragma pack () =20 // @@ -546,4 +605,33 @@ XhcGetCapabilityAddr ( IN UINT8 CapId ); =20 +/** + Calculate the offset of the xHCI Supported Protocol Capability. + + @param Xhc The XHCI Instance. + @param MajorVersion The USB Major Version in xHCI Support Protocol Cap= ability Field + + @return The offset of xHCI Supported Protocol capability register. + +**/ +UINT32 +XhcGetSupportedProtocolCapabilityAddr ( + IN USB_XHCI_INSTANCE *Xhc, + IN UINT8 MajorVersion + ); + +/** + Find SpeedField value match with Port Speed ID value. + + @param Xhc The XHCI Instance. + @param Speed The Port Speed filed in USB PortSc register + + @return The USB Port Speed. + +**/ +UINT16 +XhcCheckUsbPortSpeedUsedPsic ( + IN USB_XHCI_INSTANCE *Xhc, + IN UINT8 Speed + ); #endif --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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