From nobody Sun Feb 8 23:37:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90268+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90268+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1654557441; cv=none; d=zohomail.com; s=zohoarc; b=QXpNVvrfCtZK7y0KkGVO7k7VPClYrLA2pu73ZDFyhbXkL+j8FvYbXedGW5gAUYRIvdhEjgl+j/wn6NizF8dS9y89lQZQ0kNaf8txh5/cy1V2ZFKfhSNw2d968dKXUA9YltrG3KM+sxB0CpJl05Jwpa2aPkD7kUsMaE33zp4KXoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654557441; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Pn/WCIGqIQfTQgv4UQo054zPlHb+kVAzPgJJS1PHWEo=; b=Z/gCznAljpEKxp17qRTEBwBQc2G287sCGeXdVocvNy5MyHCeqQ3Rl5jdHgRtajV3C+oHBKRKVITiEkV34ataZcyLpuXUbliWUqOC7neV52Rn6sveP113sVDgncwf42w5K5sh2dxN5dYokcu4T3vvgai4FF7F1hj4zsPjCVZnxOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90268+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1654557441946872.6818496215884; Mon, 6 Jun 2022 16:17:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id TkygYY1788612xQrVySL5EJf; Mon, 06 Jun 2022 16:17:21 -0700 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.5360.1654557439971488024 for ; Mon, 06 Jun 2022 16:17:20 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="275474994" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="275474994" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="608952575" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 16:16:43 -0700 Message-Id: <20220606231645.3813-3-nathaniel.l.desimone@intel.com> In-Reply-To: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> References: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: fp6hF1fjH4RYiPas0v751U65x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1654557441; bh=qgRpW/twzaNboH+3TXOp2Wc8XtC4RiqmTu+X0TMft68=; h=Cc:Date:From:Reply-To:Subject:To; b=JDZjIcMd2QkiuKzUEsI9mwo8tFh9vsGgxpXEr7osTmyrUjxJCDwukLvI0ujM0h8eX0K gnYN9ek4wX6xr9RsPrSki/xRpQDr27mrCdeqLr3ZdtLYugMCIlEaq/Anocm2b57MEr297 YEL5YcPD5X7DIdLLOsmTjL7sUqbHNTBRFj8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1654557442777100007 Content-Type: text/plain; charset="utf-8" Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Cc: Chasel Chiu Cc: Michael Kubacki Signed-off-by: Nate DeSimone Reviewed-by: Chasel Chiu --- .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++- .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPc= d.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc index 84d4ec1331..8f3cc6ba28 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the UpXtreme board. # -# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -259,6 +259,13 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2 gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpace= Guid.PcdPciExpressRegionLength =20 + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkgPcd.dsc index 4a7ba4d5f0..4a5d5ef03b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the WhiskeylakeURvp board. # -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -242,6 +242,13 @@ ###################################### gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpace= Guid.PcdPciExpressRegionLength =20 + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90268): https://edk2.groups.io/g/devel/message/90268 Mute This Topic: https://groups.io/mt/91589973/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-