From nobody Tue Feb 10 12:57:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+90254+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90254+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1654555843; cv=none; d=zohomail.com; s=zohoarc; b=dd0AVFpfNbahZs+j+zrNBHsHn97bIz86HdRyyIwgIKlayTzPCDhag8Lo4YihQpVkdKO901gwZAUUF6AETeX0xC3VT4mQP6Jqq4Xjmb+KngNnCAXaPrf6VJT02d3QTEm0K+CaloMWyORQnHdMt5tk7oFR0pGMwdS2SVShNExfjzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654555843; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=trVRWRhABUvTBWTLmtUpVu40XyX3eQeW5zs6njm5YrI=; b=VMS4ZAtqFVb7lKIhv4+4NSgc0f+UtHRFndhBbpUgTxoaKALipgv481StRPg1DHlEV8cf3t8lWuPr1i7tC3iMDTe3TCQ+ziMUq0EuOR77ET6jwzNKqnVXh07W2fyiqKJaFkQ5q6I22ZrC2uS7qhrnb8c88t9IDPYbNuwDauIWK3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+90254+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1654555843084237.6619187549138; Mon, 6 Jun 2022 15:50:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MUipYY1788612xuJZsOKzqRG; Mon, 06 Jun 2022 15:50:42 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.5198.1654555839570502626 for ; Mon, 06 Jun 2022 15:50:41 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="340202050" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="340202050" X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="565186091" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Ankit Sinha , Michael Kubacki , Benjamin Doron , Jeremy Soller Subject: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 15:50:27 -0700 Message-Id: <20220606225030.3403-2-nathaniel.l.desimone@intel.com> In-Reply-To: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> References: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: AuNUtQFSqbpEX0gwZ10pp88lx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1654555842; bh=EtuyhvlM3hoH/FgiM1X3PzZK5ubUv9pDA/g9ptJq4UA=; h=Cc:Date:From:Reply-To:Subject:To; b=CBEq7vy+c1G7yrUuBEWFJFHN2fWKk4bRRLakuRq6Y+zu5+SZfrZ1mzz88q9l7iWNBDx OLccfRk+16viYyXY+qp/H1kjyXRbfaeJy8Y2Y77vB8TTBgfChju2W0eS5dsEXtdRTYTKA k8LGvc+CXnERQL1js7IM8E1hbgz53vfVcb0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1654555844914100016 Content-Type: text/plain; charset="utf-8" Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Merged missing PCD settings into GalagoPro3 Cc: Chasel Chiu Cc: Ankit Sinha Cc: Michael Kubacki Cc: Benjamin Doron Cc: Jeremy Soller Signed-off-by: Nate DeSimone --- .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 +++- .../GalagoPro3/OpenBoardPkgPcd.dsc | 52 +++++++++++++++++-- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++- 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoa= rdPkgPcd.dsc index 21ee86403d..02080aa864 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the Aspire VN7-572G board. # -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -346,6 +346,13 @@ gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and BI= OS Guard not present, measured boot enforcement checking code not present gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 =20 + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index 44dacdf082..26e2c16aae 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the GalagoPro3 board. # -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -40,6 +40,26 @@ # gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE =20 + # + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PE= IMs + # (both inside FSP and outside FSP). + # Pros: + # * PEI Main is re-built from source and is always the latest v= ersion + # * Platform code can link any desired LibraryClass to PEI Main + # (Ex: Custom DebugLib instance, SerialPortLib, etc.) + # Cons: + # * The PEI Main being used to execute FSP PEIMs is not the PEI= Main + # that the FSP PEIMs were tested with, adding risk of breakag= e. + # * Two copies of PEI Main will exist in the final binary, + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never + # executed, wasting space. + # + # TRUE: The PEI Main included in FSP is used to dispatch all PEI= Ms + # (both inside FSP and outside FSP). PEI Main will not be include= d in + # FvPreMemory. This is the default and is the recommended choice. + # + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE + # # FSP Base address PCD will be updated in FDF basing on flash map. # @@ -52,6 +72,7 @@ gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 =20 +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # # FSP API mode does not share stack with the boot loader, # so FSP needs more temporary memory for FSP heap + stack size. @@ -63,6 +84,24 @@ # since the stacks are separate. # gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 +!else + # + # In FSP Dispatch mode boot loader stack size must be large + # enough for executing both boot loader and FSP. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 +!endif + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and FSP= sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif =20 [PcdsFeatureFlag.common] ###################################### @@ -222,7 +261,7 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 - +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) # # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld # (They will be DynamicEx in FSP Dispatch mode) @@ -242,6 +281,7 @@ # 3: Place AP in the Run-Loop state. # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 +!endif =20 ###################################### # Silicon Configuration @@ -251,8 +291,12 @@ gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 =20 - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index 725596cbf7..ccf757e202 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the KabylakeRvp3 board. # -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +78,7 @@ # so FSP needs more temporary memory for FSP heap + stack size. # gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + # # FSP API mode does not need to enlarge the boot loader stack size # since the stacks are separate. @@ -290,6 +291,13 @@ gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 =20 + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### @@ -346,7 +354,6 @@ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} !endif =20 - ###################################### # Board Configuration ###################################### --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90254): https://edk2.groups.io/g/devel/message/90254 Mute This Topic: https://groups.io/mt/91589483/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-