From nobody Tue May 7 05:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89807+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89807+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1652777064; cv=none; d=zohomail.com; s=zohoarc; b=V9N4V17ksaCui/vtB3x1LcpiISzXaWwyt4k76V6TvduZdNwdMrFMtVkTNRK32TsuWVeE2y/Y7EHJMJ3vhDUKhcufmF3lAx+KprUEtcbZC5SsOSwvs8//hRfpXTyiUtlrx/iqZgq7NaEchrlu7a1f/K3fr/ORqFtDtVqSDqfMvGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652777064; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=u9XrDszIJ2CpSbMarl4Q6vWx8/Y+7FhSflRbL0ZqpjM=; b=a89nnf2bxYiRuVQdN+Ct2D08IAnod6oBHdFE7DWTRokjgpPPCB+afHnAC9aV36cfJrkhV+YFujW4oN4pUbMq3DlA/t3kGPOhN6cR0Sox7VaF7M/3WmTpbn6YyeEV3IaVWawWzIhRg6iLLQ17POkOHObj5Ba8SzMF44//SrasUZ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89807+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165277706453675.55862823450627; Tue, 17 May 2022 01:44:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Gdk7YY1788612xJlF6x4W8RH; Tue, 17 May 2022 01:44:24 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4835.1652777061061604497 for ; Tue, 17 May 2022 01:44:23 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="268695137" X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="268695137" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 01:44:23 -0700 X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="544805180" X-Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.201.76]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 01:44:21 -0700 From: "cbduggap" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel] [PATCH v5 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention Date: Tue, 17 May 2022 14:14:00 +0530 Message-Id: <20220517084401.1805-2-chinni.b.duggapu@intel.com> In-Reply-To: <20220517084401.1805-1-chinni.b.duggapu@intel.com> References: <20220517084401.1805-1-chinni.b.duggapu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com X-Gm-Message-State: 3qAKR5gRuMBKssMz874HMMtcx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1652777064; bh=xn+WhzB7Xtb0LrWRQ0vRkOSHYVajFlgAVY+DAwSetpI=; h=Cc:Date:From:Reply-To:Subject:To; b=HwpjOE0R7Q5GWYNv/zVYXCqxENolf+cbiOXkzlwdwK+WELPrHi7pGDkdF7tU0sGq42n 6pSjPOoh5mjhrgICmzzK5EUxznT/stLEp6LOMbhmaXg91KsfMSMOppdPQNZFoQL2Mvwl2 ujEsbosaG8t5oV14zBGVhFjeuAzwk2Y6iio= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1652777066550100003 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3926 This API accept one parameter using RCX and this is consumed in mutiple sub functions. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: cbduggap Reviewed-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++++++++++--------- .../Include/SaveRestoreSseAvxNasm.inc | 28 +++++++++++++ 2 files changed, 48 insertions(+), 19 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index a9f5f28ed7..7dd89c531a 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -114,7 +114,7 @@ endstruc global ASM_PFX(LoadMicrocodeDefault) ASM_PFX(LoadMicrocodeDefault): ; Inputs: - ; rsp -> LoadMicrocodeParams pointer + ; rcx -> LoadMicrocodeParams pointer ; Register Usage: ; rsp Preserved ; All others destroyed @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): =20 cmp rsp, 0 jz ParamError - mov eax, dword [rsp + 8] ; Parameter pointer - cmp eax, 0 + cmp rcx, 0 jz ParamError - mov esp, eax + mov rsp, rcx =20 ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k @@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault): jne ParamError =20 ; UPD structure is compliant with FSP spec 2.4 - mov eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] - cmp eax, 0 + mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] + cmp rax, 0 jz Exit2 - cmp eax, 0800h + cmp rax, 0800h jl ParamError =20 - mov esi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] - cmp esi, 0 + mov rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] + cmp rsi, 0 jnz CheckMainHeader =20 ParamError: @@ -256,7 +255,8 @@ CheckAddress: ; UPD structure is compliant with FSP spec 2.4 ; Is automatic size detection ? mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] - cmp rax, 0ffffffffffffffffh + mov rcx, 0ffffffffffffffffh + cmp rax, rcx jz LoadMicrocodeDefault4 =20 ; Address >=3D microcode region address + microcode region size? @@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp): ; ; Save parameter pointer in rdx ; - mov rdx, qword [rsp + 8] - + mov rdx, rcx ; ; Enable FSP STACK ; @@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi): ; ENABLE_SSE ENABLE_AVX - + ; + ; Save Input Parameter in YMM10 + ; + SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6 ; @@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi): ; ; Check Parameter ; - mov rax, qword [rsp + 8] - cmp rax, 0 - mov rax, 08000000000000002h + cmp rcx, 0 + mov rcx, 08000000000000002h jz TempRamInitExit =20 ; @@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi): jnz TempRamInitExit =20 ; Load microcode - LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT= 0 in YMM9 (upper 128bits). ; @note If return value rax is not 0, microcode did not load, but contin= ue and attempt to boot. =20 ; Call Sec CAR Init - LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit =20 - LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp rax, 0 jnz TempRamInitExit diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index e8bd91669d..38c807a311 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -177,6 +177,30 @@ LXMMN xmm5, %1, 1 %endmacro =20 +; +; Upper half of YMM10 to save/restore RCX +; +; +; Save RCX to YMM10[128:191] +; Modified: XMM5 and YMM10 +; + +%macro SAVE_RCX 0 + LYMMN ymm10, xmm5, 1 + SXMMN xmm5, 0, rcx + SYMMN ymm10, 1, xmm5 + %endmacro + +; +; Restore RCX from YMM10[128:191] +; Modified: XMM5 and RCX +; + +%macro LOAD_RCX 0 + LYMMN ymm10, xmm5, 1 + movq rcx, xmm5 + %endmacro + ; ; YMM7[128:191] for calling stack ; arg 1:Entry @@ -231,6 +255,7 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est ; whether the processor supports SSE instruction. ; + mov r10, rcx mov rax, 1 cpuid bt rdx, 25 @@ -241,6 +266,7 @@ NextAddress: ; bt ecx, 19 jnc SseError + mov rcx, r10 =20 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) @@ -258,6 +284,7 @@ NextAddress: %endmacro =20 %macro ENABLE_AVX 0 + mov r10, rcx mov eax, 1 cpuid and ecx, 10000000h @@ -280,5 +307,6 @@ EnableAvx: xgetbv ; result in edx:eax or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state xsetbv + mov rcx, r10 %endmacro =20 --=20 2.36.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89807): https://edk2.groups.io/g/devel/message/89807 Mute This Topic: https://groups.io/mt/91159381/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 05:12:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89808+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89808+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1652777069; cv=none; d=zohomail.com; s=zohoarc; b=hvZZcG/WWuwFmO94NHgidusqfccaYuJrWsMI0QPEXIteZFlXrTFpQ3nuW/xxd6svzLG++arIbLHFa8j8maAa2lx+uHp6pPiRp6GRfvZgi533/iugaToszFrC9cmz6Ai1gmJITxxDSlNLGt3XuXSkouDmItxffoYxmAXL/QxVjGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652777069; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NQfBfILIdx8k/OYdePIwLfut4l6Flb9JBUH0XSXjrZU=; b=jmR7W9a60KxQWPjI/NyoKhQamhfJvjUGd0Y5NmjXicPfHC/IlYq/nZ0RtoDVwnq2MkE3uim5onVV6dr/66t4wEkGlNunSuLKvaOlx+6/+zNREAe2zvOmsq7XE3OaDEkEbXNyqbZOHxSAEvDI+SLp/YPIGp3s4zEkDzRT8+9oXLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89808+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165277706962632.422124998789286; Tue, 17 May 2022 01:44:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id n3ILYY1788612xnAuxUnlDbd; Tue, 17 May 2022 01:44:29 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4835.1652777061061604497 for ; Tue, 17 May 2022 01:44:28 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="268695160" X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="268695160" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 01:44:28 -0700 X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="544805226" X-Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.201.76]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 01:44:26 -0700 From: "cbduggap" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel] [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention Date: Tue, 17 May 2022 14:14:01 +0530 Message-Id: <20220517084401.1805-3-chinni.b.duggapu@intel.com> In-Reply-To: <20220517084401.1805-1-chinni.b.duggapu@intel.com> References: <20220517084401.1805-1-chinni.b.duggapu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com X-Gm-Message-State: ByY3T604D226eRJbhHXpgqS3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1652777069; bh=fPgL4yAWg20dIZ/dShHiv+8zteysrOoVP5M01O2hp14=; h=Cc:Date:From:Reply-To:Subject:To; b=rlTvTobYLf/kva4oPF6WJFB05yCNWZ3vMi1e69kGCESLcImcmfGro5suR+k0fas6rhu qAsU3sIP0bUL6ngeGkOCXYoYDeOBHbzqHLfL533sPzTSUn/0Cmiyz0i4S3yBNdBhhAJBX 6ODvWbnjWcXWdfLBURo631iaBHUyHwwE+os= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1652777070582100001 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3926 Pass Input parameters using RCX. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: cbduggap Reviewed-by: Chasel Chiu --- .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= X64/SecEntry.nasm b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLib= Sample/X64/SecEntry.nasm index dbbf63336e..065d80d0e2 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/Sec= Entry.nasm +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/Sec= Entry.nasm @@ -130,6 +130,9 @@ FspHeaderFound: mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] =20 + ; Pass Fsp T Udp pointer as Input parameter + mov rcx, ASM_PFX(FsptUpdDataPtr) + ; Setup the hardcode stack mov rsp, TempRamInitStack =20 @@ -167,5 +170,4 @@ FspApiFailed: align 10h TempRamInitStack: DQ TempRamInitDone - DQ ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams =20 --=20 2.36.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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