From nobody Sun Feb 8 19:37:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89746+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89746+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1652685268; cv=none; d=zohomail.com; s=zohoarc; b=Z/nnIo7+HZJtgiR+Sn/ZQt+OPX3d5h7xC2lrJaItZ11rREku4sFqU4f2Wcf+85oNpMNy4sUVfHBre8/k0+FFSy9KivW7D+ILj90JSr/deBmzkNbW86h0QUgHImEu7h28xkW6YJ+K4KYDPMGtWa4Qq28zizwVG1v1elhXRMobN74= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652685268; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zjUsTvXxaPp+kgMwn00xBq05W5sAWrb5acmLhdnxD8M=; b=K3UDjNGKgtFoLxjqcs2geB5GWd4NoZov18GDg5OJtBcsBfzZM9FbhrvQiikbNQQfOF6WhyY9TgXthxeocL3t7drApTC86c2s/+oxxCzLHygMRN3fvgo69es6WsXrDtFBgEMJDbULcq4ZiypdjSyp0QdVi3oBn5H1Es8Y/jTu2y8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89746+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165268526851415.272592488661985; Mon, 16 May 2022 00:14:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1YgpYY1788612xZ2DnS6zujt; Mon, 16 May 2022 00:14:28 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web09.26060.1652685265461479831 for ; Mon, 16 May 2022 00:14:27 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10348"; a="270451779" X-IronPort-AV: E=Sophos;i="5.91,229,1647327600"; d="scan'208";a="270451779" X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 00:14:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,229,1647327600"; d="scan'208";a="555129038" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga002.jf.intel.com with ESMTP; 16 May 2022 00:14:22 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Michael Roth , James Bottomley , Min Xu , Jiewen Yao , Tom Lendacky , Jordan Justen , Ard Biesheuvel , Erdem Aktas , Gerd Hoffmann Subject: [edk2-devel] [PATCH v3 3/5] MpInitLib: Put SEV logic in separate file Date: Mon, 16 May 2022 15:14:10 +0800 Message-Id: <20220516071412.359-4-ray.ni@intel.com> In-Reply-To: <20220516071412.359-1-ray.ni@intel.com> References: <20220516071412.359-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: 1Hr4kV5AjAFyJRUKF2MYYHVMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1652685268; bh=QSab90+d0YNIP5Vfk/ARB9ekVBChdTWYswVdzrbds9c=; h=Cc:Date:From:Reply-To:Subject:To; b=ZiFWIvnvDztBTIY6fy4cS9DDam+1MmWGhId5T8zJboHumfbhsKM/u3CJGcgLY1qveCH tZJb+8jbODrDJuphUmM42XX53M9E7lpz/u3Df7Wo+WhaGKhBfMsYLam7xUe3GRCSk5eUi A55WiRn9W3CYZMS0IMLZ5dRklYbbd1xo9G4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1652686171352100001 Content-Type: text/plain; charset="utf-8" The patch does several simplifications: 1. Treat SwitchToRealProc as part of RendezvousFunnelProc. So the common logic in MpLib.c doesn't need to be aware of SwitchToRealProc. As a result, SwitchToRealSize/Offset are removed from MP_ASSEMBLY_ADDRESS_MAP. 2. Move SwitchToRealProc to AmdSev.nasm. All other assembly code in AmdSev.nasm is called through OneTimeCall. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Michael Roth Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Erdem Aktas Cc: Gerd Hoffmann Reviewed-by: Tom Lendacky Tested-by: Tom Lendacky --- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 5 +- UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 4 +- UefiCpuPkg/Library/MpInitLib/MpLib.c | 13 +- UefiCpuPkg/Library/MpInitLib/MpLib.h | 4 +- UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 148 ++++++++++++++++ UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 159 +----------------- 6 files changed, 161 insertions(+), 172 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index 8981c32722..28301bb8f0 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -199,7 +199,6 @@ CProcedureInvoke: call eax ; Invoke C function =20 jmp $ ; Never reach here -RendezvousFunnelProcEnd: =20 ;-------------------------------------------------------------------------= ------------ ;SwitchToRealProc procedure follows. @@ -209,6 +208,8 @@ SwitchToRealProcStart: jmp $ ; Never reach here SwitchToRealProcEnd: =20 +RendezvousFunnelProcEnd: + ;-------------------------------------------------------------------------= ------------ ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); ; @@ -258,8 +259,6 @@ ASM_PFX(AsmGetAddressMap): mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], AsmRelocateApLoopStart mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart - mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], Swi= tchToRealProcEnd - SwitchToRealProcStart - mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], S= witchToRealProcStart - RendezvousFunnelProcStart mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], 0 mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSi= ze], 0 diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/Mp= InitLib/MpEqu.inc index aba53f5720..1cc071cf7b 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,8 +27,6 @@ struc MP_ASSEMBLY_ADDRESS_MAP .RelocateApLoopFuncAddress CTYPE_UINTN 1 .RelocateApLoopFuncSize CTYPE_UINTN 1 .ModeTransitionOffset CTYPE_UINTN 1 - .SwitchToRealSize CTYPE_UINTN 1 - .SwitchToRealOffset CTYPE_UINTN 1 .SwitchToRealNoNxOffset CTYPE_UINTN 1 .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 .SwitchToRealPM16ModeSize CTYPE_UINTN 1 diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index d761bdc487..aa0eb9a70b 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -936,8 +936,7 @@ FillExchangeInfoData ( // EfiBootServicesCode to avoid page fault if NX memory protection is en= abled. // if (CpuMpData->WakeupBufferHigh !=3D 0) { - Size =3D CpuMpData->AddressMap.RendezvousFunnelSize + - CpuMpData->AddressMap.SwitchToRealSize - + Size =3D CpuMpData->AddressMap.RendezvousFunnelSize - CpuMpData->AddressMap.ModeTransitionOffset; CopyMem ( (VOID *)CpuMpData->WakeupBufferHigh, @@ -991,8 +990,7 @@ BackupAndPrepareWakeupBuffer ( CopyMem ( (VOID *)CpuMpData->WakeupBuffer, (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress, - CpuMpData->AddressMap.RendezvousFunnelSize + - CpuMpData->AddressMap.SwitchToRealSize + CpuMpData->AddressMap.RendezvousFunnelSize ); } =20 @@ -1029,7 +1027,6 @@ GetApResetVectorSize ( UINTN Size; =20 Size =3D AddressMap->RendezvousFunnelSize + - AddressMap->SwitchToRealSize + sizeof (MP_CPU_EXCHANGE_INFO); =20 return Size; @@ -1054,11 +1051,9 @@ AllocateResetVector ( CpuMpData->WakeupBuffer =3D GetWakeupBuffer (ApResetVectorSize); CpuMpData->MpCpuExchangeInfo =3D (MP_CPU_EXCHANGE_INFO *)(UINTN) (CpuMpData->WakeupBuffer + - CpuMpData->AddressMap.RendezvousFunnel= Size + - CpuMpData->AddressMap.SwitchToRealSize= ); + CpuMpData->AddressMap.RendezvousFunnel= Size); CpuMpData->WakeupBufferHigh =3D AllocateCodeBuffer ( - CpuMpData->AddressMap.RendezvousFunnel= Size + - CpuMpData->AddressMap.SwitchToRealSize= - + CpuMpData->AddressMap.RendezvousFunnel= Size - CpuMpData->AddressMap.ModeTransitionOf= fset ); // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 59ab960897..974fb76019 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -1,7 +1,7 @@ /** @file Common header file for MP Initialize Library. =20 - Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -181,8 +181,6 @@ typedef struct { UINT8 *RelocateApLoopFuncAddress; UINTN RelocateApLoopFuncSize; UINTN ModeTransitionOffset; - UINTN SwitchToRealSize; - UINTN SwitchToRealOffset; UINTN SwitchToRealNoNxOffset; UINTN SwitchToRealPM16ModeOffset; UINTN SwitchToRealPM16ModeSize; diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Libr= ary/MpInitLib/X64/AmdSev.nasm index 8bb1161fa0..7c2469f9c5 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -198,3 +198,151 @@ RestoreGhcb: =20 SevEsGetApicIdExit: OneTimeCallRet SevEsGetApicId + + +;-------------------------------------------------------------------------= ------------ +;SwitchToRealProc procedure follows. +;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENC= E THIS PROC +;IS IN MACHINE CODE. +; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINT= N StackStart) +; rcx - Buffer Start +; rdx - Code16 Selector Offset +; r8 - Code32 Selector Offset +; r9 - Stack Start +;-------------------------------------------------------------------------= ------------ +SwitchToRealProcStart: +BITS 64 + cli + + ; + ; Get RDX reset value before changing stacks since the + ; new stack won't be able to accomodate a #VC exception. + ; + push rax + push rbx + push rcx + push rdx + + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for = RDX + + pop rdx + pop rcx + pop rbx + pop rax + + ; + ; Establish stack below 1MB + ; + mov rsp, r9 + + ; + ; Push ultimate Reset Vector onto the stack + ; + mov rax, rcx + shr rax, 4 + push word 0x0002 ; RFLAGS + push ax ; CS + push word 0x0000 ; RIP + push word 0x0000 ; For alignment, will be discar= ded + + ; + ; Get address of "16-bit operand size" label + ; + lea rbx, [PM16Mode] + + ; + ; Push addresses used to change to compatibility mode + ; + lea rax, [CompatMode] + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; + retfq + +BITS 32 +CompatMode: + ; + ; Set up stack to prepare for exiting protected mode + ; + push edx ; Code16 CS + push ebx ; PM16Mode label address + + ; + ; Disable paging + ; + mov eax, cr0 ; Read CR0 + btr eax, 31 ; Set PG=3D0 + mov cr0, eax ; Write CR0 + + ; + ; Disable long mode + ; + mov ecx, 0c0000080h ; EFER MSR number + rdmsr ; Read EFER + btr eax, 8 ; Set LME=3D0 + wrmsr ; Write EFER + + ; + ; Disable PAE + ; + mov eax, cr4 ; Read CR4 + btr eax, 5 ; Set PAE=3D0 + mov cr4, eax ; Write CR4 + + mov edx, esi ; Restore RDX reset value + + ; + ; Switch to 16-bit operand size + ; + retf + +BITS 16 + ; + ; At entry to this label + ; - RDX will have its reset value + ; - On the top of the stack + ; - Alignment data (two bytes) to be discarded + ; - IP for Real Mode (two bytes) + ; - CS for Real Mode (two bytes) + ; + ; This label is also used with AsmRelocateApLoop. During MP finalizati= on, + ; the code from PM16Mode to SwitchToRealProcEnd is copied to the start= of + ; the WakeupBuffer, allowing a parked AP to be booted by an OS. + ; +PM16Mode: + mov eax, cr0 ; Read CR0 + btr eax, 0 ; Set PE=3D0 + mov cr0, eax ; Write CR0 + + pop ax ; Discard alignment data + + ; + ; Clear registers (except RDX and RSP) before going into 16-bit mode + ; + xor eax, eax + xor ebx, ebx + xor ecx, ecx + xor esi, esi + xor edi, edi + xor ebp, ebp + + iret + +SwitchToRealProcEnd: diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index d7e0e1fabd..1daaa72b1e 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -152,11 +152,6 @@ SkipEnable5LevelPaging: =20 BITS 64 =20 -; -; Required for the AMD SEV helper functions -; -%include "AmdSev.nasm" - LongModeStart: mov esi, ebx lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)] @@ -265,154 +260,12 @@ CProcedureInvoke: add rsp, 20h jmp $ ; Should never reach here =20 -RendezvousFunnelProcEnd: - -;-------------------------------------------------------------------------= ------------ -;SwitchToRealProc procedure follows. -;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENC= E THIS PROC -;IS IN MACHINE CODE. -; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINT= N StackStart) -; rcx - Buffer Start -; rdx - Code16 Selector Offset -; r8 - Code32 Selector Offset -; r9 - Stack Start -;-------------------------------------------------------------------------= ------------ -SwitchToRealProcStart: -BITS 64 - cli - - ; - ; Get RDX reset value before changing stacks since the - ; new stack won't be able to accomodate a #VC exception. - ; - push rax - push rbx - push rcx - push rdx - - mov rax, 1 - cpuid - mov rsi, rax ; Save off the reset value for = RDX - - pop rdx - pop rcx - pop rbx - pop rax - - ; - ; Establish stack below 1MB - ; - mov rsp, r9 - - ; - ; Push ultimate Reset Vector onto the stack - ; - mov rax, rcx - shr rax, 4 - push word 0x0002 ; RFLAGS - push ax ; CS - push word 0x0000 ; RIP - push word 0x0000 ; For alignment, will be discar= ded - - ; - ; Get address of "16-bit operand size" label - ; - lea rbx, [PM16Mode] - - ; - ; Push addresses used to change to compatibility mode - ; - lea rax, [CompatMode] - push r8 - push rax - - ; - ; Clear R8 - R15, for reset, before going into 32-bit mode - ; - xor r8, r8 - xor r9, r9 - xor r10, r10 - xor r11, r11 - xor r12, r12 - xor r13, r13 - xor r14, r14 - xor r15, r15 - - ; - ; Far return into 32-bit mode - ; - retfq - -BITS 32 -CompatMode: - ; - ; Set up stack to prepare for exiting protected mode - ; - push edx ; Code16 CS - push ebx ; PM16Mode label address - - ; - ; Disable paging - ; - mov eax, cr0 ; Read CR0 - btr eax, 31 ; Set PG=3D0 - mov cr0, eax ; Write CR0 - - ; - ; Disable long mode - ; - mov ecx, 0c0000080h ; EFER MSR number - rdmsr ; Read EFER - btr eax, 8 ; Set LME=3D0 - wrmsr ; Write EFER - - ; - ; Disable PAE - ; - mov eax, cr4 ; Read CR4 - btr eax, 5 ; Set PAE=3D0 - mov cr4, eax ; Write CR4 - - mov edx, esi ; Restore RDX reset value - - ; - ; Switch to 16-bit operand size - ; - retf - -BITS 16 - ; - ; At entry to this label - ; - RDX will have its reset value - ; - On the top of the stack - ; - Alignment data (two bytes) to be discarded - ; - IP for Real Mode (two bytes) - ; - CS for Real Mode (two bytes) - ; - ; This label is also used with AsmRelocateApLoop. During MP finalizati= on, - ; the code from PM16Mode to SwitchToRealProcEnd is copied to the start= of - ; the WakeupBuffer, allowing a parked AP to be booted by an OS. - ; -PM16Mode: - mov eax, cr0 ; Read CR0 - btr eax, 0 ; Set PE=3D0 - mov cr0, eax ; Write CR0 - - pop ax ; Discard alignment data - - ; - ; Clear registers (except RDX and RSP) before going into 16-bit mode - ; - xor eax, eax - xor ebx, ebx - xor ecx, ecx - xor esi, esi - xor edi, edi - xor ebp, ebp - - iret +; +; Required for the AMD SEV helper functions +; +%include "AmdSev.nasm" =20 -SwitchToRealProcEnd: +RendezvousFunnelProcEnd: =20 ;-------------------------------------------------------------------------= ------------ ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); @@ -596,8 +449,6 @@ ASM_PFX(AsmGetAddressMap): mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], rax mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart - mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], Swi= tchToRealProcEnd - SwitchToRealProcStart - mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], S= witchToRealProcStart - RendezvousFunnelProcStart mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], PM16Mode - RendezvousFunnelProcStart mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSi= ze], SwitchToRealProcEnd - PM16Mode --=20 2.35.1.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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