From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89487+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89487+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603722; cv=none; d=zohomail.com; s=zohoarc; b=X0RcMmvpep+jfeWoVhboRqYlN3aEAMWVBFy0OzlU68aMw3Z7B7K1LqY5Ov/6ZCZt+U1ZEQHZV/L87b+5VF3/o80elyssAtmCqGJWPIrBtzWWm61pu6preCXB/sh4eMF4OxPGLKO0aoSsmdFsIqruqxFffvghMjke092WMflCU90= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603722; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=CQHJgxO8ji2qRpGWhCN6ENAGntgwqebaiqpydXtjx5c=; b=HmtSlFRQfx5lb/MZZqbE0ZpzCg74sDnMZMSmDokKp0lbJVtRLwXQ1f7lv69lLmYIRJiOnbEOmW0bRvNeZElUwvWdm2A04YhFlf4wtajVyEdY//1i64YlOLoO6m/nCqscEYflGjHKkpDrtOF8EApYoaq46gmixKwvss5qmC7hgMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89487+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603722307997.5079949664265; Tue, 3 May 2022 11:48:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id EITqYY1788612xZdWcSfGeA5; Tue, 03 May 2022 11:48:41 -0700 X-Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web08.1014.1651603719238416815 for ; Tue, 03 May 2022 11:48:40 -0700 X-Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 03 May 2022 11:48:40 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:40 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:39 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:37 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 01/10] ArmPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:11 -0600 Message-ID: <20220503184820.19312-2-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: mFSdQaJ4bjcAhvBVoFxuNtAtx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603721; bh=xu1uQJw+8wZHS7ayikls337B5kQ73mCQrnkbsOTgjjk=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=iYONjgAR19hUiHGWn5crRDit3ovP1VWJ+lye7WZ/4OQ0y7y+PFC8mONItTztnc/hge3 C8/Zw4uUBI+4WxXP3/0WnjWj1UviS6or3cXcu0JiUIHWUPdEVj1MkCIQFrGn6rk3RMqqO m87rM0L2zEJhRVqS8na+FIAPgXKjs+qW33Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603723248100007 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 1 - ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm | 82 ------ ArmPkg/Include/AsmMacroExport.inc | 23 -- ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 296 -----= --------------- ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 1 - ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf | 1 - ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm | 46 --- ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf | 4 - ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 174 -----= ------- ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 107 -----= -- ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm | 93 ------ ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 292 -----= -------------- ArmPkg/Library/ArmLib/ArmBaseLib.inf | 5 - ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibV7Support.asm | 26 -- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 1 - ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm | 45 --- ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf | 4 - ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm | 36 --- ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf | 1 - ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm | 34 --- ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm | 36 --- ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm | 46 --- ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm | 43 --- ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm | 22 -- ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm | 58 ---- ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm | 60 ---- ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 15 - 27 files changed, 1552 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/Ar= mGicLib.inf index 5e23c732bfab..addb8d3153bf 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf @@ -22,7 +22,6 @@ =20 [Sources.ARM] GicV3/Arm/ArmGicV3.S | GCC - GicV3/Arm/ArmGicV3.asm | RVCT =20 [Sources.AARCH64] GicV3/AArch64/ArmGicV3.S diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/ArmPkg/Drivers/= ArmGic/GicV3/Arm/ArmGicV3.asm deleted file mode 100644 index bf79c1350cd4..000000000000 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm +++ /dev/null @@ -1,82 +0,0 @@ -// -// Copyright (c) 2014, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -// For the moment we assume this will run in SVC mode on ARMv7 - - - INCLUDE AsmMacroExport.inc - -//UINT32 -//EFIAPI -//ArmGicGetControlSystemRegisterEnable ( -// VOID -// ); - RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable - mrc p15, 0, r0, c12, c12, 5 // ICC_SRE - bx lr - -//VOID -//EFIAPI -//ArmGicSetControlSystemRegisterEnable ( -// IN UINT32 ControlSystemRegisterEnable -// ); - RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable - mcr p15, 0, r0, c12, c12, 5 // ICC_SRE - isb - bx lr - -//VOID -//ArmGicV3EnableInterruptInterface ( -// VOID -// ); - RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface - mov r0, #1 - mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 - bx lr - -//VOID -//ArmGicV3DisableInterruptInterface ( -// VOID -// ); - RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface - mov r0, #0 - mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 - bx lr - -//VOID -//ArmGicV3EndOfInterrupt ( -// IN UINTN InterruptId -// ); - RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt - mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1 - bx lr - -//UINTN -//ArmGicV3AcknowledgeInterrupt ( -// VOID -// ); - RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt - mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1 - bx lr - -//VOID -//ArmGicV3SetPriorityMask ( -// IN UINTN Priority -// ); - RVCT_ASM_EXPORT ArmGicV3SetPriorityMask - mcr p15, 0, r0, c4, c6, 0 //ICC_PMR - bx lr - -//VOID -//ArmGicV3SetBinaryPointer ( -// IN UINTN BinaryPoint -// ); - RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer - mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1 - bx lr - - END diff --git a/ArmPkg/Include/AsmMacroExport.inc b/ArmPkg/Include/AsmMacroExp= ort.inc deleted file mode 100644 index 615feee541b6..000000000000 --- a/ArmPkg/Include/AsmMacroExport.inc +++ /dev/null @@ -1,23 +0,0 @@ -;%HEADER% -;/** @file -; Macros to centralize the EXPORT, AREA, and definition of an assembly -; function. The AREA prefix is required to put the function in its own -; section so that removal of unused functions in the final link is perfor= med. -; This provides equivalent functionality to the compiler's --split-secti= ons -; option. -; -; Copyright (c) 2015 HP Development Company, L.P. -; -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;**/ - - - MACRO - RVCT_ASM_EXPORT $func - EXPORT $func - AREA s_$func, CODE, READONLY -$func - MEND - - END diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmP= kg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm deleted file mode 100644 index aa0229d2e85f..000000000000 --- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm +++ /dev/null @@ -1,296 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Use ARMv6 instruction to operate on a single stack -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// Copyright (c) 2014, ARM Limited. All rights reserved.
-// Copyright (c) 2016 HP Development Company, L.P.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - -#include - -/* - -This is the stack constructed by the exception handler (low address to hig= h address) - # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM - Reg Offset - =3D=3D=3D =3D=3D=3D=3D=3D=3D - R0 0x00 # stmfd SP!,{R0-R12} - R1 0x04 - R2 0x08 - R3 0x0c - R4 0x10 - R5 0x14 - R6 0x18 - R7 0x1c - R8 0x20 - R9 0x24 - R10 0x28 - R11 0x2c - R12 0x30 - SP 0x34 # reserved via subtraction 0x20 (32) from SP - LR 0x38 - PC 0x3c - CPSR 0x40 - DFSR 0x44 - DFAR 0x48 - IFSR 0x4c - IFAR 0x50 - - LR 0x54 # SVC Link register (we need to restore it) - - LR 0x58 # pushed by srsfd - CPSR 0x5c - - */ - - - EXPORT ExceptionHandlersStart - EXPORT ExceptionHandlersEnd - EXPORT CommonExceptionEntry - EXPORT AsmCommonExceptionEntry - IMPORT CommonCExceptionHandler - - PRESERVE8 - AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=3D5 - -// -// This code gets copied to the ARM vector table -// ExceptionHandlersStart - ExceptionHandlersEnd gets copied -// -ExceptionHandlersStart - -Reset - b ResetEntry - -UndefinedInstruction - b UndefinedInstructionEntry - -SoftwareInterrupt - b SoftwareInterruptEntry - -PrefetchAbort - b PrefetchAbortEntry - -DataAbort - b DataAbortEntry - -ReservedException - b ReservedExceptionEntry - -Irq - b IrqEntry - -Fiq - b FiqEntry - -ResetEntry - srsfd #0x13! ; Store return state on SVC stack - ; We are already in SVC mode - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#0 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -UndefinedInstructionEntry - sub LR, LR, #4 ; Only -2 for Thumb, adjust in Commo= nExceptionEntry - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#1 ; ExceptionType - ldr R1,CommonExceptionEntry; - bx R1 - -SoftwareInterruptEntry - srsfd #0x13! ; Store return state on SVC stack - ; We are already in SVC mode - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#2 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -PrefetchAbortEntry - sub LR,LR,#4 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#3 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -DataAbortEntry - sub LR,LR,#8 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#4 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -ReservedExceptionEntry - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#5 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -IrqEntry - sub LR,LR,#4 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#6 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -FiqEntry - sub LR,LR,#4 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR - stmfd SP!,{R0-R12} ; Store the register state - ; Since we have already switch to SV= C R8_fiq - R12_fiq - ; never get used or saved - mov R0,#7 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -// -// This gets patched by the C code that patches in the vector table -// -CommonExceptionEntry - dcd AsmCommonExceptionEntry - -ExceptionHandlersEnd - -// -// This code runs from CpuDxe driver loaded address. It is patched into -// CommonExceptionEntry. -// -AsmCommonExceptionEntry - mrc p15, 0, R1, c6, c0, 2 ; Read IFAR - str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.I= FAR - - mrc p15, 0, R1, c5, c0, 1 ; Read IFSR - str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.I= FSR - - mrc p15, 0, R1, c6, c0, 0 ; Read DFAR - str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.D= FAR - - mrc p15, 0, R1, c5, c0, 0 ; Read DFSR - str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.D= FSR - - ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on th= e stack - str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.C= PSR - - add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_= ARM.LR - and R3, R1, #0x1f ; Check CPSR to see if User or System = Mode - cmp R3, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D= =3D 0x1f)) - cmpne R3, #0x10 ; - stmeqed R2, {lr}^ ; save unbanked lr - ; else - stmneed R2, {lr} ; save SVC lr - - - ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd - ; Check to see if we have to adjust fo= r Thumb entry - sub r4, r0, #1 ; if (ExceptionType =3D=3D 1 || Except= ionType =3D=3D 2)) { - cmp r4, #1 ; // UND & SVC have different LR adj= ust for Thumb - bhi NoAdjustNeeded - - tst r1, #0x20 ; if ((CPSR & T)) =3D=3D T) { // Th= umb Mode on entry - addne R5, R5, #2 ; PC +=3D 2; - strne R5,[SP,#0x58] ; Update LR value pushed by srsfd - -NoAdjustNeeded - - str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC - - add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack - str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP - - ; R0 is ExceptionType - mov R1,SP ; R1 is SystemContext - -#if (FixedPcdGet32(PcdVFPEnabled)) - vpush {d0-d15} ; save vstm registers in case they are= used in optimizations -#endif - - mov R4, SP ; Save current SP - tst R4, #4 - subne SP, SP, #4 ; Adjust SP if not 8-byte aligned - -/* -VOID -EFIAPI -CommonCExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, R0 - IN OUT EFI_SYSTEM_CONTEXT SystemContext R1 - ) - -*/ - blx CommonCExceptionHandler ; Call exception handler - - mov SP, R4 ; Restore SP - -#if (FixedPcdGet32(PcdVFPEnabled)) - vpop {d0-d15} -#endif - - ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR - mcr p15, 0, R1, c5, c0, 1 ; Write IFSR - - ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR - mcr p15, 0, R1, c5, c0, 0 ; Write DFSR - - ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC - str R1,[SP,#0x58] ; Store it back to srsfd stack slot so= it can be restored - - ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR - str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so= it can be restored - - add R3, SP, #0x54 ; Make R3 point to SVC LR saved on ent= ry - add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_= ARM.LR - and R1, R1, #0x1f ; Check to see if User or System Mode - cmp R1, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D= =3D 0x1f)) - cmpne R1, #0x10 ; - ldmeqed R2, {lr}^ ; restore unbanked lr - ; else - ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR} - - ldmfd SP!,{R0-R12} ; Restore general purpose registers - ; Exception handler can not change SP - - add SP,SP,#0x20 ; Clear out the remaining stack space - ldmfd SP!,{LR} ; restore the link register for this c= ontext - rfefd SP! ; return from exception via srsfd stac= k slot - - END - - diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf b/ArmPkg/Li= brary/ArmExceptionLib/ArmExceptionLib.inf index fdb9c24d21bc..68ed1c5c5935 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf @@ -33,7 +33,6 @@ =20 [Sources.Arm] Arm/ArmException.c - Arm/ExceptionSupport.asm | RVCT Arm/ExceptionSupport.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf b/A= rmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf index ef1a43a27c45..ca70daa2847c 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf +++ b/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf @@ -28,7 +28,6 @@ =20 [Sources.Arm] Arm/ArmException.c - Arm/ExceptionSupport.asm | RVCT Arm/ExceptionSupport.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm b/ArmPkg/Library/ArmHv= cLib/Arm/ArmHvc.asm deleted file mode 100644 index 01e4d3f9cfe6..000000000000 --- a/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright (c) 2012-2014, ARM Limited. All rights reserved. -// Copyright (c) 2014, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - - - INCLUDE AsmMacroExport.inc - - RVCT_ASM_EXPORT ArmCallHvc - push {r4-r8} - // r0 will be popped just after the HVC call - push {r0} - - // Load the HVC arguments values into the appropriate registers - ldr r7, [r0, #28] - ldr r6, [r0, #24] - ldr r5, [r0, #20] - ldr r4, [r0, #16] - ldr r3, [r0, #12] - ldr r2, [r0, #8] - ldr r1, [r0, #4] - ldr r0, [r0, #0] - - hvc #0 - - // Pop the ARM_HVC_ARGS structure address from the stack into r8 - pop {r8} - - // Load the HVC returned values into the appropriate registers - // A HVC call can return up to 4 values - we do not need to store back= r4-r7. - str r3, [r8, #12] - str r2, [r8, #8] - str r1, [r8, #4] - str r0, [r8, #0] - - mov r0, r8 - - // Restore the registers r4-r8 - pop {r4-r8} - - bx lr - - END diff --git a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf b/ArmPkg/Library/ArmHvc= Lib/ArmHvcLib.inf index 69f68f63d7a6..c5f2a016c0cd 100644 --- a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf +++ b/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf @@ -15,7 +15,6 @@ LIBRARY_CLASS =3D ArmHvcLib =20 [Sources.ARM] - Arm/ArmHvc.asm | RVCT Arm/ArmHvc.S | GCC =20 [Sources.AARCH64] @@ -24,6 +23,3 @@ [Packages] MdePkg/MdePkg.dec ArmPkg/ArmPkg.dec - -[BuildOptions] - RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu Cortex-A15 diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/A= rmLib/Arm/ArmLibSupport.asm deleted file mode 100644 index 1265dddea636..000000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm +++ /dev/null @@ -1,174 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - INCLUDE AsmMacroIoLib.inc - - - INCLUDE AsmMacroExport.inc - - RVCT_ASM_EXPORT ArmReadMidr - mrc p15,0,R0,c0,c0,0 - bx LR - - RVCT_ASM_EXPORT ArmCacheInfo - mrc p15,0,R0,c0,c0,1 - bx LR - - RVCT_ASM_EXPORT ArmGetInterruptState - mrs R0,CPSR - tst R0,#0x80 // Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - - RVCT_ASM_EXPORT ArmGetFiqState - mrs R0,CPSR - tst R0,#0x40 // Check if FIQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - - RVCT_ASM_EXPORT ArmSetDomainAccessControl - mcr p15,0,r0,c3,c0,0 - bx lr - - RVCT_ASM_EXPORT CPSRMaskInsert - stmfd sp!, {r4-r12, lr} // save all the banked registers - mov r3, sp // copy the stack pointer into a non-banked re= gister - mrs r2, cpsr // read the cpsr - bic r2, r2, r0 // clear mask in the cpsr - and r1, r1, r0 // clear bits outside the mask in the input - orr r2, r2, r1 // set field - msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode swi= tch) - isb - mov sp, r3 // restore stack pointer - ldmfd sp!, {r4-r12, lr} // restore registers - bx lr // return (hopefully thumb-safe!) = // return (hopefully thumb-safe!) - - RVCT_ASM_EXPORT CPSRRead - mrs r0, cpsr - bx lr - - RVCT_ASM_EXPORT ArmReadCpacr - mrc p15, 0, r0, c1, c0, 2 - bx lr - - RVCT_ASM_EXPORT ArmWriteCpacr - mcr p15, 0, r0, c1, c0, 2 - isb - bx lr - - RVCT_ASM_EXPORT ArmWriteAuxCr - mcr p15, 0, r0, c1, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmReadAuxCr - mrc p15, 0, r0, c1, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmSetTTBR0 - mcr p15,0,r0,c2,c0,0 - isb - bx lr - - RVCT_ASM_EXPORT ArmSetTTBCR - mcr p15, 0, r0, c2, c0, 2 - isb - bx lr - - RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress - mrc p15,0,r0,c2,c0,0 - MOV32 r1, 0xFFFFC000 - and r0, r0, r1 - isb - bx lr - -// -//VOID -//ArmUpdateTranslationTableEntry ( -// IN VOID *TranslationTableEntry // R0 -// IN VOID *MVA // R1 -// ); - RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry - mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA - dsb - mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA - mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor arra= y. R9 =3D=3D NoOp - dsb - isb - bx lr - - RVCT_ASM_EXPORT ArmInvalidateTlb - mov r0,#0 - mcr p15,0,r0,c8,c7,0 - mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor arra= y. R9 =3D=3D NoOp - dsb - isb - bx lr - - RVCT_ASM_EXPORT ArmReadScr - mrc p15, 0, r0, c1, c1, 0 - bx lr - - RVCT_ASM_EXPORT ArmWriteScr - mcr p15, 0, r0, c1, c1, 0 - isb - bx lr - - RVCT_ASM_EXPORT ArmReadHVBar - mrc p15, 4, r0, c12, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmWriteHVBar - mcr p15, 4, r0, c12, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmReadMVBar - mrc p15, 0, r0, c12, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmWriteMVBar - mcr p15, 0, r0, c12, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmCallWFE - wfe - bx lr - - RVCT_ASM_EXPORT ArmCallSEV - sev - bx lr - - RVCT_ASM_EXPORT ArmReadSctlr - mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control r= egister configuration data) - bx lr - - RVCT_ASM_EXPORT ArmWriteSctlr - mcr p15, 0, r0, c1, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmReadCpuActlr - mrc p15, 0, r0, c1, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmWriteCpuActlr - mcr p15, 0, r0, c1, c0, 1 - dsb - isb - bx lr - - RVCT_ASM_EXPORT ArmGetPhysicalAddressBits - mrc p15, 0, r0, c0, c1, 4 ; MMFR0 - and r0, r0, #0xf ; VMSA [3:0] - cmp r0, #5 ; >=3D 5 implies LPAE support - movlt r0, #32 ; 32 bits if no LPAE - movge r0, #40 ; 40 bits if LPAE - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupportV7.asm deleted file mode 100644 index e14f1566258c..000000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ /dev/null @@ -1,107 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - INCLUDE AsmMacroExport.inc - - -//------------------------------------------------------------------------= ------ - - RVCT_ASM_EXPORT ArmIsMpCore - mrc p15,0,R0,c0,c0,5 - // Get Multiprocessing extension (bit31) & U bit (bit30) - and R0, R0, #0xC0000000 - // if (bit31 =3D=3D 1) && (bit30 =3D=3D 0) then the processor is part of= a multiprocessor system - cmp R0, #0x80000000 - moveq R0, #1 - movne R0, #0 - bx LR - - RVCT_ASM_EXPORT ArmEnableAsynchronousAbort - cpsie a - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableAsynchronousAbort - cpsid a - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableIrq - cpsie i - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableIrq - cpsid i - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableFiq - cpsie f - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableFiq - cpsid f - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableInterrupts - cpsie if - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableInterrupts - cpsid if - isb - bx LR - - RVCT_ASM_EXPORT ArmReadIdMmfr4 - mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register - bx LR - -// UINTN -// ReadCCSIDR ( -// IN UINT32 CSSELR -// ) - RVCT_ASM_EXPORT ReadCCSIDR - mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) - isb - mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) - bx lr - -// UINT32 -// ReadCCSIDR2 ( -// IN UINT32 CSSELR -// ) - RVCT_ASM_EXPORT ReadCCSIDR2 - mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) - isb - mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2) - bx lr - -// UINT32 -// ReadCLIDR ( -// IN UINT32 CSSELR -// ) - RVCT_ASM_EXPORT ReadCLIDR - mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register - bx lr - - RVCT_ASM_EXPORT ArmReadNsacr - mrc p15, 0, r0, c1, c1, 2 - bx lr - - RVCT_ASM_EXPORT ArmWriteNsacr - mcr p15, 0, r0, c1, c1, 2 - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm b/ArmPkg/L= ibrary/ArmLib/Arm/ArmV7ArchTimerSupport.asm deleted file mode 100644 index 6896c1be2b07..000000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm +++ /dev/null @@ -1,93 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - INCLUDE AsmMacroExport.inc - PRESERVE8 - - RVCT_ASM_EXPORT ArmReadCntFrq - mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ - bx lr - - RVCT_ASM_EXPORT ArmWriteCntFrq - mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ - bx lr - - RVCT_ASM_EXPORT ArmReadCntPct - mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntkCtl - mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Regi= ster) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntkCtl - mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control = Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntpTval - mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer va= lue register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntpTval - mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical time= r value register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntpCtl - mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Con= trol Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntpCtl - mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Time= r Control Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvTval - mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value r= egister) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvTval - mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Val= ue register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvCtl - mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control = Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvCtl - mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Cont= rol Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvCt - mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntpCval - mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compa= re Value Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntpCval - mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer C= ompare Value Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvCval - mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compar= e Value Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvCval - mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer C= ompare Value Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvOff - mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvOff - mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset regi= ster) - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/Ar= mLib/Arm/ArmV7Support.asm deleted file mode 100644 index 3146c2b52181..000000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm +++ /dev/null @@ -1,292 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - INCLUDE AsmMacroExport.inc - PRESERVE8 - -DC_ON EQU ( 0x1:SHL:2 ) -IC_ON EQU ( 0x1:SHL:12 ) -CTRL_M_BIT EQU (1 << 0) -CTRL_C_BIT EQU (1 << 2) -CTRL_B_BIT EQU (1 << 7) -CTRL_I_BIT EQU (1 << 12) - - - RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line - bx lr - - RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA - mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line - bx lr - - - RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA - mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache li= ne to PoU - mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor - bx lr - - - RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA - mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU - bx lr - - - RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache= line - bx lr - - - RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line - bx lr - - - RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line - bx lr - - - RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c10, 2 ; Clean this line - bx lr - - - RVCT_ASM_EXPORT ArmInvalidateInstructionCache - mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableMmu - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableMmu - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - - mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB - mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predi= ctor array - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableCachesAndMmu - mrc p15, 0, r0, c1, c0, 0 ; Get control register - bic r0, r0, #CTRL_M_BIT ; Disable MMU - bic r0, r0, #CTRL_C_BIT ; Disable D Cache - bic r0, r0, #CTRL_I_BIT ; Disable I Cache - mcr p15, 0, r0, c1, c0, 0 ; Write control register - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmMmuEnabled - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - and R0,R0,#1 - bx LR - - RVCT_ASM_EXPORT ArmEnableDataCache - ldr R1,=3DDC_ON ; Specify SCTLR.C bit : (Data) Cache ena= ble bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified cache= s enabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableDataCache - ldr R1,=3DDC_ON ; Specify SCTLR.C bit : (Data) Cache ena= ble bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified cac= hes disabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableInstructionCache - ldr R1,=3DIC_ON ; Specify SCTLR.I bit : Instruction cach= e enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches ena= bled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableInstructionCache - ldr R1,=3DIC_ON ; Specify SCTLR.I bit : Instruction cach= e enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control registe= r configuration data) - BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches d= isabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableSWPInstruction - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x00000400 - mcr p15, 0, r0, c1, c0, 0 - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableBranchPrediction - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control registe= r configuration data) - orr r0, r0, #0x00000800 ; - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableBranchPrediction - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control registe= r configuration data) - bic r0, r0, #0x00000800 ; - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmSetLowVectors - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control registe= r configuration data) - bic r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - isb - bx LR - - RVCT_ASM_EXPORT ArmSetHighVectors - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control registe= r configuration data) - orr r0, r0, #0x00002000 ; Set V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - isb - bx LR - - RVCT_ASM_EXPORT ArmV7AllDataCachesOperation - stmfd SP!,{r4-r12, LR} - mov R1, R0 ; Save Function call in R1 - mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR - ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) - mov R3, R3, LSR #23 ; Cache level value (naturally aligned) - beq Finished - mov R10, #0 - -Loop1 - add R2, R10, R10, LSR #1 ; Work out 3xcachelevel - mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for thi= s level - and R12, R12, #7 ; get those 3 bits alone - cmp R12, #2 - blt Skip ; no cache or only instruction cache at th= is level - mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register = (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeI= D reg - mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CC= SIDR) - and R2, R12, #&7 ; extract the line length field - add R2, R2, #4 ; add 4 for the line length offset (log2 1= 6 bytes) - ldr R4, =3D0x3FF - ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (ri= ght aligned) - clz R5, R4 ; R5 is the bit position of the way size i= ncrement - ldr R7, =3D0x00007FFF - ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (= right aligned) - -Loop2 - mov R9, R4 ; R9 working copy of the max way size (rig= ht aligned) - -Loop3 - orr R0, R10, R9, LSL R5 ; factor in the way number and cache numbe= r into R11 - orr R0, R0, R7, LSL R2 ; factor in the index number - - blx R1 - - subs R9, R9, #1 ; decrement the way number - bge Loop3 - subs R7, R7, #1 ; decrement the index - bge Loop2 -Skip - add R10, R10, #2 ; increment the cache number - cmp R3, R10 - bgt Loop1 - -Finished - dsb - ldmfd SP!, {r4-r12, lr} - bx LR - - RVCT_ASM_EXPORT ArmDataMemoryBarrier - dmb - bx LR - - RVCT_ASM_EXPORT ArmDataSynchronizationBarrier - dsb - bx LR - - RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier - isb - bx LR - - RVCT_ASM_EXPORT ArmReadVBar - // Set the Address of the Vector Table in the VBAR register - mrc p15, 0, r0, c12, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmWriteVBar - // Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 - // Ensure the SCTLR.V bit is clear - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control registe= r configuration data) - bic r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control regis= ter configuration data) - isb - bx lr - - RVCT_ASM_EXPORT ArmEnableVFP - // Read CPACR (Coprocessor Access Control Register) - mrc p15, 0, r0, c1, c0, 2 - // Enable VPF access (Full Access to CP10, CP11) (V* instructions) - orr r0, r0, #0x00f00000 - // Write back CPACR (Coprocessor Access Control Register) - mcr p15, 0, r0, c1, c0, 2 - isb - // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled= and operate normally. - mov r0, #0x40000000 - mcr p10,#0x7,r0,c8,c0,#0 - bx lr - - RVCT_ASM_EXPORT ArmCallWFI - wfi - bx lr - -//Note: Return 0 in Uniprocessor implementation - RVCT_ASM_EXPORT ArmReadCbar - mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Regist= er - bx lr - - RVCT_ASM_EXPORT ArmReadMpidr - mrc p15, 0, r0, c0, c0, 5 ; read MPIDR - bx lr - - RVCT_ASM_EXPORT ArmReadTpidrurw - mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW - bx lr - - RVCT_ASM_EXPORT ArmWriteTpidrurw - mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW - bx lr - - RVCT_ASM_EXPORT ArmIsArchTimerImplemented - mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 - and r0, r0, #0x000F0000 - bx lr - - RVCT_ASM_EXPORT ArmReadIdPfr1 - mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/A= rmBaseLib.inf index f61c71b673d1..e37d85bee471 100644 --- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf +++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf @@ -30,11 +30,6 @@ Arm/ArmV7Support.S | GCC Arm/ArmV7ArchTimerSupport.S | GCC =20 - Arm/ArmLibSupport.asm | RVCT - Arm/ArmLibSupportV7.asm | RVCT - Arm/ArmV7Support.asm | RVCT - Arm/ArmV7ArchTimerSupport.asm | RVCT - [Sources.AARCH64] AArch64/AArch64Lib.h AArch64/AArch64Lib.c diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibV7Support.asm b/ArmPkg/L= ibrary/ArmMmuLib/Arm/ArmMmuLibV7Support.asm deleted file mode 100644 index a65e95db5735..000000000000 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibV7Support.asm +++ /dev/null @@ -1,26 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2016, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - INCLUDE AsmMacroExport.inc - - -//------------------------------------------------------------------------= ------ - - RVCT_ASM_EXPORT ArmHasMpExtensions - mrc p15,0,R0,c0,c0,5 - // Get Multiprocessing extension (bit31) - lsr R0, R0, #31 - bx LR - - RVCT_ASM_EXPORT ArmReadIdMmfr0 - mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register - bx lr - - END diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index 2a7e7147958c..3d78e7dabf47 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -27,7 +27,6 @@ Arm/ArmMmuLibCore.c Arm/ArmMmuLibUpdate.c Arm/ArmMmuLibV7Support.S |GCC - Arm/ArmMmuLibV7Support.asm |RVCT =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm b/ArmPkg/Library/ArmSm= cLib/Arm/ArmSmc.asm deleted file mode 100644 index d14573c9cc6c..000000000000 --- a/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm +++ /dev/null @@ -1,45 +0,0 @@ -// -// Copyright (c) 2012-2014, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - - - INCLUDE AsmMacroExport.inc - - RVCT_ASM_EXPORT ArmCallSmc - push {r4-r8} - // r0 will be popped just after the SMC call - push {r0} - - // Load the SMC arguments values into the appropriate registers - ldr r7, [r0, #28] - ldr r6, [r0, #24] - ldr r5, [r0, #20] - ldr r4, [r0, #16] - ldr r3, [r0, #12] - ldr r2, [r0, #8] - ldr r1, [r0, #4] - ldr r0, [r0, #0] - - smc #0 - - // Pop the ARM_SMC_ARGS structure address from the stack into r8 - pop {r8} - - // Load the SMC returned values into the appropriate registers - // A SMC call can return up to 4 values - we do not need to store back= r4-r7. - str r3, [r8, #12] - str r2, [r8, #8] - str r1, [r8, #4] - str r0, [r8, #0] - - mov r0, r8 - - // Restore the registers r4-r8 - pop {r4-r8} - - bx lr - - END diff --git a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf b/ArmPkg/Library/ArmSmc= Lib/ArmSmcLib.inf index a89f9203fb7e..6ce0ea4caf47 100644 --- a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf +++ b/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf @@ -14,7 +14,6 @@ LIBRARY_CLASS =3D ArmSmcLib =20 [Sources.ARM] - Arm/ArmSmc.asm | RVCT Arm/ArmSmc.S | GCC =20 [Sources.AARCH64] @@ -26,6 +25,3 @@ [Packages] MdePkg/MdePkg.dec ArmPkg/ArmPkg.dec - -[BuildOptions] - RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu 7-A.security diff --git a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm b/ArmPkg/Library/ArmSv= cLib/Arm/ArmSvc.asm deleted file mode 100644 index d1751488b2b1..000000000000 --- a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm +++ /dev/null @@ -1,36 +0,0 @@ -// -// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - - - INCLUDE AsmMacroExport.inc - - RVCT_ASM_EXPORT ArmCallSvc - // r0 will be popped just after the SVC call - push {r0, r4-r8} - - // Load the SVC arguments values into the appropriate registers - ldm r0, {r0-r7} - - svc #0 - // Prevent speculative execution beyond svc instruction - dsb nsh - isb - - // Load the ARM_SVC_ARGS structure address from the stack into r8 - ldr r8, [sp] - - // Load the SVC returned values into the appropriate registers - // A SVC call can return up to 4 values - we do not need to store back= r4-r7. - stm r8, {r0-r3} - - mov r0, r8 - - // Restore the registers r4-r8 - pop {r1, r4-r8} - bx lr - - END diff --git a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf b/ArmPkg/Library/ArmSvc= Lib/ArmSvcLib.inf index 744a29fbf723..ecfbc5d64a28 100644 --- a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf +++ b/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf @@ -14,7 +14,6 @@ LIBRARY_CLASS =3D ArmSvcLib =20 [Sources.ARM] - Arm/ArmSvc.asm | RVCT Arm/ArmSvc.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm b/ArmPkg/Lib= rary/CompilerIntrinsicsLib/Arm/lasr.asm deleted file mode 100644 index c388d7e27b49..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm +++ /dev/null @@ -1,34 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - INCLUDE AsmMacroExport.inc - -; -;UINT32 -;EFIAPI -;__aeabi_lasr ( -; IN UINT32 Dividen -; IN UINT32 Divisor -; ); -; - RVCT_ASM_EXPORT __aeabi_lasr - SUBS r3,r2,#0x20 - BPL {pc} + 0x18 ; 0x1c - RSB r3,r2,#0x20 - LSR r0,r0,r2 - ORR r0,r0,r1,LSL r3 - ASR r1,r1,r2 - BX lr - ASR r0,r1,r3 - ASR r1,r1,#31 - BX lr - - END - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm b/ArmPkg/Lib= rary/CompilerIntrinsicsLib/Arm/llsl.asm deleted file mode 100644 index d8ff6cafd342..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm +++ /dev/null @@ -1,36 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - INCLUDE AsmMacroExport.inc - -; -;VOID -;EFIAPI -;__aeabi_llsl ( -; IN VOID *Destination, -; IN VOID *Source, -; IN UINT32 Size -; ); -; - - RVCT_ASM_EXPORT __aeabi_llsl - SUBS r3,r2,#0x20 - BPL {pc} + 0x18 ; 0x1c - RSB r3,r2,#0x20 - LSL r1,r1,r2 - ORR r1,r1,r0,LSR r3 - LSL r0,r0,r2 - BX lr - LSL r1,r0,r3 - MOV r0,#0 - BX lr - - END - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm b/ArmPkg/= Library/CompilerIntrinsicsLib/Arm/memmove.asm deleted file mode 100644 index 939b46aeefd3..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm +++ /dev/null @@ -1,46 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2011-2014, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - INCLUDE AsmMacroExport.inc - -; -;VOID -;EFIAPI -;__aeabi_memmove ( -; IN VOID *Destination, -; IN CONST VOID *Source, -; IN UINT32 Size -; ); -; - RVCT_ASM_EXPORT __aeabi_memmove - CMP r2, #0 - BXEQ lr - CMP r0, r1 - BXEQ lr - BHI memmove_backward - -memmove_forward - LDRB r3, [r1], #1 - STRB r3, [r0], #1 - SUBS r2, r2, #1 - BNE memmove_forward - BX lr - -memmove_backward - add r0, r2 - add r1, r2 -memmove_backward_loop - LDRB r3, [r1, #-1]! - STRB r3, [r0, #-1]! - SUBS r2, r2, #1 - BNE memmove_backward_loop - BX lr - - END diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm b/ArmPkg/Li= brary/CompilerIntrinsicsLib/Arm/mullu.asm deleted file mode 100644 index 8ff0c066925d..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm +++ /dev/null @@ -1,43 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - EXPORT __ARM_ll_mullu - EXPORT __aeabi_lmul - - AREA Math, CODE, READONLY - -; -;INT64 -;EFIAPI -;__aeabi_lmul ( -; IN INT64 Multiplicand -; IN INT32 Multiplier -; ); -; -__ARM_ll_mullu - mov r3, #0 -// Make upper part of INT64 Multiplier 0 and use __aeabi_lmul - -; -;INT64 -;EFIAPI -;__aeabi_lmul ( -; IN INT64 Multiplicand -; IN INT64 Multiplier -; ); -; -__aeabi_lmul - stmdb sp!, {lr} - mov lr, r0 - umull r0, ip, r2, lr - mla r1, r2, r1, ip - mla r1, r3, lr, r1 - ldmia sp!, {pc} - - END diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm b/ArmPkg/L= ibrary/CompilerIntrinsicsLib/Arm/switch.asm deleted file mode 100644 index c8e8afef32ad..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm +++ /dev/null @@ -1,22 +0,0 @@ -///-----------------------------------------------------------------------= ------- -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - - INCLUDE AsmMacroExport.inc - - RVCT_ASM_EXPORT __ARM_switch8 - LDRB r12,[lr,#-1] - CMP r3,r12 - LDRBCC r3,[lr,r3] - LDRBCS r3,[lr,r12] - ADD r12,lr,r3,LSL #1 - BX r12 - - END diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm b/ArmPkg/Li= brary/CompilerIntrinsicsLib/Arm/uread.asm deleted file mode 100644 index 82aab976ac82..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm +++ /dev/null @@ -1,58 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - - INCLUDE AsmMacroExport.inc - -; -;UINT32 -;EFIAPI -;__aeabi_uread4 ( -; IN VOID *Pointer -; ); -; - RVCT_ASM_EXPORT __aeabi_uread4 - ldrb r1, [r0] - ldrb r2, [r0, #1] - ldrb r3, [r0, #2] - ldrb r0, [r0, #3] - orr r1, r1, r2, lsl #8 - orr r1, r1, r3, lsl #16 - orr r0, r1, r0, lsl #24 - bx lr - -; -;UINT64 -;EFIAPI -;__aeabi_uread8 ( -; IN VOID *Pointer -; ); -; - RVCT_ASM_EXPORT __aeabi_uread8 - mov r3, r0 - - ldrb r1, [r3] - ldrb r2, [r3, #1] - orr r1, r1, r2, lsl #8 - ldrb r2, [r3, #2] - orr r1, r1, r2, lsl #16 - ldrb r0, [r3, #3] - orr r0, r1, r0, lsl #24 - - ldrb r1, [r3, #4] - ldrb r2, [r3, #5] - orr r1, r1, r2, lsl #8 - ldrb r2, [r3, #6] - orr r1, r1, r2, lsl #16 - ldrb r2, [r3, #7] - orr r1, r1, r2, lsl #24 - - bx lr - END diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm b/ArmPkg/L= ibrary/CompilerIntrinsicsLib/Arm/uwrite.asm deleted file mode 100644 index d433d9987eb5..000000000000 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm +++ /dev/null @@ -1,60 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - - - - INCLUDE AsmMacroExport.inc - -; -;UINT32 -;EFIAPI -;__aeabi_uwrite4 ( -; IN UINT32 Data, -; IN VOID *Pointer -; ); -; -; - RVCT_ASM_EXPORT __aeabi_uwrite4 - mov r2, r0, lsr #8 - strb r0, [r1] - strb r2, [r1, #1] - mov r2, r0, lsr #16 - strb r2, [r1, #2] - mov r2, r0, lsr #24 - strb r2, [r1, #3] - bx lr - -; -;UINT64 -;EFIAPI -;__aeabi_uwrite8 ( -; IN UINT64 Data, //r0-r1 -; IN VOID *Pointer //r2 -; ); -; -; - RVCT_ASM_EXPORT __aeabi_uwrite8 - mov r3, r0, lsr #8 - strb r0, [r2] - strb r3, [r2, #1] - mov r3, r0, lsr #16 - strb r3, [r2, #2] - mov r3, r0, lsr #24 - strb r3, [r2, #3] - - mov r3, r1, lsr #8 - strb r1, [r2, #4] - strb r3, [r2, #5] - mov r3, r1, lsr #16 - strb r3, [r2, #6] - mov r3, r1, lsr #24 - strb r3, [r2, #7] - bx lr - - END - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf= b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf index fcf48c678119..7e22e6f67bff 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf +++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf @@ -18,9 +18,6 @@ LIBRARY_CLASS =3D CompilerIntrinsicsLib =20 [Sources] - memcpy.c | RVCT - memset.c | RVCT - memcpy.c | GCC memset.c | GCC =20 @@ -30,18 +27,6 @@ memmove_ms.c | MSFT =20 [Sources.ARM] - Arm/mullu.asm | RVCT - Arm/switch.asm | RVCT - Arm/llsr.asm | RVCT - Arm/memmove.asm | RVCT - Arm/uread.asm | RVCT - Arm/uwrite.asm | RVCT - Arm/lasr.asm | RVCT - Arm/llsl.asm | RVCT - Arm/div.asm | RVCT - Arm/uldiv.asm | RVCT - Arm/ldivmod.asm | RVCT - Arm/ashrdi3.S | GCC Arm/ashldi3.S | GCC Arm/div.S | GCC --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89487): https://edk2.groups.io/g/devel/message/89487 Mute This Topic: https://groups.io/mt/90866283/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89488+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89488+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603723; cv=none; d=zohomail.com; s=zohoarc; b=V7FbgyY5njuJhZ2VBwm5LceOqnWkYYPqEMPHR2dNEuPLxSN+IkqPl+GKwokAogMf0i8enEQh1+BsLrtOsGcZNxLJKzHWtNZsgu1nXTgXLsHD7VW1aTRhW3dmRbQuU/LC8EKkbNMQp6RwP84Pj49sA68DlFYFuQLBrij4YYXtOqk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603723; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YmeAVXknuJMpNQ/EoXH2GJDTGoCZ2cKAmwTyioQPfuQ=; b=hs7kX66x1GfE8o6CYcU6u7h1WO/cKsS72fMQ+CJXilIcOXrLaiVYJGSDnJhX9Jr9aX6rb5503hn6vCvTzxPaYWIJC4kqyptmkMAR7Fn2kUk4Dnp55ZUQ91k/qaaIBdEGQgcLR0m47uoEfXaWSpknuROkiD61vK3NoysVZcJeh0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89488+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603723802201.62955593976642; Tue, 3 May 2022 11:48:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pb6DYY1788612xgg4crmEqEw; Tue, 03 May 2022 11:48:43 -0700 X-Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web08.1014.1651603719238416815 for ; Tue, 03 May 2022 11:48:42 -0700 X-Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 03 May 2022 11:48:42 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:41 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:40 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:39 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 02/10] ArmPlatformPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:12 -0600 Message-ID: <20220503184820.19312-3-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: iIjCG5GJ2Ifno04uq36P1BUhx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603723; bh=EDoEumMCdWCuGB3pXbXUZ9E79n1ER4fHhFj6ofIdZos=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=isg67ZmBBowDoRAj11HoJS0i+TRxP34LN/9rTk2ycRqD6ik32Yb2PPeJ0eUa0gLRm7T IQL2t/vw/U24M/gqVkKKQVhlZXVezBp/PUfPARS4OqnsEXVbaEUgc6dNZ4ixBQglGHLb9 5g1yKKV+IR0B/4KkR2ApcWW4zvmgJo5RXgE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603725316100009 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- ArmPlatformPkg/Library/ArmPlatformLibNull/Arm/ArmPlatformHelper.asm | = 62 --------- ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf | = 1 - ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.asm | 1= 18 ---------------- ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf | = 1 - ArmPlatformPkg/PrePeiCore/Arm/Exception.asm | = 83 ------------ ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm | = 89 ------------ ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.asm | = 32 ----- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | = 3 - ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | = 3 - ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.asm | 1= 42 -------------------- ArmPlatformPkg/PrePi/PeiMPCore.inf | = 1 - ArmPlatformPkg/PrePi/PeiUniCore.inf | = 1 - ArmPlatformPkg/Scripts/Makefile | = 5 +- 13 files changed, 1 insertion(+), 540 deletions(-) diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/Arm/ArmPlatformHelpe= r.asm b/ArmPlatformPkg/Library/ArmPlatformLibNull/Arm/ArmPlatformHelper.asm deleted file mode 100644 index 1c305f8b507e..000000000000 --- a/ArmPlatformPkg/Library/ArmPlatformLibNull/Arm/ArmPlatformHelper.asm +++ /dev/null @@ -1,62 +0,0 @@ -// -// Copyright (c) 2012-2013, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -#include - - INCLUDE AsmMacroIoLib.inc - - EXPORT ArmPlatformPeiBootAction - EXPORT ArmPlatformGetCorePosition - EXPORT ArmPlatformGetPrimaryCoreMpId - EXPORT ArmPlatformIsPrimaryCore - - IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore - IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask - - PRESERVE8 - AREA ArmPlatformNullHelper, CODE, READONLY - -ArmPlatformPeiBootAction FUNCTION - bx lr - ENDFUNC - -//UINTN -//ArmPlatformGetCorePosition ( -// IN UINTN MpId -// ); -ArmPlatformGetCorePosition FUNCTION - and r1, r0, #ARM_CORE_MASK - and r0, r0, #ARM_CLUSTER_MASK - add r0, r1, r0, LSR #7 - bx lr - ENDFUNC - -//UINTN -//ArmPlatformGetPrimaryCoreMpId ( -// VOID -// ); -ArmPlatformGetPrimaryCoreMpId FUNCTION - mov32 r0, FixedPcdGet32(PcdArmPrimaryCore) - bx lr - ENDFUNC - -//UINTN -//ArmPlatformIsPrimaryCore ( -// IN UINTN MpId -// ); -ArmPlatformIsPrimaryCore FUNCTION - mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask) - and r0, r0, r1 - mov32 r1, FixedPcdGet32(PcdArmPrimaryCore) - cmp r0, r1 - moveq r0, #1 - movne r0, #0 - bx lr - ENDFUNC - - END - diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.i= nf b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf index e0d0028d8224..4a1cd97e3553 100644 --- a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf +++ b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf @@ -29,7 +29,6 @@ =20 [Sources.Arm] Arm/ArmPlatformHelper.S | GCC - Arm/ArmPlatformHelper.asm | RVCT =20 [Sources.AArch64] AArch64/ArmPlatformHelper.S diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStac= kLib.asm b/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackL= ib.asm deleted file mode 100644 index 2c346146d09c..000000000000 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.asm +++ /dev/null @@ -1,118 +0,0 @@ -// -// Copyright (c) 2012-2013, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -#include - - INCLUDE AsmMacroIoLib.inc - - EXPORT ArmPlatformStackSet - EXPORT ArmPlatformStackSetPrimary - EXPORT ArmPlatformStackSetSecondary - - IMPORT ArmPlatformIsPrimaryCore - IMPORT ArmPlatformGetCorePosition - IMPORT ArmPlatformGetPrimaryCoreMpId - - IMPORT _gPcd_FixedAtBuild_PcdCoreCount - - PRESERVE8 - AREA ArmPlatformStackLib, CODE, READONLY - -//VOID -//ArmPlatformStackSet ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ArmPlatformStackSet FUNCTION - // Save parameters - mov r6, r3 - mov r5, r2 - mov r4, r1 - mov r3, r0 - - // Save the Link register - mov r7, lr - - // Identify Stack - mov r0, r1 - bl ArmPlatformIsPrimaryCore - cmp r0, #1 - - // Restore parameters - mov r0, r3 - mov r1, r4 - mov r2, r5 - mov r3, r6 - - // Restore the Link register - mov lr, r7 - - beq ArmPlatformStackSetPrimary - bne ArmPlatformStackSetSecondary - ENDFUNC - -//VOID -//ArmPlatformStackSetPrimary ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ArmPlatformStackSetPrimary FUNCTION - mov r4, lr - - // Add stack of primary stack to StackBase - add r0, r0, r2 - - // Compute SecondaryCoresCount * SecondaryCoreStackSize - mov32 r1, FixedPcdGet32 (PcdCoreCount) - sub r1, #1 - mul r3, r3, r1 - - // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCo= unt * SecondaryCoreStackSize)) - add sp, r0, r3 - - bx r4 - ENDFUNC - -//VOID -//ArmPlatformStackSetSecondary ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ArmPlatformStackSetSecondary FUNCTION - mov r4, lr - mov sp, r0 - - // Get Core Position - mov r0, r1 - bl ArmPlatformGetCorePosition - mov r5, r0 - - // Get Primary Core Position - bl ArmPlatformGetPrimaryCoreMpId - bl ArmPlatformGetCorePosition - - // Get Secondary Core Position. We should get consecutive secondary stac= k number from 1...(CoreCount-1) - cmp r5, r0 - subhi r5, r5, #1 - add r5, r5, #1 - - // Compute top of the secondary stack - mul r3, r3, r5 - - // Set stack - add sp, sp, r3 - - bx r4 - ENDFUNC - - END diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib= .inf b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf index 76f809c80d9f..dfa0e7b9e786 100644 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf +++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf @@ -21,7 +21,6 @@ ArmPlatformPkg/ArmPlatformPkg.dec =20 [Sources.ARM] - Arm/ArmPlatformStackLib.asm | RVCT Arm/ArmPlatformStackLib.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/PrePeiCore/Arm/Exception.asm b/ArmPlatformPkg/P= rePeiCore/Arm/Exception.asm deleted file mode 100644 index 28d625e67af4..000000000000 --- a/ArmPlatformPkg/PrePeiCore/Arm/Exception.asm +++ /dev/null @@ -1,83 +0,0 @@ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -#include - - IMPORT PeiCommonExceptionEntry - EXPORT PeiVectorTable - - PRESERVE8 - AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=3D5 - -//=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -//Default Exception Handlers -//=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - - -PeiVectorTable - b _DefaultResetHandler - b _DefaultUndefined - b _DefaultSWI - b _DefaultPrefetchAbort - b _DefaultDataAbort - b _DefaultReserved - b _DefaultIrq - b _DefaultFiq - -// -// Default Exception handlers: There is no plan to return from any of thes= e exceptions. -// No context saving at all. -// -_DefaultResetHandler - mov r1, lr - cps #0x13 ; Switch to SVC for common stack - mov r0, #0 - blx PeiCommonExceptionEntry - -_DefaultUndefined - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #1 - blx PeiCommonExceptionEntry - -_DefaultSWI - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #2 - blx PeiCommonExceptionEntry - -_DefaultPrefetchAbort - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #3 - blx PeiCommonExceptionEntry - -_DefaultDataAbort - sub r1, LR, #8 - cps #0x13 ; Switch to SVC for common stack - mov r0, #4 - blx PeiCommonExceptionEntry - -_DefaultReserved - mov r1, lr - cps #0x13 ; Switch to SVC for common stack - mov r0, #5 - blx PeiCommonExceptionEntry - -_DefaultIrq - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #6 - blx PeiCommonExceptionEntry - -_DefaultFiq - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #7 - blx PeiCommonExceptionEntry - - END diff --git a/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm b/ArmPl= atformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm deleted file mode 100644 index 2734b0951a09..000000000000 --- a/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm +++ /dev/null @@ -1,89 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -#include - - INCLUDE AsmMacroIoLib.inc - - IMPORT CEntryPoint - IMPORT ArmPlatformGetCorePosition - IMPORT ArmPlatformIsPrimaryCore - IMPORT ArmReadMpidr - IMPORT ArmPlatformPeiBootAction - EXPORT _ModuleEntryPoint - - PRESERVE8 - AREA PrePeiCoreEntryPoint, CODE, READONLY - -StartupAddr DCD CEntryPoint - -_ModuleEntryPoint - // Do early platform specific actions - bl ArmPlatformPeiBootAction - - // Identify CPU ID - bl ArmReadMpidr - // Keep a copy of the MpId register value - mov r5, r0 - - // Is it the Primary Core ? - bl ArmPlatformIsPrimaryCore - - // Get the top of the primary stacks (and the base of the secondary stac= ks) - mov32 r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCore= PrimaryStackSize) - - // r0 is equal to 1 if I am the primary core - cmp r0, #1 - beq _SetupPrimaryCoreStack - -_SetupSecondaryCoreStack - // r1 contains the base of the secondary stacks - - // Get the Core Position - mov r6, r1 // Save base of the secondary stacks - mov r0, r5 - bl ArmPlatformGetCorePosition - // The stack starts at the top of the stack region. Add '1' to the Core = Position to get the top of the stack - add r0, r0, #1 - - // StackOffset =3D CorePos * StackSize - mov32 r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize) - mul r0, r0, r2 - // SP =3D StackBase + StackOffset - add sp, r6, r0 - -_PrepareArguments - // The PEI Core Entry Point has been computed by GenFV and stored in the= second entry of the Reset Vector - mov32 r2, FixedPcdGet32(PcdFvBaseAddress) - ldr r1, [r2, #4] - - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped ali= as) - ldr r3, StartupAddr - - // Jump to PrePeiCore C code - // r0 =3D mp_id - // r1 =3D pei_core_address - mov r0, r5 - blx r3 - -_SetupPrimaryCoreStack - mov sp, r1 - mov32 r8, FixedPcdGet64 (PcdCPUCoresStackBase) - mov32 r9, FixedPcdGet32 (PcdInitValueInTempStack) - mov r10, r9 - mov r11, r9 - mov r12, r9 -0:stm r8!, {r9-r12} - cmp r8, r1 - blt 0b - b _PrepareArguments - -_NeverReturn - b _NeverReturn - - END diff --git a/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.asm b/ArmPlatformPkg= /PrePeiCore/Arm/SwitchStack.asm deleted file mode 100644 index 65f64805a04a..000000000000 --- a/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.asm +++ /dev/null @@ -1,32 +0,0 @@ -;-------------------------------------------------------------------------= ----- -; -; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;-------------------------------------------------------------------------= ----- - - EXPORT SecSwitchStack - - AREA Switch_Stack, CODE, READONLY - -;/** -; This allows the caller to switch the stack and return -; -; @param StackDelta Signed amount by which to modify the stack po= inter -; -; @return Nothing. Goes to the Entry Point passing in the new paramete= rs -; -;**/ -;VOID -;EFIAPI -;SecSwitchStack ( -; VOID *StackDelta -; ); -; -SecSwitchStack - MOV R1, SP - ADD R1, R0, R1 - MOV SP, R1 - BX LR - END diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPk= g/PrePeiCore/PrePeiCoreMPCore.inf index fb01dd1a113e..a5b4722459d1 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -21,11 +21,8 @@ =20 [Sources.ARM] Arm/ArchPrePeiCore.c - Arm/PrePeiCoreEntryPoint.asm | RVCT Arm/PrePeiCoreEntryPoint.S | GCC - Arm/SwitchStack.asm | RVCT Arm/SwitchStack.S | GCC - Arm/Exception.asm | RVCT Arm/Exception.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformP= kg/PrePeiCore/PrePeiCoreUniCore.inf index e9eb092d3ac9..466a2b01c384 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -21,11 +21,8 @@ =20 [Sources.ARM] Arm/ArchPrePeiCore.c - Arm/PrePeiCoreEntryPoint.asm | RVCT Arm/PrePeiCoreEntryPoint.S | GCC - Arm/SwitchStack.asm | RVCT Arm/SwitchStack.S | GCC - Arm/Exception.asm | RVCT Arm/Exception.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.asm b/ArmPlatformPkg= /PrePi/Arm/ModuleEntryPoint.asm deleted file mode 100644 index eaba90cc3d7c..000000000000 --- a/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.asm +++ /dev/null @@ -1,142 +0,0 @@ -// -// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// - -#include -#include - - INCLUDE AsmMacroIoLib.inc - - IMPORT CEntryPoint - IMPORT ArmPlatformIsPrimaryCore - IMPORT ArmReadMpidr - IMPORT ArmPlatformPeiBootAction - IMPORT ArmPlatformStackSet - IMPORT mSystemMemoryEnd - - EXPORT _ModuleEntryPoint - - PRESERVE8 - AREA PrePiCoreEntryPoint, CODE, READONLY - -StartupAddr DCD CEntryPoint - -_ModuleEntryPoint - // Do early platform specific actions - bl ArmPlatformPeiBootAction - - // Get ID of this CPU in multi-core system - bl ArmReadMpidr - // Keep a copy of the MpId register value - mov r8, r0 - -_SetSVCMode - // Enter SVC mode, Disable FIQ and IRQ - mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ) - msr CPSR_c, r1 - -// Check if we can install the stack at the top of the System Memory or if= we need -// to install the stacks at the bottom of the Firmware Device (case the FD= is located -// at the top of the DRAM) -_SystemMemoryEndInit - adrll r1, mSystemMemoryEnd - ldrd r2, r3, [r1] - teq r3, #0 - moveq r1, r2 - mvnne r1, #0 - -_SetupStackPosition - // r1 =3D SystemMemoryTop - - // Calculate Top of the Firmware Device - mov32 r2, FixedPcdGet32(PcdFdBaseAddress) - mov32 r3, FixedPcdGet32(PcdFdSize) - sub r3, r3, #1 - add r3, r3, r2 // r3 =3D FdTop =3D PcdFdBaseAddress + PcdFdSize - - // UEFI Memory Size (stacks are allocated in this region) - mov32 r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize) - - // - // Reserve the memory for the UEFI region (contain stacks on its top) - // - - // Calculate how much space there is between the top of the Firmware and= the Top of the System Memory - subs r0, r1, r3 // r0 =3D SystemMemoryTop - FdTop - bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Cas= e when the PrePi is in XIP memory outside of the DRAM - cmp r0, r4 - bge _SetupStack - - // Case the top of stacks is the FdBaseAddress - mov r1, r2 - -_SetupStack - // r1 contains the top of the stack (and the UEFI Memory) - - // Because the 'push' instruction is equivalent to 'stmdb' (decrement be= fore), we need to increment - // one to the top of the stack. We check if incrementing one does not ov= erflow (case of DRAM at the - // top of the memory space) - adds r9, r1, #1 - bcs _SetupOverflowStack - -_SetupAlignedStack - mov r1, r9 - b _GetBaseUefiMemory - -_SetupOverflowStack - // Case memory at the top of the address space. Ensure the top of the st= ack is EFI_PAGE_SIZE - // aligned (4KB) - mov32 r9, EFI_PAGE_MASK - and r9, r9, r1 - sub r1, r1, r9 - -_GetBaseUefiMemory - // Calculate the Base of the UEFI Memory - sub r9, r1, r4 - -_GetStackBase - // r1 =3D The top of the Mpcore Stacks - // Stack for the primary core =3D PrimaryCoreStack - mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize) - sub r10, r1, r2 - - // Stack for the secondary core =3D Number of Cores - 1 - mov32 r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSe= condaryStackSize) - sub r10, r10, r1 - - // r10 =3D The base of the MpCore Stacks (primary stack & secondary stac= ks) - mov r0, r10 - mov r1, r8 - //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackS= ize) - mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize) - mov32 r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize) - bl ArmPlatformStackSet - - // Is it the Primary Core ? - mov r0, r8 - bl ArmPlatformIsPrimaryCore - cmp r0, #1 - bne _PrepareArguments - -_PrepareArguments - mov r0, r8 - mov r1, r9 - mov r2, r10 - - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped ali= as) - ldr r4, StartupAddr - - // Jump to PrePiCore C code - // r0 =3D MpId - // r1 =3D UefiMemoryBase - // r2 =3D StacksBase - blx r4 - -_NeverReturn - b _NeverReturn - - END diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiM= PCore.inf index 053f9fd9e616..a613b24c340e 100644 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -22,7 +22,6 @@ [Sources.ARM] Arm/ArchPrePi.c Arm/ModuleEntryPoint.S | GCC - Arm/ModuleEntryPoint.asm | RVCT =20 [Sources.AArch64] AArch64/ArchPrePi.c diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/Pei= UniCore.inf index 83a3df78ac26..b62ea3c485bd 100644 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -23,7 +23,6 @@ [Sources.ARM] Arm/ArchPrePi.c Arm/ModuleEntryPoint.S | GCC - Arm/ModuleEntryPoint.asm | RVCT =20 [Sources.AArch64] AArch64/ArchPrePi.c diff --git a/ArmPlatformPkg/Scripts/Makefile b/ArmPlatformPkg/Scripts/Makef= ile index 270fc80b6ae8..baa618456413 100644 --- a/ArmPlatformPkg/Scripts/Makefile +++ b/ArmPlatformPkg/Scripts/Makefile @@ -5,10 +5,7 @@ # #*/ =20 -# Define the following variable to specify an alternative toolchain to the= one located in your PATH: -# - RVCT_TOOLS_PATH: for RVCT and RVCTLINUX toolchains - -EDK2_TOOLCHAIN ?=3D RVCTLINUX +EDK2_TOOLCHAIN ?=3D GCC5 EDK2_ARCH ?=3D ARM EDK2_BUILD ?=3D DEBUG =20 --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89488): https://edk2.groups.io/g/devel/message/89488 Mute This Topic: https://groups.io/mt/90866284/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89489+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89489+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603724; cv=none; d=zohomail.com; s=zohoarc; b=MfoCDrL/g1pe5uAfUzXk3uJD+Ps4fJIfRrAAccxs1ZBbnF1UOSSIlqZn1vBhQHrPx4L08v3r38/dhBUT0rDa0ixNCNRzDUMc3h9LAgx/lvfrA002UPa37WoLWcx/Yz0Bwcu79s12fd9XrzZ+EuRuVLizKdODf+Qaflyu6IBVaYU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603724; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3YOWFB4uUEYsCc5En07dJ9Jkzv0X+d69aRF0m8sevqE=; b=alhVdYOrdnyoWvDj45jxhssn7u6C5io3DHewfUdI5pxXpzhL3hCwRj9OAPQNCyyqxuOCDh8tb0YLAT9wpFnVzZ2DZbpdNOVhY0EGBXSBuO0ZVlJcWD3ZWvB/Xh/mRrhAmLbCvG041sx/5QBNt+300WeDDEpBT+IF3lyrAx935zA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89489+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603724989688.6760564633028; Tue, 3 May 2022 11:48:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qFUPYY1788612xwsdediZMbU; Tue, 03 May 2022 11:48:44 -0700 X-Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by mx.groups.io with SMTP id smtpd.web08.1015.1651603723967357143 for ; Tue, 03 May 2022 11:48:44 -0700 X-Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 03 May 2022 11:48:43 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:42 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:42 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:40 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 03/10] CryptoPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:13 -0600 Message-ID: <20220503184820.19312-4-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: upqSRrS7zV6aaY0QEFpa0rzAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603724; bh=5y4eXvzsk28V1JG7BrguDF+0Q9m8VvWdBES/YsnmJm8=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=ZtAaweRl35+dlRweItCwe0PE26ItGas5UTSzGL0G8oLSOhzyukXO7jZZ63pAA/9YSzs OEfFGYF0QS3I2E0+MxFIaO2+YOLqjiMZRkbqxRaDUdPB7olg7ir+f7Gzj4EGeXCEJ322C hA3OBU35J4U0Vp0feGY7Tulb1FwWkbJIs2E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603727264100015 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- CryptoPkg/CryptoPkg.dsc | 1 - CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf | 4 ---- CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf | 4 ---- CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf | 4 ---- CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf | 4 ---- CryptoPkg/Library/OpensslLib/OpensslLib.inf | 1 - CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf | 1 - CryptoPkg/Test/CryptoPkgHostUnitTest.dsc | 1 - 8 files changed, 20 deletions(-) diff --git a/CryptoPkg/CryptoPkg.dsc b/CryptoPkg/CryptoPkg.dsc index 0aa72ed87846..06990cb6fc79 100644 --- a/CryptoPkg/CryptoPkg.dsc +++ b/CryptoPkg/CryptoPkg.dsc @@ -298,5 +298,4 @@ MSFT:*_*_*_CC_FLAGS =3D /D ENABLE_MD5_DEPRECATED_INTERFACES INTEL:*_*_*_CC_FLAGS =3D /D ENABLE_MD5_DEPRECATED_INTERFACES GCC:*_*_*_CC_FLAGS =3D -D ENABLE_MD5_DEPRECATED_INTERFACES - RVCT:*_*_*_CC_FLAGS =3D -DENABLE_MD5_DEPRECATED_INTERFACES !endif diff --git a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf b/CryptoPkg/Li= brary/BaseCryptLib/BaseCryptLib.inf index 5bbdb387d6ba..0310e49ff3ce 100644 --- a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +++ b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf @@ -101,10 +101,6 @@ # MSFT:*_*_*_CC_FLAGS =3D /wd4090 =20 - # -JCryptoPkg/Include : To disable the use of the system includes provid= ed by RVCT - # --diag_remark=3D1 : Reduce severity of "#1-D: last line of file en= ds without a newline" - RVCT:*_*_ARM_CC_FLAGS =3D -JCryptoPkg/Include --diag_remark=3D1 - GCC:*_CLANG35_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANG38_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANGPDB_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Dincompatible-point= er-types diff --git a/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf b/CryptoPkg/Lib= rary/BaseCryptLib/PeiCryptLib.inf index fd500e61ec99..7b93aba26dc3 100644 --- a/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf +++ b/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf @@ -91,10 +91,6 @@ # MSFT:*_*_*_CC_FLAGS =3D /wd4090 /wd4718 =20 - # -JCryptoPkg/Include : To disable the use of the system includes provid= ed by RVCT - # --diag_remark=3D1 : Reduce severity of "#1-D: last line of file en= ds without a newline" - RVCT:*_*_ARM_CC_FLAGS =3D -JCryptoPkg/Include --diag_remark=3D1 - GCC:*_CLANG35_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANG38_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANGPDB_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Dincompatible-point= er-types diff --git a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf b/CryptoPkg= /Library/BaseCryptLib/RuntimeCryptLib.inf index 3e4524896c45..9da781e2218a 100644 --- a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +++ b/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf @@ -106,10 +106,6 @@ # MSFT:*_*_*_CC_FLAGS =3D /wd4090 =20 - # -JCryptoPkg/Include : To disable the use of the system includes provid= ed by RVCT - # --diag_remark=3D1 : Reduce severity of "#1-D: last line of file en= ds without a newline" - RVCT:*_*_ARM_CC_FLAGS =3D -JCryptoPkg/Include --diag_remark=3D1 - GCC:*_CLANG35_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANG38_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANGPDB_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Dincompatible-point= er-types diff --git a/CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf b/= CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf index 44c183b90563..71e39c9536b8 100644 --- a/CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf +++ b/CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf @@ -85,10 +85,6 @@ # C4018: '>': signed/unsigned mismatch MSFT:*_*_*_CC_FLAGS =3D /wd4090 /wd4018 =20 - # -JCryptoPkg/Include : To disable the use of the system includes provid= ed by RVCT - # --diag_remark=3D1 : Reduce severity of "#1-D: last line of file en= ds without a newline" - RVCT:*_*_ARM_CC_FLAGS =3D -JCryptoPkg/Include --diag_remark=3D1 - GCC:*_CLANG35_*_CC_FLAGS =3D -std=3Dc99 GCC:*_CLANG38_*_CC_FLAGS =3D -std=3Dc99 =20 diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf b/CryptoPkg/Librar= y/OpensslLib/OpensslLib.inf index a97b3f5e8ff2..93a317a6f9c0 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf @@ -694,7 +694,6 @@ # 1: ignore "#1-D: last line of file ends without a newline" # 3017: may be used before being set (NOTE: This was fixed in O= penSSL 1.1 HEAD with # commit d9b8b89bec4480de3a10bdaf9425db371c19145b, and can be drop= ped then.) - RVCT:*_*_ARM_CC_FLAGS =3D $(OPENSSL_FLAGS) --library_interface=3Daea= bi_clib99 --diag_suppress=3D1296,1295,550,1293,111,68,177,223,144,513,188,1= 28,546,1,3017 -JCryptoPkg/Include XCODE:*_*_IA32_CC_FLAGS =3D -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FL= AGS) -w -std=3Dc99 -Wno-error=3Duninitialized XCODE:*_*_X64_CC_FLAGS =3D -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FL= AGS) -w -std=3Dc99 -Wno-error=3Duninitialized =20 diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf b/CryptoPkg/= Library/OpensslLib/OpensslLibCrypto.inf index 490b83602be9..6c9f80530479 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf @@ -643,7 +643,6 @@ # 1: ignore "#1-D: last line of file ends without a newline" # 3017: may be used before being set (NOTE: This was fixed in O= penSSL 1.1 HEAD with # commit d9b8b89bec4480de3a10bdaf9425db371c19145b, and can be drop= ped then.) - RVCT:*_*_ARM_CC_FLAGS =3D $(OPENSSL_FLAGS) --library_interface=3Daea= bi_clib99 --diag_suppress=3D1296,1295,550,1293,111,68,177,223,144,513,188,1= 28,546,1,3017 -JCryptoPkg/Include XCODE:*_*_IA32_CC_FLAGS =3D -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FL= AGS) -w -std=3Dc99 -Wno-error=3Duninitialized XCODE:*_*_X64_CC_FLAGS =3D -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FL= AGS) -w -std=3Dc99 -Wno-error=3Duninitialized =20 diff --git a/CryptoPkg/Test/CryptoPkgHostUnitTest.dsc b/CryptoPkg/Test/Cryp= toPkgHostUnitTest.dsc index c50a9cc4dc9f..16478f4a57ca 100644 --- a/CryptoPkg/Test/CryptoPkgHostUnitTest.dsc +++ b/CryptoPkg/Test/CryptoPkgHostUnitTest.dsc @@ -43,4 +43,3 @@ MSFT:*_*_*_CC_FLAGS =3D /D ENABLE_MD5_DEPRECATED_INTERFACES INTEL:*_*_*_CC_FLAGS =3D /D ENABLE_MD5_DEPRECATED_INTERFACES GCC:*_*_*_CC_FLAGS =3D -D ENABLE_MD5_DEPRECATED_INTERFACES - RVCT:*_*_*_CC_FLAGS =3D -DENABLE_MD5_DEPRECATED_INTERFACES --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89489): https://edk2.groups.io/g/devel/message/89489 Mute This Topic: https://groups.io/mt/90866286/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89490+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89490+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603727; cv=none; d=zohomail.com; s=zohoarc; b=NcUX7xGoOsbSCyGJ9laT4cGwcF2RanWESSZKQ3KBUF89D5AV1/AgBtzz26LPKuw6wCfCj/u9qbkYdfO7DfPMnzj92KtSvOwAlkjew77s2aV6JY0hNslJql1Zx46LugKWLwxGrtIBU6gV9992/Wh+vrNd9fUR+oKtdNoM0j8vlN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603727; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=SD5ZzSogyjcxasEw+LyuhS5eIary2Bna0BesH9909LU=; b=MWKLC44KxaL0/occDugCfVkOrjIaMo8DmG7S7Z6IzyzT/paUYqXwd5vkaedpMVldR2spr1W9Zr3yb7lXii0jnrMegauxIDxFxqhTpZxLZ1ltnkyJZxKUCdGx+9FuMOdoey2F29s6P6nUwGSlO7W/itQPklIkj30JEPsn+UPPUNE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89490+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603727030341.4213227782616; Tue, 3 May 2022 11:48:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1BHuYY1788612xnHYFliIbnK; Tue, 03 May 2022 11:48:46 -0700 X-Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by mx.groups.io with SMTP id smtpd.web08.1016.1651603726023523017 for ; Tue, 03 May 2022 11:48:46 -0700 X-Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 03 May 2022 11:48:45 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:44 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:43 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:42 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 04/10] MdePkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:14 -0600 Message-ID: <20220503184820.19312-5-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: TefX98aNKlZ8hSlv189ZUbU9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603726; bh=hzGtGiw5yu0B92Jw8Mb//JT/lFNwd4bzougIxdADiuU=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=hqrGePrOTn3xIlLqblXrj153K7jMS1ebmsxmSmgoNkPG2oTN2WKSARz8ejvIXR6nmW9 1WcTpXKyway/JusNUKmxklyn/1P9BVE7E1c/0eEadUEK4rFHZixIIdkPF1idf6mPulW2F HLFNqW026qViNDDH5bqI6zkphKFZja6s698= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603729211100023 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- MdePkg/Include/Arm/ProcessorBind.h | 4 +- MdePkg/Include/Base.h | 42 +---= ---------------- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 2 - MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf | 1 - MdePkg/Library/BaseLib/BaseLib.inf | 11 ----- MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf | 8 ---- MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 6 --- MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf | 1 - MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 1 - 9 files changed, 3 insertions(+), 73 deletions(-) diff --git a/MdePkg/Include/Arm/ProcessorBind.h b/MdePkg/Include/Arm/Proces= sorBind.h index 5a8204ba2e66..3d924f19a35d 100644 --- a/MdePkg/Include/Arm/ProcessorBind.h +++ b/MdePkg/Include/Arm/ProcessorBind.h @@ -72,9 +72,9 @@ #endif =20 // -// RVCT and MSFT don't support the __builtin_unreachable() macro +// MSFT doesn't support the __builtin_unreachable() macro // -#if defined (__ARMCC_VERSION) || defined (_MSC_EXTENSIONS) +#if defined (_MSC_EXTENSIONS) #define UNREACHABLE() #endif =20 diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index ce7bdedd34e2..d19ddfe4bba7 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -204,15 +204,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED #endif =20 -#ifdef __CC_ARM -// -// Older RVCT ARM compilers don't fully support #pragma pack and require _= _packed -// as a prefix for the structure. -// -#define PACKED __packed -#else #define PACKED -#endif =20 /// /// 128 bit buffer containing a unique identifier value. @@ -578,39 +570,7 @@ struct _LIST_ENTRY { **/ #define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UIN= TN) - 1)) =20 -#if defined (__CC_ARM) -// -// RVCT ARM variable argument list support. -// - -/// -/// Variable used to traverse the list of arguments. This type can vary by -/// implementation and could be an array or structure. -/// - #ifdef __APCS_ADSABI -typedef int *va_list[1]; -#define VA_LIST va_list - #else -typedef struct __va_list { - void *__ap; -} va_list; -#define VA_LIST va_list - #endif - -#define VA_START(Marker, Parameter) __va_start(Marker, Parameter) - -#define VA_ARG(Marker, TYPE) __va_arg(Marker, TYPE) - -#define VA_END(Marker) ((void)0) - -// For some ARM RVCT compilers, __va_copy is not defined - #ifndef __va_copy -#define __va_copy(dest, src) ((void)((dest) =3D (src))) - #endif - -#define VA_COPY(Dest, Start) __va_copy (Dest, Start) - -#elif defined (_M_ARM) || defined (_M_ARM64) +#if defined (_M_ARM) || defined (_M_ARM64) // // MSFT ARM variable argument list support. // diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index 950f5229b2a4..c4cd29a7839d 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -47,8 +47,6 @@ Ebc/CpuSleepFlushTlb.c =20 [Sources.ARM] - Arm/CpuFlushTlb.asm | RVCT - Arm/CpuSleep.asm | RVCT Arm/CpuFlushTlb.asm | MSFT Arm/CpuSleep.asm | MSFT Arm/CpuFlushTlb.S | GCC diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.in= f b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf index cea6857926b3..e803abc0b171 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf @@ -31,7 +31,6 @@ [Sources.ARM] IoLibArmVirt.c Arm/ArmVirtMmio.S | GCC - Arm/ArmVirtMmio.asm | RVCT =20 [Sources.AARCH64] IoLibArmVirt.c diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 16b7ac391705..6be5be9428f2 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -341,19 +341,8 @@ [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT Math64.c | MSFT =20 - Arm/SwitchStack.asm | RVCT - Arm/SetJumpLongJump.asm | RVCT - Arm/DisableInterrupts.asm | RVCT - Arm/EnableInterrupts.asm | RVCT - Arm/GetInterruptsState.asm | RVCT - Arm/CpuPause.asm | RVCT - Arm/CpuBreakpoint.asm | RVCT - Arm/MemoryFence.asm | RVCT - Arm/SpeculationBarrier.S | RVCT - Arm/SwitchStack.asm | MSFT Arm/SetJumpLongJump.asm | MSFT Arm/DisableInterrupts.asm | MSFT diff --git a/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf b/MdePkg/Librar= y/BaseLib/UnitTestHostBaseLib.inf index d09bd12bef19..09a610c31c1d 100644 --- a/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf +++ b/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf @@ -180,16 +180,8 @@ [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT Math64.c | MSFT =20 - Arm/SwitchStack.asm | RVCT - Arm/SetJumpLongJump.asm | RVCT - Arm/CpuPause.asm | RVCT - Arm/CpuBreakpoint.asm | RVCT - Arm/MemoryFence.asm | RVCT - Arm/SpeculationBarrier.S | RVCT - Arm/SwitchStack.asm | MSFT Arm/SetJumpLongJump.asm | MSFT Arm/CpuPause.asm | MSFT diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M= dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf index e4e3d532e7b8..366a6c6f64a0 100644 --- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf +++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf @@ -85,12 +85,6 @@ Arm/CompareMem.S |GCC Arm/CompareGuid.S |GCC =20 - Arm/ScanMem.asm |RVCT - Arm/SetMem.asm |RVCT - Arm/CopyMem.asm |RVCT - Arm/CompareMem.asm |RVCT - Arm/CompareGuid.asm |RVCT - [Sources.AARCH64] AArch64/ScanMem.S AArch64/SetMem.S diff --git a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf b/MdePk= g/Library/BaseStackCheckLib/BaseStackCheckLib.inf index 0dc3c4a83aa5..b827645d72b9 100644 --- a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf +++ b/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf @@ -26,7 +26,6 @@ =20 [Sources] BaseStackCheckGcc.c | GCC - BaseStackCheckGcc.c | RVCT BaseStackCheckNull.c | MSFT =20 [Packages] diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 83d5b8ed7c9b..02ba12961a19 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -71,7 +71,6 @@ =20 [Sources.ARM] Synchronization.c - Arm/Synchronization.asm | RVCT Arm/Synchronization.S | GCC =20 [Sources.AARCH64] --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89490): https://edk2.groups.io/g/devel/message/89490 Mute This Topic: https://groups.io/mt/90866288/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89491+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89491+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603727; cv=none; d=zohomail.com; s=zohoarc; b=GeqHwDgpSUGZTOFJYgKdyzisGvGK4Lx2xE9+e2m6XxQIkTS+J+DcEfHyK/ZGH7OZdPSy5gOTnhh3WGdu1Ce5nBOC2mqwOikEAl8kVkShoAt7jzWL5cBkoUHR9dch8hTZNtgH6TQPmCwD+HlZtgOdo00l5DDc6EG32PAIYn33CEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603727; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Q3FgzI/htdROJopDeRsvQZ1wIJvGUNiC6Tpiys1+kdA=; b=cIfJL9PBTvM08DCS96k8lmnVbmQPYpvseolhWUFooWESrYo2p9keIlMgFNq/OmdTOsyiCE0JgUBUUElIKUxq+n7Ma9EjAxAGnVJ6Za2h3YPUxbL7+SIuQN8GTVOxM3l+J4PKlaJBqVdopjlG/SmshOVGwW79KHIIFe0XTUGeThY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89491+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603727413421.3808372597713; Tue, 3 May 2022 11:48:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dTNNYY1788612xv1mKIOyhPJ; Tue, 03 May 2022 11:48:47 -0700 X-Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web08.1014.1651603719238416815 for ; Tue, 03 May 2022 11:48:46 -0700 X-Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 03 May 2022 11:48:46 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:45 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:45 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:43 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 05/10] FatPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:15 -0600 Message-ID: <20220503184820.19312-6-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: fmWnRRu72Tp7Er3C37mVJSmXx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603727; bh=qxfN/BGNfJsVXFqlJiq7muMaK/L9K9VeneJ8Cq/kwNI=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=nVmLnCNDXPA/UC6XDQ2lhAUMVKghLZNICzWQmB5JZ0dbvyIi3g8B2t4z5ZaNdKYJOup vsxik2CheRUecXlq2yfa7xE337dXvCI3zfcDI4kZc7tcbz+wIL0nOEDgPaX3HrS+MAmHo PJkzr8Djp3QwuPZYCKQNflA7cW1hsL+EIFo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603729190100021 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- FatPkg/FatPkg.dsc | 1 - 1 file changed, 1 deletion(-) diff --git a/FatPkg/FatPkg.dsc b/FatPkg/FatPkg.dsc index 4ddb5c3e004b..6fa439e440cb 100644 --- a/FatPkg/FatPkg.dsc +++ b/FatPkg/FatPkg.dsc @@ -24,7 +24,6 @@ GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG INTEL:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG MSFT:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG - RVCT:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTER= FACES =20 !include MdePkg/MdeLibs.dsc.inc --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89491): https://edk2.groups.io/g/devel/message/89491 Mute This Topic: https://groups.io/mt/90866289/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89492+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89492+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603728; cv=none; d=zohomail.com; s=zohoarc; b=Dt/SszbElmohDt6J9pZ3Rbxc6OxtWiH4JBT6Ff7K7cZ9E6eJ7CsTnBeJoNp5v1yMBPHINjmm8HwzVV6zmYGjlq3EOFs6N6yCaJVepflEQJ6nrU+VyGfrudEfx+CMnTXnrDU4U1cwEESLtnrMBpfXT1ztmij7yAXf5MaL4QN3LDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603728; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XqfBE2GIPiDTNrtb60DkAcNOFMnZCKOB0COHxvr4ebM=; b=d5sYeuoWtiQakP4kNKOcI4VRlWOMZ6j3LW8WcLBYyGXJCVY8cGybgzdqthyCsj2lrVCcKKTcdVL6r1mYHjXiu0NgKXpkQHVh9SQDyNyETVmrwbNxeoF9WXbRq1pWBZ4E3Q9qnvRrkQi5fgPA2WlgmZ7ddg+StIxUfHWzwnUAIqY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89492+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603728613932.0398758749495; Tue, 3 May 2022 11:48:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ezDLYY1788612xkXDoJTuFD7; Tue, 03 May 2022 11:48:48 -0700 X-Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by mx.groups.io with SMTP id smtpd.web08.1015.1651603723967357143 for ; Tue, 03 May 2022 11:48:47 -0700 X-Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 03 May 2022 11:48:47 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:47 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:46 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:45 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 06/10] NetworkPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:16 -0600 Message-ID: <20220503184820.19312-7-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: 4QnF1N2UegaJLVz6gwMnW9wTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603728; bh=H0rLmR+lIv/OuCc5vtssj2Yph2iIhfqarUE3cMK4stQ=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VIuGqLt+tpj4IEt02bF6oUEA/iiH8h6UBWbsBUzFlendWJdENaV1gZSDCeuz3c+dJm6 g6ro0T8Yf/nrbANfnjki4fguOQ1+jYmyOTrn4Dl4wkFWnlPpadiAipy2L4ylwm7Q/e/Gw pXWdUuudzhj306VBoTpF3+Qj1WFWo2rjWXc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603729205100022 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- NetworkPkg/NetworkBuildOptions.dsc.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/NetworkPkg/NetworkBuildOptions.dsc.inc b/NetworkPkg/NetworkBui= ldOptions.dsc.inc index 738da2222f7e..e83765b199c1 100644 --- a/NetworkPkg/NetworkBuildOptions.dsc.inc +++ b/NetworkPkg/NetworkBuildOptions.dsc.inc @@ -6,7 +6,7 @@ # feature test macros (eg., API deprecation macros) according to the flags= described # in "NetworkDefines.dsc.inc". # -# Supported tool chain families: "GCC", "INTEL", "MSFT", "RVCT". +# Supported tool chain families: "GCC", "INTEL", "MSFT". # # Copyright (c) 2020, Intel Corporation. All rights reserved.
# @@ -18,5 +18,4 @@ MSFT:*_*_*_CC_FLAGS =3D /D ENABLE_MD5_DEPRECATED_INTERFACES INTEL:*_*_*_CC_FLAGS =3D /D ENABLE_MD5_DEPRECATED_INTERFACES GCC:*_*_*_CC_FLAGS =3D -D ENABLE_MD5_DEPRECATED_INTERFACES - RVCT:*_*_*_CC_FLAGS =3D -DENABLE_MD5_DEPRECATED_INTERFACES !endif --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89492): https://edk2.groups.io/g/devel/message/89492 Mute This Topic: https://groups.io/mt/90866290/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89493+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89493+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603730; cv=none; d=zohomail.com; s=zohoarc; b=jJTeRVxphTgBSYSrfuhZjE2T8vYumFzLuVyR8iE4PEIX0pRXZGzt2Du/gfaxeeVqWWYy0iQ+iciEahxs6ndgY4xIV7bs6D8T3IqArvwG1MVfYp62w2TnOO44CASvFlfIvLQa+FlMwJr4O3fLjqZ0x1L4hNehGVZ42B6hn1Q/weA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603730; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=p8CiKWkZYtRJ4tzarp/xqrgttSDpRvvlBOpAzRPhZk8=; b=S0L4fH4wVocuw/Nyglqgjo7oaDm7e93ujTPNBwsDd4mcgyM6Pj/aB76le0lKnI/5eUe4v1u4PPtZeJi8DuQjuyQjGKsg1U5/U69mic4G5i+WgC8PQxnCYnPRZjc8+g3hkwHHUBuvmM6JceUNQMaSgMvdWW68xXV4s8UOUnRJf18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89493+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603730141819.5406741385843; Tue, 3 May 2022 11:48:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qCrOYY1788612xBr4BAblXdy; Tue, 03 May 2022 11:48:49 -0700 X-Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by mx.groups.io with SMTP id smtpd.web08.1016.1651603726023523017 for ; Tue, 03 May 2022 11:48:48 -0700 X-Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 03 May 2022 11:48:48 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:48 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:48 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:46 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 07/10] ArmVirtPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:17 -0600 Message-ID: <20220503184820.19312-8-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: f7gAkaldODgBZECprSgnTVt8x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603729; bh=ns6Jk0Xjha8PAbfz3JRd3HS6wxt+5FOonlciIn57sK0=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=q/lkH7E4vs7EGcpVvRvCFp/5Dr/dSLZrPhRDO/zJStSxo3LIdeycZkRDyrSoiXfVoTC 8aqlPZmRpX02fWUBNfaxbLR3JJcpsnxScsiJl6WOEzPzREVwah7Tdsd7U7Obk46f8/Xyh P0Xv/PVEuNwSG8RpkHZ7+bTiu180ea5CqSY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603731221100031 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- ArmVirtPkg/ArmVirt.dsc.inc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc index ba711deac025..5784509224e4 100644 --- a/ArmVirtPkg/ArmVirt.dsc.inc +++ b/ArmVirtPkg/ArmVirt.dsc.inc @@ -32,7 +32,6 @@ [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 - RVCT:*_*_ARM_DLINK_FLAGS =3D --scatter $(EDK_TOOLS_PATH)/Scripts/Rvct-Al= ign4K.sct =20 [LibraryClasses.common] !if $(TARGET) =3D=3D RELEASE @@ -262,14 +261,11 @@ ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf =20 [BuildOptions] - RVCT:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG - GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG =20 # # Disable deprecated APIs. # - RVCT:*_*_*_CC_FLAGS =3D -DDISABLE_NEW_DEPRECATED_INTERFACES GCC:*_*_*_CC_FLAGS =3D -DDISABLE_NEW_DEPRECATED_INTERFACES =20 ##########################################################################= ###### --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89493): https://edk2.groups.io/g/devel/message/89493 Mute This Topic: https://groups.io/mt/90866291/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89494+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89494+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603731; cv=none; d=zohomail.com; s=zohoarc; b=Zwrefqwf5LvERquidarACrCXfGsBVk3At2vqC6t+DIyztoSzHxxHJSHLikfxnqztOaVX12ar6bNz3mqnPe+9jyWboJ5W3ut4l45G/4BYjrLCYIUjtqxBUhoVgRfNl2IWPjMhvxoBAKGZx2JpoahqnhGXOoF0ndfy4FQeiChrdW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603731; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=37aKBRH2PUk04+WYFc7isvZJog08ldMgCL9D97sL8xs=; b=T3ZkK/kgyrOuoXNP3so+P6reihtCcYEcTlsA3bgqabAbFwlrvOXMx/4AZ8xdvxN0kP4F/yqbBFEiTx4gidtNx9nckbsrQvmT1xyX1EcgFMsPHGqpBgSAEz1I5uGpw792JZDDWLHXeOwTXfc6NE3WXALae2C6D5irZM31U3F9aIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89494+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1651603731637183.30627443140168; Tue, 3 May 2022 11:48:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DgqyYY1788612xZ2RcRvnr0r; Tue, 03 May 2022 11:48:51 -0700 X-Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web08.1014.1651603719238416815 for ; Tue, 03 May 2022 11:48:50 -0700 X-Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 03 May 2022 11:48:50 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:50 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:49 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:48 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 08/10] EmbeddedPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:18 -0600 Message-ID: <20220503184820.19312-9-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: auZZDRrSLKpUywHrEYwnalsbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603731; bh=gx97YFLc2yJqBd4FgyKnFnOCvGOX02bpiM6umJ5FJY4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=R41DB9whM8Xa62zwYmMQ0OFA+2wVC8lDWvT6ld1E0giSe8z32e8sU2+MXJy8AhTvE+c bZCL81a63clkmv/RKJXHtzG3TZv7Y6zhGhgSl9EzsEA79N0Nlq51ps985PUF+S5OoIlu3 8psLeeZIUP5RCsHaN90jQKnKDrKh4OYZmWc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603733241100036 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- EmbeddedPkg/EmbeddedPkg.dsc | 1 - EmbeddedPkg/GdbStub/Arm/Processor.c | 10 ---------- 2 files changed, 11 deletions(-) diff --git a/EmbeddedPkg/EmbeddedPkg.dsc b/EmbeddedPkg/EmbeddedPkg.dsc index f7ed61545c2e..e9062cacbb42 100644 --- a/EmbeddedPkg/EmbeddedPkg.dsc +++ b/EmbeddedPkg/EmbeddedPkg.dsc @@ -199,7 +199,6 @@ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 =20 [BuildOptions] - RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu=3D7-A.security *_*_*_CC_FLAGS =3D -DDISABLE_NEW_DEPRECATED_INTERFACES =20 ##########################################################################= ###### diff --git a/EmbeddedPkg/GdbStub/Arm/Processor.c b/EmbeddedPkg/GdbStub/Arm/= Processor.c index ec160903a5fb..ed91b6b561d9 100644 --- a/EmbeddedPkg/GdbStub/Arm/Processor.c +++ b/EmbeddedPkg/GdbStub/Arm/Processor.c @@ -23,11 +23,6 @@ EFI_EXCEPTION_TYPE_ENTRY gExceptionType[] =3D { // { EXCEPT_ARM_RESERVED, GDB_SIGILL } }; =20 -// Shut up some annoying RVCT warnings -#ifdef __CC_ARM - #pragma diag_suppress 1296 -#endif - UINTN gRegisterOffsets[] =3D { OFFSET_OF (EFI_SYSTEM_CONTEXT_ARM, R0), OFFSET_OF (EFI_SYSTEM_CONTEXT_ARM, R1), @@ -73,11 +68,6 @@ UINTN gRegisterOffsets[] =3D { OFFSET_OF (EFI_SYSTEM_CONTEXT_ARM, CPSR) }; =20 -// restore warnings for RVCT -#ifdef __CC_ARM - #pragma diag_default 1296 -#endif - /** Return the number of entries in the gExceptionType[] =20 --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89494): https://edk2.groups.io/g/devel/message/89494 Mute This Topic: https://groups.io/mt/90866292/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 20:04:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89495+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89495+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1651603732; cv=none; d=zohomail.com; s=zohoarc; b=lgom+X0J4AktvTCL2e3voL+ipzNcPf+ZAdRsd/cBbxDrcmY3dIrU7kmaPditGJetr3V6NYr86cc2ihTybDupr3Vue3tt5DGFRNy4LNiasil6fyn8AGgNB1gGIhd/+T8855N82kFsh7Njf1/fiK1BxpXjY8mZqtbdWpzCLTetZ24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651603732; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xlvG7Kozuw3Z11F1GDxKOUlfAqFUyqiepU7YAAgU1/Y=; b=la+YwSh/7tt6ZZzFhhgbyKODzPPd/ROaro2pJkcTT9kHojG+Ls6XgzfgNxFu8OP0qM0+yPz4g/VO8/vvYFVs2kk2rhCN7l4DJ2IekKj1AlEoe+ltcnfe9cpKUgL7gwyJLE9R3C62+SGU6PdO6ZSWpiNy3UxF8OuVlnytt2gxL4Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89495+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165160373291494.72738783311661; Tue, 3 May 2022 11:48:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eTYcYY1788612xHNyERHZu4b; Tue, 03 May 2022 11:48:52 -0700 X-Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by mx.groups.io with SMTP id smtpd.web08.1015.1651603723967357143 for ; Tue, 03 May 2022 11:48:52 -0700 X-Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 03 May 2022 11:48:52 -0700 X-QCInternal: smtphost X-Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:48:51 -0700 X-Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:50 -0700 X-Received: from linbox.ba.nuviainc.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 3 May 2022 11:48:49 -0700 From: "Rebecca Cran" To: , Leif Lindholm , "Ard Biesheuvel" , Sami Mujawar , Gerd Hoffmann , Bob Feng , "Liming Gao" , Yuwei Chen , "Jiewen Yao" , Jian J Wang , Xiaoyu Lu , Guomin Jiang , Abner Chang , Daniel Schaefer , Ray Ni , Michael D Kinney , "Zhiguang Liu" , Maciej Rabeda , Jiaxin Wu , Siyuan Fu , "Jordan Justen" , Anthony Perard , Julien Grall CC: Rebecca Cran Subject: [edk2-devel] [PATCH 09/10] OvmfPkg: Remove RVCT support Date: Tue, 3 May 2022 12:48:19 -0600 Message-ID: <20220503184820.19312-10-quic_rcran@quicinc.com> In-Reply-To: <20220503184820.19312-1-quic_rcran@quicinc.com> References: <20220503184820.19312-1-quic_rcran@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_rcran@quicinc.com X-Gm-Message-State: 6qaiCK2hmBf29sppsIB7epSIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1651603732; bh=XVHp4pA0huB0XbUxs55hkgNwBJswQmqgk6mrK0nd6Ac=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VpVpRmG9Hw9oVwSNCm46GbNm0R0ZDekXAgspqOcfgc51bSfipaGyBvWWNPPRZ1eRZyn zw0kgsXwIqwfDWGd/oBMpsMJtkl4qvOzrVJK2+dt85L9RKW75tCPnoCEGX9/SXJamfMPz TRkneniErcL5UV10F2IwrPErjkibhAzygf4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1651603733227100035 Content-Type: text/plain; charset="utf-8" RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- OvmfPkg/Library/XenHypercallLib/XenHypercallLib.inf | 3 --- 1 file changed, 3 deletions(-) diff --git a/OvmfPkg/Library/XenHypercallLib/XenHypercallLib.inf b/OvmfPkg/= Library/XenHypercallLib/XenHypercallLib.inf index 21ce5b443471..32ae73f7aac5 100644 --- a/OvmfPkg/Library/XenHypercallLib/XenHypercallLib.inf +++ b/OvmfPkg/Library/XenHypercallLib/XenHypercallLib.inf @@ -58,6 +58,3 @@ =20 [Guids.IA32, Guids.X64] gEfiXenInfoGuid - -[BuildOptions.ARM] - RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu Cortex-A15 --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Remove support for it. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm Acked-by: Liming Gao Reviewed-by: Ard Biesheuvel Reviewed-by: Bob Feng --- BaseTools/Conf/build_rule.template | 42 ++---- BaseTools/Conf/tools_def.template | 157 -------------------- BaseTools/Scripts/Rvct-Align32.sct | 19 --- BaseTools/Scripts/Rvct-Align4K.sct | 19 --- BaseTools/Source/C/Include/Common/BaseTypes.h | 10 +- BaseTools/Source/Python/AutoGen/BuildEngine.py | 2 +- BaseTools/Source/Python/AutoGen/GenMake.py | 2 +- BaseTools/Source/Python/AutoGen/ModuleAutoGen.py | 17 +-- BaseTools/Source/Python/UPT/Library/DataType.py | 1 - 9 files changed, 16 insertions(+), 253 deletions(-) diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule= .template index 435662351213..5895b48fd88d 100755 --- a/BaseTools/Conf/build_rule.template +++ b/BaseTools/Conf/build_rule.template @@ -128,8 +128,7 @@ "$(CC)" /Fo${dst} $(DEPS_FLAGS) $(CC_FLAGS) $(INC) ${src} =20 - - # For RVCTCYGWIN CC_FLAGS must be first to work around pathing iss= ues + "$(CC)" $(DEPS_FLAGS) $(CC_FLAGS) -c -o ${dst} $(INC) ${src} =20 @@ -145,7 +144,7 @@ $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj =20 - + "$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src} =20 [C-Header-File] @@ -157,7 +156,7 @@ =20 [Assembly-Code-File.COMMON.COMMON] - + ?.asm, ?.Asm, ?.ASM =20 @@ -175,16 +174,15 @@ Trim --source-code --convert-hex --trim-long -o ${d_path}(+)${s_ba= se}.iiii ${d_path}(+)${s_base}.ii "$(ASM)" /Fo${dst} $(ASM_FLAGS) /I${s_path} $(INC) ${d_path}(+)${s= _base}.iiii =20 - + Trim --asm-file -o ${d_path}(+)${s_base}.i -i $(INC_LIST) ${src} "$(PP)" $(DEPS_FLAGS) $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_= base}.ii Trim --trim-long --source-code -o ${d_path}(+)${s_base}.iiii ${d_p= ath}(+)${s_base}.ii - # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iiii =20 [Assembly-Code-File.COMMON.ARM,Assembly-Code-File.COMMON.AARCH64] # Remove --convert-hex for ARM as it breaks MSFT assemblers - + ?.asm, ?.Asm, ?.ASM =20 @@ -208,11 +206,10 @@ Trim --source-code --trim-long -o ${d_path}(+)${s_base}.iiii ${d_p= ath}(+)${s_base}.ii "$(ASM)" /Fo${dst} $(ASM_FLAGS) /I${s_path} $(INC) ${d_path}(+)${s= _base}.iiii =20 - + Trim --asm-file -o ${d_path}(+)${s_base}.i -i $(INC_LIST) ${src} "$(PP)" $(DEPS_FLAGS) $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_= base}.ii Trim --trim-long --source-code -o ${d_path}(+)${s_base}.iiii ${d_p= ath}(+)${s_base}.ii - # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iiii =20 [Nasm-Assembly-Code-File.COMMON.COMMON] @@ -276,13 +273,6 @@ $(RM) ${dst} "$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST) =20 - - "$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST) - =20 - - # $(OBJECT_FILES_LIST) has wrong paths for cygwin - "$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES) - "$(SLINK)" $(SLINK_FLAGS) ${dst} -filelist $(OBJECT_FILES_LIST) =20 @@ -307,13 +297,6 @@ "$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-group,@$(STATIC_LI= BRARY_FILES_LIST),--end-group $(CC_FLAGS) $(DLINK2_FLAGS) "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst} =20 - - "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) --via $(STATIC_= LIBRARY_FILES_LIST) $(DLINK2_FLAGS) - - - #$(STATIC_LIBRARY_FILES_LIST) has wrong paths for cygwin - "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) $(STATIC_LIBRAR= Y_FILES) $(DLINK2_FLAGS) - "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist $(STA= TIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS) =20 @@ -349,13 +332,6 @@ "$(DLINK)" $(DLINK_FLAGS) -Wl,--start-group,@$(STATIC_LIBRARY_FILE= S_LIST),--end-group $(DLINK2_FLAGS) =20 - - "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) --via $(STATIC_= LIBRARY_FILES_LIST) $(DLINK2_FLAGS) - - - #$(STATIC_LIBRARY_FILES_LIST) has the wrong paths for cygwin - "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) $(STATIC_LIBRAR= Y_FILES) $(DLINK2_FLAGS) - "$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist $(ST= ATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS) =20 @@ -369,7 +345,7 @@ $(DEBUG_DIR)(+)$(MODULE_NAME).efi $(OUTPUT_DIR)(+)$(MODULE_NAME).map =20 - + "$(GENFW)" -e $(MODULE_TYPE) -o ${dst} ${src} $(GENFW_FLAGS) $(CP) ${dst} $(DEBUG_DIR) $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi @@ -661,7 +637,7 @@ $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.lib =20 - + $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc =20 @@ -671,5 +647,5 @@ "$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUI= D) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS) "$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst} - + "$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUI= D) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 9c310cf23d25..5ed19810b727 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -333,24 +333,6 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Required to build platforms or ACPI tables: # Intel(r) ACPI Compiler (iasl.exe) from # https://acpica.org/downloads -# RVCT -win- Requires: -# ARM C/C++ Compiler, 5.00 -# Optional: -# Required to build EBC drivers: -# Intel(r) Compiler for Efi Byte Code (Intel= (r) EBC Compiler) -# Required to build platforms or ACPI tables: -# Microsoft ASL ACPI Compiler (asl.exe) v4.0= .0 from -# http://download.microsoft.com/download/2/c= /1/2c16c7e0-96c1-40f5-81fc-3e4bf7b65496/microsoft_asl_compiler-v4-0-0.msi -# Notes: Since this tool chain is obsolete, it does= n't enable the compiler option for included header file list generation, -# and lose the incremental build capability. -# RVCTLINUX -unix- Requires: -# ARM C/C++ Compiler, 5.00 -# Optional: -# Required to build platforms or ACPI tables: -# Intel(r) ACPI Compiler from -# https://acpica.org/downloads -# Notes: Since this tool chain is obsolete, it does= n't enable the compiler option for included header file list generation, -# and lose the incremental build capability. # * Commented out - All versions of VS2005 use the same standard install d= irectory # ##########################################################################= ########## @@ -361,7 +343,6 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # MSFT - Microsoft # GCC - GNU GCC # INTEL - INTEL -# RVCT - ARM RealView Toolchain ##########################################################################= ########## ##########################################################################= ########## # @@ -3012,144 +2993,6 @@ RELEASE_XCODE5_X64_ASM_FLAGS =3D -arch x86_64 NOOPT_XCODE5_X64_CC_FLAGS =3D -target x86_64-pc-win32-macho -c -g -gdw= arf -O0 -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno= -ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implici= t-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missi= ng-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-vara= rgs -ftrap-function=3Dundefined_behavior_has_been_optimized_away_by_clang -= D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS) RELEASE_XCODE5_X64_CC_FLAGS =3D -target x86_64-pc-win32-macho -c -Os = -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-exte= nsions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float = -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field= -initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno= -unused-const-variable -ftrap-function=3Dundefined_behavior_has_been_optimi= zed_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS) =20 -##########################################################################= ########## -# -# RVCT Common -# -##########################################################################= ########## - -DEFINE RVCT_ALL_ASM_FLAGS =3D --diag_suppress=3D1786 --diag_error=3Dwarn= ing --apcs /interwork -DEFINE RVCT_ALL_CC_FLAGS =3D --c90 --no_autoinline --asm --gnu --apcs /= interwork --signed_chars --no_unaligned_access --split_sections --enum_is_i= nt --preinclude AutoGen.h --diag_suppress=3D186,188,1,111,68 --diag_warning= 167 --diag_error=3Dwarning --diag_style=3Dide --protect_stack -DEFINE RVCT_ALL_DLINK_FLAGS =3D --no_scanlib --no_exceptions --datacompres= sor off --strict --symbols --diag_style=3Dide --no_legacyalign --scatter $(= EDK_TOOLS_PATH)/Scripts/Rvct-Align32.sct - -##########################################################################= ########## -# -# ARM RealView Tools - Windows -# -##########################################################################= ########## -# RVCT - Tools from ARM - -*_RVCT_*_*_FAMILY =3D RVCT - -# -# Use default values, or override in DSC file -# -*_RVCT_ARM_ARCHCC_FLAGS =3D --thumb --fpu=3Dsoftvfp -*_RVCT_ARM_ARCHASM_FLAGS =3D -*_RVCT_ARM_ARCHDLINK_FLAGS =3D -*_RVCT_ARM_PLATFORM_FLAGS =3D --cpu 7-A - - DEBUG_RVCT_ARM_DLINK_FLAGS =3D $(ARCHDLINK_FLAGS) DEF(RVCT_ALL_DLINK= _FLAGS) --entry $(IMAGE_ENTRY_POINT) --map --list $(DEST_DIR_DEBUG)/$(BASE_= NAME).map -RELEASE_RVCT_ARM_DLINK_FLAGS =3D $(ARCHDLINK_FLAGS) DEF(RVCT_ALL_DLINK= _FLAGS) --entry $(IMAGE_ENTRY_POINT) --map --list $(DEST_DIR_DEBUG)/$(BASE_= NAME).map - - -*_RVCT_ARM_ASM_FLAGS =3D $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) DEF(RVCT= _ALL_ASM_FLAGS) -*_RVCT_ARM_PP_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E --prei= nclude AutoGen.h -*_RVCT_ARM_VFRPP_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E -DVFR= COMPILE --preinclude $(MODULE_NAME)StrDefs.h -*_RVCT_ARM_MAKE_PATH =3D nmake /NOLOGO -*_RVCT_ARM_SLINK_FLAGS =3D --partial -o - DEBUG_RVCT_ARM_CC_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(RVCT_= ALL_CC_FLAGS) -O1 -g -RELEASE_RVCT_ARM_CC_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) --diag_su= ppress=3D550 DEF(RVCT_ALL_CC_FLAGS) -O2 - -################## -# ARM definitions -################## -*_RVCT_ARM_CC_PATH =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCT_ARM_SLINK_PATH =3D ENV(RVCT_TOOLS_PATH)armlink -*_RVCT_ARM_DLINK_PATH =3D ENV(RVCT_TOOLS_PATH)armlink -*_RVCT_ARM_ASM_PATH =3D ENV(RVCT_TOOLS_PATH)armasm -*_RVCT_ARM_PP_PATH =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCT_ARM_VFRPP_PATH =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCT_ARM_FROMELF_PATH =3D ENV(RVCT_TOOLS_PATH)fromelf - -##########################################################################= ########## -# -# ARM RealView Tools - Linux -# -##########################################################################= ########## -# RVCTLINUX - Tools from ARM in a Cygwin environment -*_RVCTLINUX_*_*_FAMILY =3D RVCT -*_RVCTLINUX_*_*_BUILDRULEFAMILY =3D RVCTLINUX - -*_RVCTLINUX_*_MAKE_PATH =3D make - -# -# Use default values, or override in DSC file -# -*_RVCTLINUX_ARM_ARCHCC_FLAGS =3D --thumb --fpu=3Dsoftvfp -*_RVCTLINUX_ARM_ARCHASM_FLAGS =3D -*_RVCTLINUX_ARM_ARCHDLINK_FLAGS =3D -*_RVCTLINUX_ARM_PLATFORM_FLAGS =3D --cpu 7-A - -DEBUG_RVCTLINUX_ARM_DLINK_FLAGS =3D $(ARCHDLINK_FLAGS) DEF(RVCT_ALL_DL= INK_FLAGS) --entry $(IMAGE_ENTRY_POINT) --map --list $(DEST_DIR_DEBUG)/$(BA= SE_NAME).map -RELEASE_RVCTLINUX_ARM_DLINK_FLAGS =3D $(ARCHDLINK_FLAGS) DEF(RVCT_ALL_DL= INK_FLAGS) --entry $(IMAGE_ENTRY_POINT) --map --list $(DEST_DIR_DEBUG)/$(BA= SE_NAME).map - -*_RVCTLINUX_ARM_ASM_FLAGS =3D $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) DEF= (RVCT_ALL_ASM_FLAGS) -*_RVCTLINUX_ARM_PP_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E -*_RVCTLINUX_ARM_VFRPP_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E = -DVFRCOMPILE --preinclude $(MODULE_NAME)StrDefs.h -*_RVCTLINUX_ARM_SLINK_FLAGS =3D --partial -o - DEBUG_RVCTLINUX_ARM_CC_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(= RVCT_ALL_CC_FLAGS) -O1 -g -RELEASE_RVCTLINUX_ARM_CC_FLAGS =3D $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) --di= ag_suppress=3D550 DEF(RVCT_ALL_CC_FLAGS) -O2 - -################## -# ARM definitions -################## -*_RVCTLINUX_ARM_CC_PATH =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCTLINUX_ARM_SLINK_PATH =3D ENV(RVCT_TOOLS_PATH)armlink -*_RVCTLINUX_ARM_DLINK_PATH =3D ENV(RVCT_TOOLS_PATH)armlink -*_RVCTLINUX_ARM_ASM_PATH =3D ENV(RVCT_TOOLS_PATH)armasm -*_RVCTLINUX_ARM_PP_PATH =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCTLINUX_ARM_VFRPP_PATH =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCTLINUX_ARM_FROMELF_PATH =3D ENV(RVCT_TOOLS_PATH)fromelf - -##########################################################################= ########## -# -# ARM RealView Tools - Cygwin -# -##########################################################################= ########## -# ARMCYGWIN - Tools from ARM in a Cygwin environment - -*_RVCTCYGWIN_*_*_FAMILY =3D RVCT -*_RVCTCYGWIN_*_*_BUILDRULEFAMILY =3D RVCTCYGWIN - -*_RVCTCYGWIN_ARM_CCPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCTCYGWIN_ARM_SLINKPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)armlink -*_RVCTCYGWIN_ARM_DLINKPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)armlink -*_RVCTCYGWIN_ARM_ASMPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)armasm -*_RVCTCYGWIN_ARM_PPPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCTCYGWIN_ARM_VFRPPPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)armcc -*_RVCTCYGWIN_ARM_FROMELFPATH_FLAG =3D ENV(RVCT_TOOLS_PATH)fromelf - -# -# Use default values, or override in DSC file -# -*_RVCTCYGWIN_ARM_ARCHCC_FLAGS =3D --thumb --fpu=3Dsoftvfp -*_RVCTCYGWIN_ARM_ARCHASM_FLAGS =3D -*_RVCTCYGWIN_ARM_ARCHDLINK_FLAGS =3D -*_RVCTCYGWIN_ARM_PLATFORM_FLAGS =3D --cpu 7-A - - DEBUG_RVCTCYGWIN_ARM_DLINK_FLAGS =3D "$(DLINKPATH_FLAG)" $(ARCHDLINK= _FLAGS) DEF(RVCT_ALL_DLINK_FLAGS) --entry $(IMAGE_ENTRY_POINT) --map --list= `cygpath -m $(DEST_DIR_DEBUG)/$(BASE_NAME).map` -RELEASE_RVCTCYGWIN_ARM_DLINK_FLAGS =3D "$(DLINKPATH_FLAG)" $(ARCHDLINK= _FLAGS) DEF(RVCT_ALL_DLINK_FLAGS) --entry $(IMAGE_ENTRY_POINT) --map --list= `cygpath -m $(DEST_DIR_DEBUG)/$(BASE_NAME).map` - -*_RVCTCYGWIN_ARM_ASM_FLAGS =3D "$(ASMPATH_FLAG)" $(ARCHASM_FLAGS) $(= PLATFORM_FLAGS) DEF(RVCT_ALL_ASM_FLAGS) -*_RVCTCYGWIN_ARM_PP_FLAGS =3D "$(CCPATH_FLAG)" $(ARCHCC_FLAGS) $(PL= ATFORM_FLAGS) -E -*_RVCTCYGWIN_ARM_VFRPP_FLAGS =3D "$(CCPATH_FLAG)" $(ARCHCC_FLAGS) $(PL= ATFORM_FLAGS) -E -DVFRCOMPILE --preinclude `cygpath -m $(MODULE_NAME)StrDe= fs.h` -*_RVCTCYGWIN_ARM_MAKE_PATH =3D make -*_RVCTCYGWIN_ARM_SLINK_FLAGS =3D "$(SLINKPATH_FLAG)" --partial -o - DEBUG_RVCTCYGWIN_ARM_CC_FLAGS =3D "$(CCPATH_FLAG)" $(ARCHCC_FLAGS) $(PL= ATFORM_FLAGS) DEF(RVCT_ALL_CC_FLAGS) -O1 -g -RELEASE_RVCTCYGWIN_ARM_CC_FLAGS =3D "$(CCPATH_FLAG)" $(ARCHCC_FLAGS) $(PL= ATFORM_FLAGS) --diag_suppress=3D550 DEF(RVCT_ALL_CC_FLAGS) -O2 - -################## -# ARM definitions -################## -*_RVCTCYGWIN_ARM_CC_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py -*_RVCTCYGWIN_ARM_SLINK_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py -*_RVCTCYGWIN_ARM_DLINK_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py -*_RVCTCYGWIN_ARM_ASM_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py -*_RVCTCYGWIN_ARM_PP_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py -*_RVCTCYGWIN_ARM_VFRPP_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py -*_RVCTCYGWIN_ARM_FROMELF_PATH =3D ENV(WORKSPACE)/BaseTools/Bin/CYGWIN_N= T-5.1-i686/armcc_wrapper.py - ################# # ASM 16 linker definitions ################# diff --git a/BaseTools/Scripts/Rvct-Align32.sct b/BaseTools/Scripts/Rvct-Al= ign32.sct deleted file mode 100644 index d0969a1a9633..000000000000 --- a/BaseTools/Scripts/Rvct-Align32.sct +++ /dev/null @@ -1,19 +0,0 @@ -/** @file - - Copyright (c) 2015, Linaro Ltd. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -REGION 0x220 RELOC { - ER_RO +0 ALIGN 32 { - * (+RO) - } - ER_RW +0 ALIGN 32 { - * (+RW) - } - ER_ZI +0 { - * (+ZI) - } -} diff --git a/BaseTools/Scripts/Rvct-Align4K.sct b/BaseTools/Scripts/Rvct-Al= ign4K.sct deleted file mode 100644 index bf3738ac1cb4..000000000000 --- a/BaseTools/Scripts/Rvct-Align4K.sct +++ /dev/null @@ -1,19 +0,0 @@ -/** @file - - Copyright (c) 2015, Linaro Ltd. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -REGION 0x1000 RELOC { - ER_RO +0 ALIGN 4096 { - * (+RO) - } - ER_RW +0 ALIGN 4096 { - * (+RW) - } - ER_ZI +0 { - * (+ZI) - } -} diff --git a/BaseTools/Source/C/Include/Common/BaseTypes.h b/BaseTools/Sour= ce/C/Include/Common/BaseTypes.h index 150980b4c0bf..e669da894c32 100644 --- a/BaseTools/Source/C/Include/Common/BaseTypes.h +++ b/BaseTools/Source/C/Include/Common/BaseTypes.h @@ -57,15 +57,7 @@ #define NULL ((VOID *) 0) #endif =20 -#ifdef __CC_ARM - // - // Older RVCT ARM compilers don't fully support #pragma pack and require= __packed - // as a prefix for the structure. - // - #define PACKED __packed -#else - #define PACKED -#endif +#define PACKED =20 // // Support for variable length argument lists using the ANSI standard. diff --git a/BaseTools/Source/Python/AutoGen/BuildEngine.py b/BaseTools/Sou= rce/Python/AutoGen/BuildEngine.py index 722fead75af6..752a1a1f6a86 100644 --- a/BaseTools/Source/Python/AutoGen/BuildEngine.py +++ b/BaseTools/Source/Python/AutoGen/BuildEngine.py @@ -317,7 +317,7 @@ class BuildRule: # @param LineIndex The line number from which the parsing= will begin # @param SupportedFamily The list of supported tool chain famil= ies # - def __init__(self, File=3DNone, Content=3DNone, LineIndex=3D0, Support= edFamily=3D[TAB_COMPILER_MSFT, "INTEL", "GCC", "RVCT"]): + def __init__(self, File=3DNone, Content=3DNone, LineIndex=3D0, Support= edFamily=3D[TAB_COMPILER_MSFT, "INTEL", "GCC"]): self.RuleFile =3D File # Read build rules from file if it's not none if File is not None: diff --git a/BaseTools/Source/Python/AutoGen/GenMake.py b/BaseTools/Source/= Python/AutoGen/GenMake.py index e55efff059f9..da406e6ff468 100755 --- a/BaseTools/Source/Python/AutoGen/GenMake.py +++ b/BaseTools/Source/Python/AutoGen/GenMake.py @@ -166,7 +166,7 @@ class BuildFile(object): GMAKE_FILETYPE : "include" } =20 - _INC_FLAG_ =3D {TAB_COMPILER_MSFT : "/I", "GCC" : "-I", "INTEL" : "-I"= , "RVCT" : "-I", "NASM" : "-I"} + _INC_FLAG_ =3D {TAB_COMPILER_MSFT : "/I", "GCC" : "-I", "INTEL" : "-I"= , "NASM" : "-I"} =20 ## Constructor of BuildFile # diff --git a/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py b/BaseTools/S= ource/Python/AutoGen/ModuleAutoGen.py index 368a31047e82..d05410b32966 100755 --- a/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py +++ b/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py @@ -32,7 +32,7 @@ import tempfile ## Mapping Makefile type gMakeTypeMap =3D {TAB_COMPILER_MSFT:"nmake", "GCC":"gmake"} # -# Regular expression for finding Include Directories, the difference betwe= en MSFT and INTEL/GCC/RVCT +# Regular expression for finding Include Directories, the difference betwe= en MSFT and INTEL/GCC # is the former use /I , the Latter used -I to specify include directories # gBuildOptIncludePatternMsft =3D re.compile(r"(?:.*?)/I[ \t]*([^ ]*)", re.M= ULTILINE | re.DOTALL) @@ -684,12 +684,12 @@ class ModuleAutoGen(AutoGen): @cached_property def BuildOptionIncPathList(self): # - # Regular expression for finding Include Directories, the differen= ce between MSFT and INTEL/GCC/RVCT + # Regular expression for finding Include Directories, the differen= ce between MSFT and INTEL/GCC # is the former use /I , the Latter used -I to specify include dir= ectories # if self.PlatformInfo.ToolChainFamily in (TAB_COMPILER_MSFT): BuildOptIncludeRegEx =3D gBuildOptIncludePatternMsft - elif self.PlatformInfo.ToolChainFamily in ('INTEL', 'GCC', 'RVCT'): + elif self.PlatformInfo.ToolChainFamily in ('INTEL', 'GCC'): BuildOptIncludeRegEx =3D gBuildOptIncludePatternOther else: # @@ -704,16 +704,7 @@ class ModuleAutoGen(AutoGen): except KeyError: FlagOption =3D '' =20 - if self.ToolChainFamily !=3D 'RVCT': - IncPathList =3D [NormPath(Path, self.Macros) for Path in B= uildOptIncludeRegEx.findall(FlagOption)] - else: - # - # RVCT may specify a list of directory seperated by commas - # - IncPathList =3D [] - for Path in BuildOptIncludeRegEx.findall(FlagOption): - PathList =3D GetSplitList(Path, TAB_COMMA_SPLIT) - IncPathList.extend(NormPath(PathEntry, self.Macros) fo= r PathEntry in PathList) + IncPathList =3D [NormPath(Path, self.Macros) for Path in Build= OptIncludeRegEx.findall(FlagOption)] =20 # # EDK II modules must not reference header files outside of th= e packages they depend on or diff --git a/BaseTools/Source/Python/UPT/Library/DataType.py b/BaseTools/So= urce/Python/UPT/Library/DataType.py index bd216786a565..2033149aa6dc 100644 --- a/BaseTools/Source/Python/UPT/Library/DataType.py +++ b/BaseTools/Source/Python/UPT/Library/DataType.py @@ -939,7 +939,6 @@ MODEL_META_DATA_CONDITIONAL_STATEMENT_ENDIF =3D 5014 TOOL_FAMILY_LIST =3D ["MSFT", "INTEL", "GCC", - "RVCT" ] =20 TYPE_HOB_SECTION =3D 'HOB' --=20 2.35.3 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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