From nobody Sun Feb 8 12:38:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88737+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88737+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1649716362; cv=none; d=zohomail.com; s=zohoarc; b=jJlBg+pWiq9ySkWs2kTkb2toujcbyLO6vhva4m3s/+lMn7V2WtpLPoZy+HTAHeBcXri/d/FOka4wmsmclCMx2TmlzSZjeM3fvV4vJUduaJstiCbL0CLv6jFjdxeBgnJf0O+fAK5Cpaok6OfQaUgcq3N6UMTcR+tg72iVPppvoAY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649716362; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=uQUmFxBTpLRlXSCgDTIDIeq4yWp6VDWPL6N/a7i+PdE=; b=Jzsnth71vesAZjdD8X9Io3yEDiAL42OksDOhiIxnJI6+E11ACBfutXwUVmeXLvk4aoFgHDKRgoX/efGWlMYi2TwOTyZcE8ONbcp0paJCyNBwYaxhnpcgBhhhmN/SQWOxTl42UFNu2tkK8hLEgn72Urn9iN3PbCQvqMKYRpVGrD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88737+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1649716362962937.2470728424303; Mon, 11 Apr 2022 15:32:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 673DYY1788612xnVGlDsmh6J; Mon, 11 Apr 2022 15:32:42 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.27681.1649670388892280906 for ; Mon, 11 Apr 2022 02:46:30 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10313"; a="324989933" X-IronPort-AV: E=Sophos;i="5.90,251,1643702400"; d="scan'208";a="324989933" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2022 02:46:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,251,1643702400"; d="scan'208";a="507044991" X-Received: from shwdeopenlab704.ccr.corp.intel.com ([10.239.182.50]) by orsmga003.jf.intel.com with ESMTP; 11 Apr 2022 02:46:12 -0700 From: Yu Pu To: devel@edk2.groups.io Cc: Yu Pu , Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-devel] [PATCH v1 07/15] MdePkg: Move API and implementation from UefiCpuLib to CpuLib Date: Mon, 11 Apr 2022 17:45:47 +0800 Message-Id: <20220411094555.1375-8-yu.pu@intel.com> In-Reply-To: <20220411094555.1375-1-yu.pu@intel.com> References: <20220411094555.1375-1-yu.pu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yu.pu@intel.com X-Gm-Message-State: Stn5c6aAg1NSyFBmLULwdzhmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1649716362; bh=TNRF4io2Y2gyvCKkJphB5heBoWm7w6a3pPzYBttc9kM=; h=Cc:Date:From:Reply-To:Subject:To; b=rXVgiSGY9KzXRYY3a672PXMBEDU5dP7ZMjbN2s4ZTOEoUmIGnfCyBEQ+i95csNc3nNv 97FU27bpxGt0byo0mS5KYzV4oMQkIHqnG+rdjmKkotF4ir1ZNp5zr7GSAUyXQxcDLWlmF snxSZO3LiH/EKiS1jTw64FPBQbufkGEYH18= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1649716364856100044 Content-Type: text/plain; charset="utf-8" There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Yu Pu --- MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c | 75 ++++++++++++++++++++ MdePkg/Include/Library/CpuLib.h | 48 +++++++++++++ MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 ++ MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm | 68 ++++++++++++++++++ MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm | 51 +++++++++++++ 5 files changed, 248 insertions(+) diff --git a/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c b/MdePkg/Library/Bas= eCpuLib/X86BaseCpuLib.c new file mode 100644 index 000000000000..e69f00417022 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c @@ -0,0 +1,75 @@ +/** @file + This library defines some routines that are generic for IA32 family CPU. + The library routines are UEFI specification compliant. + Copyright (c) 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include +#include + +/** + Determine if the standard CPU signature is "AuthenticAMD". + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ) +{ + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && + RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && + RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); +} + +/** + Return the 32bit CPU family and model value. + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. +**/ +UINT32 +EFIAPI +GetCpuFamilyModel ( + VOID + ) +{ + CPUID_VERSION_INFO_EAX Eax; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + + // + // Mask other fields than Family and Model. + // + Eax.Bits.SteppingId =3D 0; + Eax.Bits.ProcessorType =3D 0; + Eax.Bits.Reserved1 =3D 0; + Eax.Bits.Reserved2 =3D 0; + return Eax.Uint32; +} + +/** + Return the CPU stepping ID. + @return CPU stepping ID value in CPUID[01h].EAX. +**/ +UINT8 +EFIAPI +GetCpuSteppingId ( + VOID + ) +{ + CPUID_VERSION_INFO_EAX Eax; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + + return (UINT8)Eax.Bits.SteppingId; +} diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLi= b.h index 25f6d9478c52..3f29937dc71b 100644 --- a/MdePkg/Include/Library/CpuLib.h +++ b/MdePkg/Include/Library/CpuLib.h @@ -41,4 +41,52 @@ CpuFlushTlb ( VOID ); =20 +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) + +/** + Initializes floating point units for requirement of UEFI specification. + This function initializes floating-point control word to 0x027F (all exc= eptions + masked,double-precision, round-to-nearest) and multimedia-extensions con= trol word + (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush= to zero + for masked underflow). +**/ +VOID +EFIAPI +InitializeFloatingPointUnits ( + VOID + ); + +/** + Determine if the standard CPU signature is "AuthenticAMD". + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ); + +/** + Return the 32bit CPU family and model value. + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. +**/ +UINT32 +EFIAPI +GetCpuFamilyModel ( + VOID + ); + +/** + Return the CPU stepping ID. + @return CPU stepping ID value in CPUID[01h].EAX. +**/ +UINT8 +EFIAPI +GetCpuSteppingId ( + VOID + ); + +#endif + #endif diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index 950f5229b2a4..7cdbb552c08c 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -28,6 +28,9 @@ # VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 +[Sources.IA32, Sources.X64] + X86BaseCpuLib.c + [Sources.IA32] Ia32/CpuSleep.c | MSFT Ia32/CpuFlushTlb.c | MSFT @@ -38,10 +41,13 @@ Ia32/CpuSleepGcc.c | GCC Ia32/CpuFlushTlbGcc.c | GCC =20 + Ia32/InitializeFpu.nasm + [Sources.X64] X64/CpuFlushTlb.nasm X64/CpuSleep.nasm =20 + X64/InitializeFpu.nasm =20 [Sources.EBC] Ebc/CpuSleepFlushTlb.c diff --git a/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm b/MdePkg/Lib= rary/BaseCpuLib/Ia32/InitializeFpu.nasm new file mode 100644 index 000000000000..5e27cc325012 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm @@ -0,0 +1,68 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + + SECTION .rodata + +; +; Float control word initial value: +; all exceptions masked, double-precision, round-to-nearest +; +mFpuControlWord: DW 0x27F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underf= low +; +mMmxControlWord: DD 0x1F80 + + SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exc= eptions +; masked,double-precision, round-to-nearest) and multimedia-extensions con= trol word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush= to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + push ebx + + ; + ; Initialize floating point units + ; + finit + fldcw [mFpuControlWord] + + ; + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test + ; whether the processor supports SSE instruction. + ; + mov eax, 1 + cpuid + bt edx, 25 + jnc Done + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov eax, cr4 + or eax, BIT9 + mov cr4, eax + + ; + ; The processor should support SSE instruction and we can use + ; ldmxcsr instruction + ; + ldmxcsr [mMmxControlWord] +Done: + pop ebx + + ret + diff --git a/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm b/MdePkg/Libr= ary/BaseCpuLib/X64/InitializeFpu.nasm new file mode 100644 index 000000000000..8485b4713548 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm @@ -0,0 +1,51 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + + SECTION .rodata +; +; Float control word initial value: +; all exceptions masked, double-extended-precision, round-to-nearest +; +mFpuControlWord: DW 0x37F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underf= low +; +mMmxControlWord: DD 0x1F80 + +DEFAULT REL +SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exc= eptions +; masked,double-precision, round-to-nearest) and multimedia-extensions con= trol word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush= to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + ; + ; Initialize floating point units + ; + finit + fldcw [mFpuControlWord] + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov rax, cr4 + or rax, BIT9 + mov cr4, rax + + ldmxcsr [mMmxControlWord] + + ret + --=20 2.30.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88737): https://edk2.groups.io/g/devel/message/88737 Mute This Topic: https://groups.io/mt/90407117/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-