From nobody Mon Feb 9 23:39:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88014+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88014+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1648192610; cv=none; d=zohomail.com; s=zohoarc; b=LiZfYrwUIv5MbmigjHDaiW53z9ZtIBWa3UGtFpHbKbq2l8KbTX6U/HPeVYwAlXPmHXDuf6RWRfOej2vqfSrQoOqcR05G3z6aOtzdukB2XkLFs5SjTbXX3oB1VxezU/Ii+JVmss2QcXjGLf6DeCDECvu1BqC5pL5XTNIc6PxXOtA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1648192610; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RgTiN0viHxEckZTtgSTGiAlfIidihCIB6U/JH/306J8=; b=Vf/R8+5dNlxfmFR+a/8qIkmXmcJZ0b3LS7lVQ5wNKHTWTgHE588GBUJ/lVe5uS1Uo18Al2wOd5fy+Gv3LvF2hLP0GT8XsCnFSLgBP8NubwLREFTJafqDevNtOiMMKiJfJ9TRYHuif8gVgj0nMHF69YeL2bJWx3XBY/akQ/7PhSA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88014+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1648192610603271.7175836741503; Fri, 25 Mar 2022 00:16:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XK4dYY1788612xKiL0aP6HwY; Fri, 25 Mar 2022 00:16:50 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.2324.1648192609318382827 for ; Fri, 25 Mar 2022 00:16:49 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P6QqU7032494; Fri, 25 Mar 2022 07:16:46 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3f18fqrg97-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Mar 2022 07:16:46 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 09047A1; Fri, 25 Mar 2022 07:16:46 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id CBCD147; Fri, 25 Mar 2022 07:16:43 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH V2 2/8] [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor architecture Date: Fri, 25 Mar 2022 14:12:43 +0800 Message-Id: <20220325061249.30626-3-abner.chang@hpe.com> In-Reply-To: <20220325061249.30626-1-abner.chang@hpe.com> References: <20220325061249.30626-1-abner.chang@hpe.com> X-Proofpoint-GUID: tX1NU2ChEIAuc3JccPBJo6BJcsZSHJB8 X-Proofpoint-ORIG-GUID: tX1NU2ChEIAuc3JccPBJo6BJcsZSHJB8 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 3GKN5WHKWXm6FMS49n1eoIVQx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1648192610; bh=sG/3TRmOX8Hu9a05nzImJBTdCFVgiQTfWeFTFQ56dhc=; h=Cc:Date:From:Reply-To:Subject:To; b=QP4ROklD8pBWqF4Fs3qeX8RhBQKFWY5qjR05tMQwEUiHh2YUJrSd4KgH5yo0bAF6GaJ YdD9+QfJdyz+J7ERNLbh0DzHIro8U5Yqm3IQY1kfOD6cT9rxaMBkVplhpy9HAr3s2mB3o chV3DziieDYY+zkEop4De0Hu39R/M3JlS2Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1648192611521100007 Content-Type: text/plain; charset="utf-8" (This is migrated from edk2-platforms:Silicon/RISC-V) https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 RISC-V processor architecture definitions. Signed-off-by: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- .../Include/IndustryStandard/RISC-V/RiscV.h | 162 ++++++++++++++++++ UefiCpuPkg/Include/RISC-V/RiscVImpl.h | 87 ++++++++++ 2 files changed, 249 insertions(+) create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h b/UefiCpuPk= g/Include/IndustryStandard/RISC-V/RiscV.h new file mode 100644 index 0000000000..3edd1e6263 --- /dev/null +++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h @@ -0,0 +1,162 @@ +/** @file + RISC-V processor architecture definitions. + + Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights= reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_INDUSTRY_STANDARD_H_ +#define RISCV_INDUSTRY_STANDARD_H_ + +#if defined (MDE_CPU_RISCV64) +#define RISC_V_XLEN_BITS 64 +#else +#endif + +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 = << 0) +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 = << 1) +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 = << 2) +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 = << 3) +#define RISC_V_ISA_RV32E_ISA (0x00000001 = << 4) +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 = << 5) +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 = << 6) +#define RISC_V_ISA_RESERVED_1 (0x00000001 = << 7) +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 = << 8) +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 = << 9) +#define RISC_V_ISA_RESERVED_2 (0x00000001 = << 10) +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 = << 11) +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 = << 12) +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 = << 13) +#define RISC_V_ISA_RESERVED_3 (0x00000001 = << 14) +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 = << 15) +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 = << 16) +#define RISC_V_ISA_RESERVED_4 (0x00000001 = << 17) +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 = << 18) +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 = << 19) +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 = << 20) +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 = << 21) +#define RISC_V_ISA_RESERVED_5 (0x00000001 = << 22) +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 = << 23) +#define RISC_V_ISA_RESERVED_6 (0x00000001 = << 24) +#define RISC_V_ISA_RESERVED_7 (0x00000001 = << 25) + +// +// RISC-V CSR definitions. +// +// +// Machine information +// +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 +#define RISCV_CSR_MACHINE_MARCHID 0xF12 +#define RISCV_CSR_MACHINE_MIMPID 0xF13 +#define RISCV_CSR_MACHINE_HARRID 0xF14 +// +// Machine Trap Setup. +// +#define RISCV_CSR_MACHINE_MSTATUS 0x300 +#define RISCV_CSR_MACHINE_MISA 0x301 +#define RISCV_CSR_MACHINE_MEDELEG 0x302 +#define RISCV_CSR_MACHINE_MIDELEG 0x303 +#define RISCV_CSR_MACHINE_MIE 0x304 +#define RISCV_CSR_MACHINE_MTVEC 0x305 + +#define RISCV_TIMER_COMPARE_BITS 32 +// +// Machine Timer and Counter. +// +// #define RISCV_CSR_MACHINE_MTIME 0x701 +// #define RISCV_CSR_MACHINE_MTIMEH 0x741 +// +// Machine Trap Handling. +// +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 +#define RISCV_CSR_MACHINE_MEPC 0x341 +#define RISCV_CSR_MACHINE_MCAUSE 0x342 +#define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f +#define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) +#define RISCV_CSR_MACHINE_MBADADDR 0x343 +#define RISCV_CSR_MACHINE_MIP 0x344 + +// +// Machine Protection and Translation. +// +#define RISCV_CSR_MACHINE_MBASE 0x380 +#define RISCV_CSR_MACHINE_MBOUND 0x381 +#define RISCV_CSR_MACHINE_MIBASE 0x382 +#define RISCV_CSR_MACHINE_MIBOUND 0x383 +#define RISCV_CSR_MACHINE_MDBASE 0x384 +#define RISCV_CSR_MACHINE_MDBOUND 0x385 + +// +// Supervisor mode CSR. +// +#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100 +#define SSTATUS_SIE_BIT_POSITION 1 +#define SSTATUS_SPP_BIT_POSITION 8 +#define RISCV_CSR_SUPERVISOR_SIE 0x104 +#define RISCV_CSR_SUPERVISOR_STVEC 0x105 +#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140 +#define RISCV_CSR_SUPERVISOR_SEPC 0x141 +#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142 +#define SCAUSE_USER_SOFTWARE_INT 0 +#define SCAUSE_SUPERVISOR_SOFTWARE_INT 1 +#define SCAUSE_USER_TIMER_INT 4 +#define SCAUSE_SUPERVISOR_TIMER_INT 5 +#define SCAUSE_USER_EXTERNAL_INT 8 +#define SCAUSE_SUPERVISOR_EXTERNAL_INT 9 +#define RISCV_CSR_SUPERVISOR_STVAL 0x143 +#define RISCV_CSR_SUPERVISOR_SIP 0x144 +#define RISCV_CSR_SUPERVISOR_SATP 0x180 + +#if defined (MDE_CPU_RISCV64) +#define RISCV_SATP_MODE_MASK 0xF000000000000000 +#define RISCV_SATP_MODE_BIT_POSITION 60 +#endif +#define RISCV_SATP_MODE_OFF 0 +#define RISCV_SATP_MODE_SV32 1 +#define RISCV_SATP_MODE_SV39 8 +#define RISCV_SATP_MODE_SV48 9 +#define RISCV_SATP_MODE_SV57 10 +#define RISCV_SATP_MODE_SV64 11 + +#define SATP64_ASID_MASK 0x0FFFF00000000000 +#define SATP64_PPN_MASK 0x00000FFFFFFFFFFF + +#define RISCV_CAUSE_MISALIGNED_FETCH 0x0 +#define RISCV_CAUSE_FETCH_ACCESS 0x1 +#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define RISCV_CAUSE_BREAKPOINT 0x3 +#define RISCV_CAUSE_MISALIGNED_LOAD 0x4 +#define RISCV_CAUSE_LOAD_ACCESS 0x5 +#define RISCV_CAUSE_MISALIGNED_STORE 0x6 +#define RISCV_CAUSE_STORE_ACCESS 0x7 +#define RISCV_CAUSE_USER_ECALL 0x8 +#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9 +#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa +#define RISCV_CAUSE_MACHINE_ECALL 0xb +#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc +#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd +#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf +#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +// +// Machine Read-Write Shadow of Hypervisor Read-Only Registers +// +#define RISCV_CSR_HTIMEW 0xB01 +#define RISCV_CSR_HTIMEHW 0xB81 +// +// Machine Host-Target Interface (Non-Standard Berkeley Extension) +// +#define RISCV_CSR_MTOHOST 0x780 +#define RISCV_CSR_MFROMHOST 0x781 + +// +// User mode CSR +// +#define RISCV_CSR_CYCLE 0xc00 +#define RISCV_CSR_TIME 0xc01 +#endif diff --git a/UefiCpuPkg/Include/RISC-V/RiscVImpl.h b/UefiCpuPkg/Include/RIS= C-V/RiscVImpl.h new file mode 100644 index 0000000000..e49095de3d --- /dev/null +++ b/UefiCpuPkg/Include/RISC-V/RiscVImpl.h @@ -0,0 +1,87 @@ +/** @file + RISC-V processor implementation definitions. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_H_ +#define RISCV_H_ + +#include +#include + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) + +#if defined (MDE_CPU_RISCV64) +typedef UINT64 RISC_V_REGS_PROTOTYPE; +#else +#endif + +// +// Structure for 128-bit value +// +typedef struct { + UINT64 Value64_L; + UINT64 Value64_H; +} RISCV_UINT128; + +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _EXCEPTION_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; + EFI_PHYSICAL_ADDRESS IllegalInstHander; + EFI_PHYSICAL_ADDRESS BreakpointHander; + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; +} EXCEPTION_HANDLER_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _INTERRUPT_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; + EFI_PHYSICAL_ADDRESS TimerIntHandler; +} INTERRUPT_HANDLER_CONTEXT; + +/// +/// Interrupt handlers in context. +/// +typedef struct _TRAP_HANDLER_CONTEXT { + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; +} TRAP_HANDLER_CONTEXT; + +/// +/// Machine mode context used for saveing hart-local context. +/// +typedef struct _RISCV_MACHINE_MODE_CONTEXT { + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap= handler. + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode t= rap handler. + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode t= rap handler. + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap ha= ndler. + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machi= ne mode. +} RISCV_MACHINE_MODE_CONTEXT; + +#endif --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88014): https://edk2.groups.io/g/devel/message/88014 Mute This Topic: https://groups.io/mt/90017679/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-