From nobody Mon Feb 9 16:45:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87738+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87738+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1647586034; cv=none; d=zohomail.com; s=zohoarc; b=RGtM71jpTDeTNnvci5kb60qx1NNfPzBvOebstRuOmVj0bPF+UPbnvMuBQUyKlHgRxlo9HdWKBvR2J0ScgLeGHlCKNWpaUTxFUeTjOiFQdEdxmIjamwLPfMyKPyeDXV8aPiryApBv3cWncYTE7Tc3kOY/kPLay1TVZU5NQP8A5LY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647586034; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3VKeWUjnsNLuF4X6wl0Ools4vwfZQUSD0VKaLE5T+I8=; b=IRKQpBA4krdCbPyq5PPppYMt45VrQ+xKu2k3J8i/AL/fDPkms1nfjQTXq+XKWSD3T9265kL0zz94toPcjpbA+t0d4tdUU0sIgubHefYUjXNTxnn+eTJcmGF2sl4Cm2WZp59vmClJINAsntckzu9xG7aEqYuuP00rDSbIet4sNMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87738+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1647586034841231.15449683728082; Thu, 17 Mar 2022 23:47:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LiJoYY1788612x4TikkdHThP; Thu, 17 Mar 2022 23:47:14 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.6742.1647586033467642544 for ; Thu, 17 Mar 2022 23:47:13 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I0WSE9017538; Fri, 18 Mar 2022 06:47:11 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3eve38u9kd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:11 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id B94D58D; Fri, 18 Mar 2022 06:47:10 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 524B04B; Fri, 18 Mar 2022 06:47:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 5/6] [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib Date: Fri, 18 Mar 2022 13:43:21 +0800 Message-Id: <20220318054322.11520-6-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: mOXCWNG3gSpD7LGUpgl4koH25k_f2Cu_ X-Proofpoint-GUID: mOXCWNG3gSpD7LGUpgl4koH25k_f2Cu_ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: r7p7gR3G4kdOQvN7uPIAih8Rx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586034; bh=AAPZig6gsyRZkyNVYa9XhUBiWBp0kd06EfVMFUNbz/s=; h=Cc:Date:From:Reply-To:Subject:To; b=RvA7ojRN7ejpSgXBqjyc3FjZVuX9SkwTk/b81Ur6SGcGW0InWn+GXUptnxIXIoo1eQy yrOUFVMmbKceCdP+OQ1VFYH0I8vmZA3YUqdnqAwoI7erUmhXRT7PzScrWbTI+xhYxAjtj gEZao32KmY+0XVT1a4HC2b12tAvNM3roFII= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1647586035619100002 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 (This is migrated from edk2-platforms:Silicon/RISC-V) EDK2 RISC-V OpenSBI library which pull in external source files under UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi to the build process. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dec | 12 ++- UefiCpuPkg/UefiCpuPkg.dsc | 6 ++ .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 +++++++++++++++++++ .../IndustryStandard/RISC-V/RiscVOpensbi.h | 62 +++++++++++++ UefiCpuPkg/Include/RISC-V/OpensbiTypes.h | 82 +++++++++++++++++ BaseTools/Conf/tools_def.template | 2 +- 6 files changed, 250 insertions(+), 3 deletions(-) create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiL= ib.inf create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi= .h create mode 100644 UefiCpuPkg/Include/RISC-V/OpensbiTypes.h diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 525cde4634..8e85d242a3 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,7 +1,8 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,9 +15,16 @@ PACKAGE_GUID =3D 2171df9b-0d39-45aa-ac37-2de190010d23 PACKAGE_VERSION =3D 0.90 =20 -[Includes] +[Includes.common] Include =20 +[Includes.RISCV64] + Include/Library + Library/RISC-V/RiscVOpensbiLib/opensbi # OpenSBI header file ref= erence ("include/sbi/...") + Library/RISC-V/RiscVOpensbiLib/opensbi/include # Header file reference f= rom opensbi files, ("sbi/...") + Library/RISC-V/RiscVOpensbiLib/opensbi/platform/generic/include # Header= file reference from opensbi files, ("sbi/...") + + [LibraryClasses] ## @libraryclass Defines some routines that are generic for IA32 famil= y CPU ## to be UEFI specification compliant. diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 50c9fc294c..374e951f29 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -66,6 +66,9 @@ MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezv= ousLib.inf =20 +[LibraryClasses.RISCV64] + RiscVOpensbiLib|UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLi= b.inf + [LibraryClasses.common.SEC] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf @@ -185,5 +188,8 @@ UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf =20 +[Components.RISCV64] + UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf + [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf = b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf new file mode 100644 index 0000000000..54eed050d4 --- /dev/null +++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -0,0 +1,89 @@ +## @file +# RISC-V Opensbi Library Instance. +# +# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVOpensbiLib + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVOpensbiLib + +[Sources] + opensbi/lib/sbi/riscv_asm.c + opensbi/lib/sbi/riscv_atomic.c + opensbi/lib/sbi/riscv_hardfp.S + opensbi/lib/sbi/riscv_locks.c + opensbi/lib/sbi/sbi_bitmap.c + opensbi/lib/sbi/sbi_bitops.c + opensbi/lib/sbi/sbi_console.c + opensbi/lib/sbi/sbi_domain.c + opensbi/lib/sbi/sbi_ecall.c + opensbi/lib/sbi/sbi_ecall_base.c + opensbi/lib/sbi/sbi_ecall_hsm.c + opensbi/lib/sbi/sbi_ecall_legacy.c + opensbi/lib/sbi/sbi_ecall_replace.c + opensbi/lib/sbi/sbi_ecall_vendor.c + opensbi/lib/sbi/sbi_emulate_csr.c + opensbi/lib/sbi/sbi_fifo.c + opensbi/lib/sbi/sbi_hart.c + opensbi/lib/sbi/sbi_math.c + opensbi/lib/sbi/sbi_hfence.S + opensbi/lib/sbi/sbi_hsm.c + opensbi/lib/sbi/sbi_illegal_insn.c + opensbi/lib/sbi/sbi_init.c + opensbi/lib/sbi/sbi_ipi.c + opensbi/lib/sbi/sbi_misaligned_ldst.c + opensbi/lib/sbi/sbi_platform.c + opensbi/lib/sbi/sbi_scratch.c + opensbi/lib/sbi/sbi_string.c + opensbi/lib/sbi/sbi_system.c + opensbi/lib/sbi/sbi_timer.c + opensbi/lib/sbi/sbi_tlb.c + opensbi/lib/sbi/sbi_trap.c + opensbi/lib/sbi/sbi_unpriv.c + opensbi/lib/sbi/sbi_expected_trap.S + + opensbi/lib/utils/fdt/fdt_helper.c + opensbi/lib/utils/fdt/fdt_fixup.c + opensbi/lib/utils/fdt/fdt_domain.c + opensbi/lib/utils/ipi/fdt_ipi.c + opensbi/lib/utils/ipi/aclint_mswi.c + opensbi/lib/utils/ipi/fdt_ipi_mswi.c + opensbi/lib/utils/irqchip/fdt_irqchip.c + opensbi/lib/utils/irqchip/fdt_irqchip_plic.c + opensbi/lib/utils/irqchip/plic.c + opensbi/lib/utils/reset/fdt_reset.c + opensbi/lib/utils/reset/fdt_reset_htif.c + opensbi/lib/utils/reset/fdt_reset_sifive.c + opensbi/lib/utils/reset/fdt_reset_thead.c + opensbi/lib/utils/reset/fdt_reset_thead_asm.S + opensbi/lib/utils/serial/fdt_serial.c + opensbi/lib/utils/serial/fdt_serial_htif.c + opensbi/lib/utils/serial/fdt_serial_shakti.c + opensbi/lib/utils/serial/fdt_serial_sifive.c + opensbi/lib/utils/serial/fdt_serial_uart8250.c + opensbi/lib/utils/serial/fdt_serial_gaisler.c + opensbi/lib/utils/serial/gaisler-uart.c + opensbi/lib/utils/serial/shakti-uart.c + opensbi/lib/utils/serial/sifive-uart.c + opensbi/lib/utils/serial/uart8250.c + opensbi/lib/utils/sys/htif.c + opensbi/lib/utils/sys/sifive_test.c + opensbi/lib/utils/timer/fdt_timer.c + opensbi/lib/utils/timer/aclint_mtimer.c + opensbi/lib/utils/timer/fdt_timer_mtimer.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec # For libfdt. + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[BuildOptions] + GCC:*_*_*_PP_FLAGS =3D -D__ASSEMBLY__ diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h b/Ue= fiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h new file mode 100644 index 0000000000..db57aeeb37 --- /dev/null +++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h @@ -0,0 +1,62 @@ +/** @file + SBI inline function calls. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EDK2_SBI_H_ +#define EDK2_SBI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS + +typedef +VOID +(EFIAPI *RISCV_HART_SWITCH_MODE)( + IN UINTN FuncArg0, + IN UINTN FuncArg1, + IN UINTN NextAddr, + IN UINTN NextMode, + IN BOOLEAN NextVirt + ); + +// +// Keep the structure member in 64-bit alignment. +// +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension th= is core supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture= ID + RISCV_UINT128 MachineImplId; // Machine Implementati= on ID + RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size = of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC + // structure. Referr= ed by both C code and assembly code. + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI = Service table + UINT64 FlattenedDeviceTree; // Poin= ter to Flattened Device tree + UINT64 SecPeiHandOffData; // This= is EFI_SEC_PEI_HAND_OFF passed to PEI Core. + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HAR= T_SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +// +// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines +// +typedef struct sbi_scratch SBI_SCRATCH; +typedef struct sbi_platform SBI_PLATFORM; + +#endif diff --git a/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h b/UefiCpuPkg/Include/= RISC-V/OpensbiTypes.h new file mode 100644 index 0000000000..918cf686fc --- /dev/null +++ b/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h @@ -0,0 +1,82 @@ +/** @file + RISC-V OpenSBI header file reference. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EDK2_SBI_TYPES_H_ +#define EDK2_SBI_TYPES_H_ + +#include + +typedef INT8 s8; +typedef UINT8 u8; +typedef UINT8 uint8_t; + +typedef INT16 s16; +typedef UINT16 u16; +typedef INT16 int16_t; +typedef UINT16 uint16_t; + +typedef INT32 s32; +typedef UINT32 u32; +typedef INT32 int32_t; +typedef UINT32 uint32_t; + +typedef INT64 s64; +typedef UINT64 u64; +typedef INT64 int64_t; +typedef UINT64 uint64_t; + +// PRILX is not used in EDK2 but we need to define it here because when +// defining our own types, this constant is not defined but used by OpenSB= I. +#define PRILX "016lx" + +typedef BOOLEAN bool; +typedef unsigned long ulong; +typedef UINT64 uintptr_t; +typedef UINT64 size_t; +typedef INT64 ssize_t; +typedef UINT64 virtual_addr_t; +typedef UINT64 virtual_size_t; +typedef UINT64 physical_addr_t; +typedef UINT64 physical_size_t; + +#define true TRUE +#define false FALSE + +#define __packed __attribute__((packed)) +#define __noreturn __attribute__((noreturn)) +#define __aligned(x) __attribute__((aligned(x))) + +#if defined (__GNUC__) || defined (__clang__) +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) +#else +#define likely(x) (x) +#define unlikely(x) (x) +#endif + +#undef offsetof +#ifdef __compiler_offsetof +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER) +#else +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#endif + +#define container_of(ptr, type, member) ({ \ + const typeof(((type *)0)->member) * __mptr =3D (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) + +#define array_size(x) (sizeof(x) / sizeof((x)[0])) + +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) +#define ROUNDDOWN(a, b) ((a) / (b) * (b)) + +/* clang-format on */ + +#endif diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 9c310cf23d..32af0bd15e 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -1978,7 +1978,7 @@ DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS =3D= -Wl,--defsym=3DPECOFF_HEADER_S DEFINE GCC5_RISCV_ALL_ASM_FLAGS =3D -c -x assembler -ima= cros $(DEST_DIR_DEBUG)/AutoGen.h DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE =3D -Wno-tautological-co= mpare -Wno-pointer-compare =20 -DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DOpensbiTypes.h +DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DRISC-V/OpensbiTypes.h =20 DEFINE GCC5_RISCV64_ARCH =3D rv64imafdc DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_CO= MMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87738): https://edk2.groups.io/g/devel/message/87738 Mute This Topic: https://groups.io/mt/89863236/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-