From nobody Mon Feb 9 15:11:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87736+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87736+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1647586027133851.8051539386165; Thu, 17 Mar 2022 23:47:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sJh1YY1788612xf7mVsh23mA; Thu, 17 Mar 2022 23:47:08 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.6846.1647586027432021580 for ; Thu, 17 Mar 2022 23:47:07 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I5OxwD031962; Fri, 18 Mar 2022 06:47:05 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3ev99adp6t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:05 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 029729A; Fri, 18 Mar 2022 06:47:05 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 8C65B48; Fri, 18 Mar 2022 06:47:02 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 3/6] [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace Date: Fri, 18 Mar 2022 13:43:19 +0800 Message-Id: <20220318054322.11520-4-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: ttEXWDjnIFQy3J7qE_GnhX4atS-K18bp X-Proofpoint-GUID: ttEXWDjnIFQy3J7qE_GnhX4atS-K18bp X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: w43eUbBd7qAki3uJ6BhTkB0Ox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586028; bh=Bctk/VTdPZxkzUyy7d7VJl6GOuCD9NE9BqvyKqeuh4w=; h=Cc:Date:From:Reply-To:Subject:To; b=Edw23TRI83/W8ogmC3+qmJK4K2shI+Ul2vdhIf75hrT32kCJS2wM85uPywfoy60229d g+MBRJsfKGKVkzSb3gp3fDVTFNrSj7CzWUIDP8FxhzLizRGITJ7EENglX4E+FSSffsrQ3 dvwBv7ZTidI75GzzfkMTq56ONE15PVyaCRE= X-ZohoMail-DKIM: fail (Signature date is -1 seconds in the future.) X-ZM-MESSAGEID: 1647586046432100004 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 Add BaseUefiCpuLib instance for RISC-V RISCV64 arch. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dsc | 7 +- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +- .../Include/Library/RISC-V/RiscVCpuLib.h | 118 +++++++++++++++ .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni | 5 +- .../Library/BaseUefiCpuLib/RISCV64/Cpu.S | 143 ++++++++++++++++++ 5 files changed, 274 insertions(+), 7 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 6b43ff6822..50c9fc294c 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -14,7 +14,7 @@ PLATFORM_VERSION =3D 0.90 DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/UefiCpu - SUPPORTED_ARCHITECTURES =3D IA32|X64 + SUPPORTED_ARCHITECTURES =3D IA32|X64|RISCV64 BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT =20 @@ -55,9 +55,9 @@ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf =20 [LibraryClasses.IA32, LibraryClasses.X64] - UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf @@ -120,6 +120,8 @@ # # Drivers/Libraries within this package # +[Components.common] + UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf =20 [Components.IA32, Components.X64] UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf @@ -144,7 +146,6 @@ UefiCpuPkg/CpuIo2Smm/CpuIo2StandaloneMm.inf UefiCpuPkg/CpuMpPei/CpuMpPei.inf UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf - UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf index 34d3a7bb43..f43498e9b4 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf @@ -5,6 +5,7 @@ # # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2020, AMD Inc. All rights reserved.
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -21,7 +22,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.IA32] @@ -30,9 +31,12 @@ [Sources.X64] X64/InitializeFpu.nasm =20 -[Sources] +[Sources.IA32, Sources.X64] BaseUefiCpuLib.c =20 +[Sources.RISCV64] + RISCV64/Cpu.S + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h b/UefiCpuPkg/I= nclude/Library/RISC-V/RiscVCpuLib.h new file mode 100644 index 0000000000..610456d0be --- /dev/null +++ b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h @@ -0,0 +1,118 @@ +/** @file + RISC-V CPU library definitions. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RISCV_CPU_LIB_H_ +#define RISCV_CPU_LIB_H_ + +#include "RiscVImpl.h" + +/** + RISCV_TRAP_HANDLER +**/ +typedef +VOID +(EFIAPI *RISCV_TRAP_HANDLER)( + VOID + ); + +VOID +RiscVSetMachineScratch ( + RISCV_MACHINE_MODE_CONTEXT *RiscvContext + ); + +UINT32 +RiscVGetMachineScratch ( + VOID + ); + +UINT32 +RiscVGetMachineTrapCause ( + VOID + ); + +UINT64 +RiscVReadMachineTimer ( + VOID + ); + +UINT64 +RiscVReadMachineTimerInterface ( + VOID + ); + +VOID + RiscVSetMachineTimerCmp (UINT64); + +UINT64 +RiscVReadMachineTimerCmp ( + VOID + ); + +UINT64 +RiscVReadMachineInterruptEnable ( + VOID + ); + +UINT64 +RiscVReadMachineInterruptPending ( + VOID + ); + +UINT64 +RiscVReadMachineStatus ( + VOID + ); + +VOID + RiscVWriteMachineStatus (UINT64); + +UINT64 +RiscVReadMachineTrapVector ( + VOID + ); + +UINT64 +RiscVReadMachineIsa ( + VOID + ); + +UINT64 +RiscVReadMachineVendorId ( + VOID + ); + +UINT64 +RiscVReadMachineArchitectureId ( + VOID + ); + +UINT64 +RiscVReadMachineImplementId ( + VOID + ); + +VOID + RiscVSetSupervisorAddressTranslationRegister (UINT64); + +VOID + RiscVSetSupervisorScratch (UINT64); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID + RiscVSetSupervisorStvec (UINT64); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +#endif diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni index 83c96cea67..a94bbef53e 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni @@ -4,13 +4,14 @@ // The library routines are UEFI specification compliant. // // Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+// Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // // **/ =20 =20 -#string STR_MODULE_ABSTRACT #language en-US "Defines generic r= outines for IA32 family CPUs." +#string STR_MODULE_ABSTRACT #language en-US "Base CPU library." =20 -#string STR_MODULE_DESCRIPTION #language en-US "The library routi= nes comply with the UEFI Specification." +#string STR_MODULE_DESCRIPTION #language en-US "Base CPU library = provides generic routines for specific CPU architecture." =20 diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S b/UefiCpuPkg/L= ibrary/BaseUefiCpuLib/RISCV64/Cpu.S new file mode 100644 index 0000000000..5bc31744db --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S @@ -0,0 +1,143 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V CPU functions. +// +// Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All right= s reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include +#include + +.data + +.text +.align 3 + +// +// Set machine mode scratch. +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_FUNC (RiscVSetMachineScratch) + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0 + ret + +// +// Get machine mode scratch. +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_FUNC (RiscVGetMachineScratch) + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0 + ret + +// +// Get machine trap cause CSR. +// +ASM_FUNC (RiscVGetMachineTrapCause) + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0 + ret + +// +// Get machine interrupt enable +// +ASM_FUNC (RiscVReadMachineInterruptEnable) + csrr a0, RISCV_CSR_MACHINE_MIE + ret + +// +// Get machine interrupt pending +// +ASM_FUNC (RiscVReadMachineInterruptPending) + csrr a0, RISCV_CSR_MACHINE_MIP + ret + +// +// Get machine status +// +ASM_FUNC (RiscVReadMachineStatus) + csrr a0, RISCV_CSR_MACHINE_MSTATUS + ret + +// +// Set machine status +// +ASM_FUNC (RiscVWriteMachineStatus) + csrw RISCV_CSR_MACHINE_MSTATUS, a0 + ret + +// +// Get machine trap vector +// +ASM_FUNC (RiscVReadMachineTrapVector) + csrr a0, RISCV_CSR_MACHINE_MTVEC + ret + +// +// Read machine ISA +// +ASM_FUNC (RiscVReadMachineIsa) + csrr a0, RISCV_CSR_MACHINE_MISA + ret + +// +// Read machine vendor ID +// +ASM_FUNC (RiscVReadMachineVendorId) + csrr a0, RISCV_CSR_MACHINE_MVENDORID + ret + +// +// Read machine architecture ID +// +ASM_FUNC (RiscVReadMachineArchitectureId) + csrr a0, RISCV_CSR_MACHINE_MARCHID + ret + +// +// Read machine implementation ID +// +ASM_FUNC (RiscVReadMachineImplementId) + csrr a0, RISCV_CSR_MACHINE_MIMPID + ret + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH + ret + +// +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, RISCV_CSR_SUPERVISOR_STVEC + ret + +// +// Set Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) + csrw RISCV_CSR_SUPERVISOR_SATP, a0 + ret + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87736): https://edk2.groups.io/g/devel/message/87736 Mute This Topic: https://groups.io/mt/89863233/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-