From nobody Mon Feb 9 00:19:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86019+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86019+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1643036038; cv=none; d=zohomail.com; s=zohoarc; b=ZLBF15iDtDiDGdhBxftkSmmUlAyQraRrlDbKmVWguJQE8ofQ3jSYKso4jDy8XXXUlihg7PB+cA1Yi9CvvXtSNIh1FuUp/USfEBvwMdZkf/1s62DbMZeIg4Hx6aPyx6BYEIQ0QTFxF7Mnyw819uXY2s/o5T+7rJWraj982FPc8Lw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1643036038; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Byd7w5ZliDkNoVyCFIHYf+dVtVitM2iGreBErBULY5I=; b=X4Ca2xorZqoPRsWGocWSUtIOr9qG4UyUO5+oAqNzqFEhCwWKPA5tspYntUPV71VqUWMTcKzS8P8h66a+b3Qt/gRnk5b/M1HzDXRSfCLkdM5cX4azBkmlMbIwpDhuO+Nq9GBsPTsb9Zl5z0AA9AGLlrK8KvreFvtasohKL2TzzJI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86019+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1643036038969952.4024562742901; Mon, 24 Jan 2022 06:53:58 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id qk2xYY1788612xhJXT2wCi8Q; Mon, 24 Jan 2022 06:53:58 -0800 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.4517.1643036037542219462 for ; Mon, 24 Jan 2022 06:53:57 -0800 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20ODISA7023608; Mon, 24 Jan 2022 14:53:54 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3dspjfkywg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Jan 2022 14:53:54 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 3EBEEB0; Mon, 24 Jan 2022 14:53:53 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 4E43540; Mon, 24 Jan 2022 14:53:51 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L , Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [PATCH 2/2] ArmVirtPkg/BaseCachingPciExpressLib: Remove BaseCachingPciExpressLib Date: Mon, 24 Jan 2022 21:52:09 +0800 Message-Id: <20220124135209.8371-3-abner.chang@hpe.com> In-Reply-To: <20220124135209.8371-1-abner.chang@hpe.com> References: <20220124135209.8371-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: YPNNl-RqVWXADjuWoFKSwvf7cNjBMthQ X-Proofpoint-GUID: YPNNl-RqVWXADjuWoFKSwvf7cNjBMthQ X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: EwgqIw0Ak5RrImF7eybfUf36x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1643036038; bh=jAQZxYXK6xYkDpxiqt9XaRC9aK6ohNvaLw3nI8KqC0k=; h=Cc:Date:From:Reply-To:Subject:To; b=LDsqtjbtyilgdOG+fjLv2lAgpBMV2RGKbkDgVe45B99gr8DLezdKRVvUj3NISygdWVs +fLEF9Lmz7/vfAnZzIbnJlkTR6aULf901i5Xe9q7x77vksrKeIwUM3Na1UH0oA8WokjPE NDlk5JpuL6r4mgBnmJt1qIOD7b0gx+X78uQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1643036040904100013 Content-Type: text/plain; charset="utf-8" Remove BaseCachingPciExpressLib library from ArmVirtPkg and use the one und= er OvmfPkg instead. BaseCachingPciExpressLib is cloned to under OvmfPkg, with this change the R= ISC-V Virt platform can leverage the same library. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann --- ArmVirtPkg/ArmVirt.dsc.inc | 2 +- ArmVirtPkg/ArmVirtKvmTool.dsc | 6 +- .../BaseCachingPciExpressLib.inf | 43 - .../BaseCachingPciExpressLib/PciExpressLib.c | 1420 ----------------- 4 files changed, 4 insertions(+), 1467 deletions(-) delete mode 100644 ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCaching= PciExpressLib.inf delete mode 100644 ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressL= ib.c diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc index 5a1598d90c..4db8ad5a79 100644 --- a/ArmVirtPkg/ArmVirt.dsc.inc +++ b/ArmVirtPkg/ArmVirt.dsc.inc @@ -141,7 +141,7 @@ =20 # PCI Libraries PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf - PciExpressLib|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPci= ExpressLib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc index 9d23072d8f..4a54d13735 100644 --- a/ArmVirtPkg/ArmVirtKvmTool.dsc +++ b/ArmVirtPkg/ArmVirtKvmTool.dsc @@ -339,17 +339,17 @@ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf { NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf - NULL|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpre= ssLib.inf + NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressL= ib.inf } MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf - NULL|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpre= ssLib.inf + NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressL= ib.inf } MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf - NULL|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpre= ssLib.inf + NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressL= ib.inf } OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf OvmfPkg/Virtio10Dxe/Virtio10.inf diff --git a/ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpr= essLib.inf b/ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpr= essLib.inf deleted file mode 100644 index 33568f568f..0000000000 --- a/ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.= inf +++ /dev/null @@ -1,43 +0,0 @@ -## @file -# Instance of PCI Express Library using the 256 MB PCI Express MMIO windo= w. -# -# PCI Express Library that uses the 256 MB PCI Express MMIO window to per= form -# PCI Configuration cycles. Layers on top of an I/O Library instance. -# -# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D BaseCachingPciExpressLib - FILE_GUID =3D 3f3ffd80-04dc-4a2b-9d25-ecca55c2e520 - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D PciExpressLib|DXE_DRIVER UEFI_DRIVER = UEFI_APPLICATION - CONSTRUCTOR =3D PciExpressLibInitialize - -# -# VALID_ARCHITECTURES =3D ARM AARCH64 -# - -[Sources] - PciExpressLib.c - -[Packages] - ArmVirtPkg/ArmVirtPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - BaseLib - PcdLib - DebugLib - IoLib - PciPcdProducerLib - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - diff --git a/ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressLib.c b/= ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressLib.c deleted file mode 100644 index 2474128697..0000000000 --- a/ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressLib.c +++ /dev/null @@ -1,1420 +0,0 @@ -/** @file - Functions in this library instance make use of MMIO functions in IoLib to - access memory mapped PCI configuration space. - - All assertions for I/O operations are handled in MMIO functions in the I= oLib - Library. - - Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -#include -#include -#include -#include -#include - -/** - Assert the validity of a PCI address. A valid PCI address should contain= 1's - only in the low 28 bits. - - @param A The address to validate. - -**/ -#define ASSERT_INVALID_PCI_ADDRESS(A) \ - ASSERT (((A) & ~0xfffffff) =3D=3D 0) - -/** - Registers a PCI device so PCI configuration registers may be accessed af= ter - SetVirtualAddressMap(). - - Registers the PCI device specified by Address so all the PCI configurati= on - registers associated with that PCI device may be accessed after SetVirtu= alAddressMap() - is called. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - - @retval RETURN_SUCCESS The PCI device was registered for runti= me access. - @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on - after ExitBootServices(). - @retval RETURN_UNSUPPORTED The resources required to access the PC= I device - at runtime could not be mapped. - @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to - complete the registration. - -**/ -RETURN_STATUS -EFIAPI -PciExpressRegisterForRuntimeAccess ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return RETURN_UNSUPPORTED; -} - -STATIC UINT64 mPciExpressBaseAddress; - -RETURN_STATUS -EFIAPI -PciExpressLibInitialize ( - VOID - ) -{ - mPciExpressBaseAddress =3D PcdGet64 (PcdPciExpressBaseAddress); - return RETURN_SUCCESS; -} - -/** - Gets the base address of PCI Express. - - @return The base address of PCI Express. - -**/ -VOID * -GetPciExpressBaseAddress ( - VOID - ) -{ - return (VOID *)(UINTN)mPciExpressBaseAddress; -} - -/** - Reads an 8-bit PCI configuration register. - - Reads and returns the 8-bit PCI configuration register specified by Addr= ess. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - - @return The read value from the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressRead8 ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioRead8 ((UINTN)GetPciExpressBaseAddress () + Address); -} - -/** - Writes an 8-bit PCI configuration register. - - Writes the 8-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressWrite8 ( - IN UINTN Address, - IN UINT8 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioWrite8 ((UINTN)GetPciExpressBaseAddress () + Address, Value); -} - -/** - Performs a bitwise OR of an 8-bit PCI configuration register with - an 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, perform= s a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration registe= r is - returned. This function must guarantee that all PCI read and write opera= tions - are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressOr8 ( - IN UINTN Address, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioOr8 ((UINTN)GetPciExpressBaseAddress () + Address, OrData); -} - -/** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit - value. - - Reads the 8-bit PCI configuration register specified by Address, perform= s a - bitwise AND between the read result and the value specified by AndData, = and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressAnd8 ( - IN UINTN Address, - IN UINT8 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAnd8 ((UINTN)GetPciExpressBaseAddress () + Address, AndData); -} - -/** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit - value, followed a bitwise OR with another 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, perform= s a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that al= l PCI - read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressAndThenOr8 ( - IN UINTN Address, - IN UINT8 AndData, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAndThenOr8 ( - (UINTN)GetPciExpressBaseAddress () + Address, - AndData, - OrData - ); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..7. - - @return The value of the bit field read from the PCI configuration regis= ter. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldRead8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldRead8 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit - ); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of t= he - 8-bit register is returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..7. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldWrite8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldWrite8 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - Value - ); -} - -/** - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and - writes the result back to the bit field in the 8-bit port. - - Reads the 8-bit PCI configuration register specified by Address, perform= s a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration registe= r is - returned. This function must guarantee that all PCI read and write opera= tions - are serialized. Extra left bits in OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..7. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldOr8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldOr8 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - OrData - ); -} - -/** - Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise - AND, and writes the result back to the bit field in the 8-bit register. - - Reads the 8-bit PCI configuration register specified by Address, perform= s a - bitwise AND between the read result and the value specified by AndData, = and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..7. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldAnd8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAnd8 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - AndData - ); -} - -/** - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 8-bit port. - - Reads the 8-bit PCI configuration register specified by Address, perform= s a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that al= l PCI - read and write operations are serialized. Extra left bits in both AndDat= a and - OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..7. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldAndThenOr8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAndThenOr8 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - AndData, - OrData - ); -} - -/** - Reads a 16-bit PCI configuration register. - - Reads and returns the 16-bit PCI configuration register specified by Add= ress. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - - @return The read value from the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressRead16 ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioRead16 ((UINTN)GetPciExpressBaseAddress () + Address); -} - -/** - Writes a 16-bit PCI configuration register. - - Writes the 16-bit PCI configuration register specified by Address with t= he - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressWrite16 ( - IN UINTN Address, - IN UINT16 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioWrite16 ((UINTN)GetPciExpressBaseAddress () + Address, Value); -} - -/** - Performs a bitwise OR of a 16-bit PCI configuration register with - a 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration registe= r is - returned. This function must guarantee that all PCI read and write opera= tions - are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressOr16 ( - IN UINTN Address, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioOr16 ((UINTN)GetPciExpressBaseAddress () + Address, OrData); -} - -/** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit - value. - - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND between the read result and the value specified by AndData, = and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressAnd16 ( - IN UINTN Address, - IN UINT16 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAnd16 ((UINTN)GetPciExpressBaseAddress () + Address, AndData); -} - -/** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit - value, followed a bitwise OR with another 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that al= l PCI - read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressAndThenOr16 ( - IN UINTN Address, - IN UINT16 AndData, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAndThenOr16 ( - (UINTN)GetPciExpressBaseAddress () + Address, - AndData, - OrData - ); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..15. - - @return The value of the bit field read from the PCI configuration regis= ter. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldRead16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldRead16 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit - ); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of t= he - 16-bit register is returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..15. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldWrite16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldWrite16 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - Value - ); -} - -/** - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, = and - writes the result back to the bit field in the 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration registe= r is - returned. This function must guarantee that all PCI read and write opera= tions - are serialized. Extra left bits in OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..15. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldOr16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldOr16 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - OrData - ); -} - -/** - Reads a bit field in a 16-bit PCI configuration register, performs a bit= wise - AND, and writes the result back to the bit field in the 16-bit register. - - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND between the read result and the value specified by AndData, = and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldAnd16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAnd16 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - AndData - ); -} - -/** - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that al= l PCI - read and write operations are serialized. Extra left bits in both AndDat= a and - OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldAndThenOr16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAndThenOr16 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - AndData, - OrData - ); -} - -/** - Reads a 32-bit PCI configuration register. - - Reads and returns the 32-bit PCI configuration register specified by Add= ress. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - - @return The read value from the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressRead32 ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioRead32 ((UINTN)GetPciExpressBaseAddress () + Address); -} - -/** - Writes a 32-bit PCI configuration register. - - Writes the 32-bit PCI configuration register specified by Address with t= he - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressWrite32 ( - IN UINTN Address, - IN UINT32 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioWrite32 ((UINTN)GetPciExpressBaseAddress () + Address, Value); -} - -/** - Performs a bitwise OR of a 32-bit PCI configuration register with - a 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration registe= r is - returned. This function must guarantee that all PCI read and write opera= tions - are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressOr32 ( - IN UINTN Address, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioOr32 ((UINTN)GetPciExpressBaseAddress () + Address, OrData); -} - -/** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit - value. - - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND between the read result and the value specified by AndData, = and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressAnd32 ( - IN UINTN Address, - IN UINT32 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAnd32 ((UINTN)GetPciExpressBaseAddress () + Address, AndData); -} - -/** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit - value, followed a bitwise OR with another 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that al= l PCI - read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function a= nd - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressAndThenOr32 ( - IN UINTN Address, - IN UINT32 AndData, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAndThenOr32 ( - (UINTN)GetPciExpressBaseAddress () + Address, - AndData, - OrData - ); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..31. - - @return The value of the bit field read from the PCI configuration regis= ter. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldRead32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldRead32 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit - ); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of t= he - 32-bit register is returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..31. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldWrite32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldWrite32 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - Value - ); -} - -/** - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and - writes the result back to the bit field in the 32-bit port. - - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration registe= r is - returned. This function must guarantee that all PCI read and write opera= tions - are serialized. Extra left bits in OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..31. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldOr32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldOr32 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - OrData - ); -} - -/** - Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise - AND, and writes the result back to the bit field in the 32-bit register. - - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND between the read result and the value specified by AndData, = and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..31. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldAnd32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAnd32 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - AndData - ); -} - -/** - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 32-bit port. - - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that al= l PCI - read and write operations are serialized. Extra left bits in both AndDat= a and - OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit fi= eld. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit fie= ld. - Range 0..31. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldAndThenOr32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAndThenOr32 ( - (UINTN)GetPciExpressBaseAddress () + Address, - StartBit, - EndBit, - AndData, - OrData - ); -} - -/** - Reads a range of PCI configuration registers into a caller supplied buff= er. - - Reads the range of PCI configuration registers specified by StartAddress= and - Size into the buffer specified by Buffer. This function only allows the = PCI - configuration registers from a single PCI function to be read. Size is - returned. When possible 32-bit PCI configuration read cycles are used to= read - from StartAddress to StartAddress + Size. Due to alignment restrictions,= 8-bit - and 16-bit PCI configuration read cycles may be used at the beginning an= d the - end of the range. - - If StartAddress > 0x0FFFFFFF, then ASSERT(). - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). - If Size > 0 and Buffer is NULL, then ASSERT(). - - @param StartAddress The starting address that encodes the PCI Bus, Dev= ice, - Function and Register. - @param Size The size in bytes of the transfer. - @param Buffer The pointer to a buffer receiving the data read. - - @return Size read data from StartAddress. - -**/ -UINTN -EFIAPI -PciExpressReadBuffer ( - IN UINTN StartAddress, - IN UINTN Size, - OUT VOID *Buffer - ) -{ - UINTN ReturnValue; - - ASSERT_INVALID_PCI_ADDRESS (StartAddress); - ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); - - if (Size =3D=3D 0) { - return Size; - } - - ASSERT (Buffer !=3D NULL); - - // - // Save Size for return - // - ReturnValue =3D Size; - - if ((StartAddress & 1) !=3D 0) { - // - // Read a byte if StartAddress is byte aligned - // - *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); - StartAddress +=3D sizeof (UINT8); - Size -=3D sizeof (UINT8); - Buffer =3D (UINT8 *)Buffer + 1; - } - - if ((Size >=3D sizeof (UINT16)) && ((StartAddress & 2) !=3D 0)) { - // - // Read a word if StartAddress is word aligned - // - WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAdd= ress)); - - StartAddress +=3D sizeof (UINT16); - Size -=3D sizeof (UINT16); - Buffer =3D (UINT16 *)Buffer + 1; - } - - while (Size >=3D sizeof (UINT32)) { - // - // Read as many double words as possible - // - WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAdd= ress)); - - StartAddress +=3D sizeof (UINT32); - Size -=3D sizeof (UINT32); - Buffer =3D (UINT32 *)Buffer + 1; - } - - if (Size >=3D sizeof (UINT16)) { - // - // Read the last remaining word if exist - // - WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAdd= ress)); - StartAddress +=3D sizeof (UINT16); - Size -=3D sizeof (UINT16); - Buffer =3D (UINT16 *)Buffer + 1; - } - - if (Size >=3D sizeof (UINT8)) { - // - // Read the last remaining byte if exist - // - *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); - } - - return ReturnValue; -} - -/** - Copies the data in a caller supplied buffer to a specified range of PCI - configuration space. - - Writes the range of PCI configuration registers specified by StartAddres= s and - Size from the buffer specified by Buffer. This function only allows the = PCI - configuration registers from a single PCI function to be written. Size is - returned. When possible 32-bit PCI configuration write cycles are used to - write from StartAddress to StartAddress + Size. Due to alignment restric= tions, - 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning - and the end of the range. - - If StartAddress > 0x0FFFFFFF, then ASSERT(). - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). - If Size > 0 and Buffer is NULL, then ASSERT(). - - @param StartAddress The starting address that encodes the PCI Bus, Dev= ice, - Function and Register. - @param Size The size in bytes of the transfer. - @param Buffer The pointer to a buffer containing the data to wri= te. - - @return Size written to StartAddress. - -**/ -UINTN -EFIAPI -PciExpressWriteBuffer ( - IN UINTN StartAddress, - IN UINTN Size, - IN VOID *Buffer - ) -{ - UINTN ReturnValue; - - ASSERT_INVALID_PCI_ADDRESS (StartAddress); - ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); - - if (Size =3D=3D 0) { - return 0; - } - - ASSERT (Buffer !=3D NULL); - - // - // Save Size for return - // - ReturnValue =3D Size; - - if ((StartAddress & 1) !=3D 0) { - // - // Write a byte if StartAddress is byte aligned - // - PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer); - StartAddress +=3D sizeof (UINT8); - Size -=3D sizeof (UINT8); - Buffer =3D (UINT8 *)Buffer + 1; - } - - if ((Size >=3D sizeof (UINT16)) && ((StartAddress & 2) !=3D 0)) { - // - // Write a word if StartAddress is word aligned - // - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer)); - StartAddress +=3D sizeof (UINT16); - Size -=3D sizeof (UINT16); - Buffer =3D (UINT16 *)Buffer + 1; - } - - while (Size >=3D sizeof (UINT32)) { - // - // Write as many double words as possible - // - PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer)); - StartAddress +=3D sizeof (UINT32); - Size -=3D sizeof (UINT32); - Buffer =3D (UINT32 *)Buffer + 1; - } - - if (Size >=3D sizeof (UINT16)) { - // - // Write the last remaining word if exist - // - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer)); - StartAddress +=3D sizeof (UINT16); - Size -=3D sizeof (UINT16); - Buffer =3D (UINT16 *)Buffer + 1; - } - - if (Size >=3D sizeof (UINT8)) { - // - // Write the last remaining byte if exist - // - PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer); - } - - return ReturnValue; -} --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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